From 1f37b963599eb12d008225707abb8717abc811ca Mon Sep 17 00:00:00 2001 From: CTCaer Date: Mon, 4 Jan 2021 19:03:50 +0200 Subject: [PATCH] coreboot mitigation: Reinstate SD controller power --- bdk/soc/hw_init.c | 9 ++++++--- bdk/soc/hw_init.h | 2 +- 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/bdk/soc/hw_init.c b/bdk/soc/hw_init.c index 64daac1..269a882 100644 --- a/bdk/soc/hw_init.c +++ b/bdk/soc/hw_init.c @@ -419,7 +419,7 @@ void hw_init() bpmp_mmu_enable(); } -void hw_reinit_workaround(bool extra_reconfig, u32 magic) +void hw_reinit_workaround(bool coreboot, u32 magic) { // Disable BPMP max clock. bpmp_clk_rate_set(BPMP_CLK_NORMAL); @@ -443,10 +443,10 @@ void hw_reinit_workaround(bool extra_reconfig, u32 magic) CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_V) |= BIT(CLK_V_AHUB); CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_Y) |= BIT(CLK_Y_APE); - if (extra_reconfig) + // Do coreboot mitigations. + if (coreboot) { msleep(10); - PMC(APBDEV_PMC_PWR_DET_VAL) |= PMC_PWR_DET_SDMMC1_IO_EN; clock_disable_cl_dvfs(); @@ -455,6 +455,9 @@ void hw_reinit_workaround(bool extra_reconfig, u32 magic) gpio_config(GPIO_PORT_D, GPIO_PIN_1, GPIO_MODE_SPIO); gpio_config(GPIO_PORT_E, GPIO_PIN_6, GPIO_MODE_SPIO); gpio_config(GPIO_PORT_H, GPIO_PIN_6, GPIO_MODE_SPIO); + + // Reinstate SD controller power. + PMC(APBDEV_PMC_NO_IOPOWER) &= ~(PMC_NO_IOPOWER_SDMMC1_IO_EN); } // Power off display. diff --git a/bdk/soc/hw_init.h b/bdk/soc/hw_init.h index ff9ae4a..8888824 100644 --- a/bdk/soc/hw_init.h +++ b/bdk/soc/hw_init.h @@ -21,7 +21,7 @@ #include void hw_init(); -void hw_reinit_workaround(bool extra_reconfig, u32 magic); +void hw_reinit_workaround(bool coreboot, u32 magic); u32 hw_get_chip_id(); #endif