mirror of
https://github.com/CTCaer/hekate
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bdk: t210: add more mmio addresses
And simplify relevant drivers that hardcoded them.
This commit is contained in:
CTCaer
parent
0fe17cfb41
commit
1e28320e5a
4 changed files with 161 additions and 139 deletions
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@ -18,6 +18,7 @@
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#include <string.h>
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#include <string.h>
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#include <soc/i2c.h>
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#include <soc/i2c.h>
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#include <soc/t210.h>
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#include <soc/timer.h>
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#include <soc/timer.h>
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#define I2C_PACKET_PROT_I2C BIT(4)
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#define I2C_PACKET_PROT_I2C BIT(4)
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@ -81,14 +82,8 @@
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#define MSTR_CONFIG_LOAD BIT(0)
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#define MSTR_CONFIG_LOAD BIT(0)
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#define TIMEOUT_CONFIG_LOAD BIT(2)
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#define TIMEOUT_CONFIG_LOAD BIT(2)
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static const u32 i2c_addrs[] = {
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/* I2C_1, 2, 3, 4, 5 and 6. */
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0x7000C000, // I2C_1.
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static const u16 _i2c_base_offsets[6] = { 0x0, 0x400, 0x500, 0x700, 0x1000, 0x1100 };
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0x7000C400, // I2C_2.
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0x7000C500, // I2C_3.
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0x7000C700, // I2C_4.
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0x7000D000, // I2C_5.
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0x7000D100 // I2C_6.
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};
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static void _i2c_load_cfg_wait(vu32 *base)
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static void _i2c_load_cfg_wait(vu32 *base)
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{
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{
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@ -108,7 +103,7 @@ static int _i2c_send_single(u32 i2c_idx, u32 dev_addr, u8 *buf, u32 size)
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u32 tmp = 0;
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u32 tmp = 0;
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vu32 *base = (vu32 *)i2c_addrs[i2c_idx];
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vu32 *base = (vu32 *)(I2C_BASE + (u32)_i2c_base_offsets[i2c_idx]);
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// Set device address and send mode.
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// Set device address and send mode.
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base[I2C_CMD_ADDR0] = dev_addr << 1 | ADDR0_WRITE;
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base[I2C_CMD_ADDR0] = dev_addr << 1 | ADDR0_WRITE;
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@ -154,7 +149,7 @@ static int _i2c_recv_single(u32 i2c_idx, u8 *buf, u32 size, u32 dev_addr)
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if (size > 8)
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if (size > 8)
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return 0;
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return 0;
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vu32 *base = (vu32 *)i2c_addrs[i2c_idx];
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vu32 *base = (vu32 *)(I2C_BASE + (u32)_i2c_base_offsets[i2c_idx]);
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// Set device address and recv mode.
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// Set device address and recv mode.
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base[I2C_CMD_ADDR0] = (dev_addr << 1) | ADDR0_READ;
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base[I2C_CMD_ADDR0] = (dev_addr << 1) | ADDR0_READ;
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@ -198,7 +193,7 @@ static int _i2c_send_pkt(u32 i2c_idx, u8 *buf, u32 size, u32 dev_addr)
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int res = 0;
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int res = 0;
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vu32 *base = (vu32 *)i2c_addrs[i2c_idx];
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vu32 *base = (vu32 *)(I2C_BASE + (u32)_i2c_base_offsets[i2c_idx]);
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// Enable interrupts.
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// Enable interrupts.
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base[I2C_INT_EN] = ALL_PACKETS_COMPLETE | PACKET_COMPLETE | NO_ACK |
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base[I2C_INT_EN] = ALL_PACKETS_COMPLETE | PACKET_COMPLETE | NO_ACK |
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@ -270,7 +265,7 @@ static int _i2c_recv_pkt(u32 i2c_idx, u8 *buf, u32 size, u32 dev_addr, u32 reg)
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int res = 0;
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int res = 0;
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vu32 *base = (vu32 *)i2c_addrs[i2c_idx];
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vu32 *base = (vu32 *)(I2C_BASE + (u32)_i2c_base_offsets[i2c_idx]);
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// Enable interrupts.
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// Enable interrupts.
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base[I2C_INT_EN] = ALL_PACKETS_COMPLETE | PACKET_COMPLETE | NO_ACK |
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base[I2C_INT_EN] = ALL_PACKETS_COMPLETE | PACKET_COMPLETE | NO_ACK |
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@ -352,7 +347,7 @@ static int _i2c_recv_pkt(u32 i2c_idx, u8 *buf, u32 size, u32 dev_addr, u32 reg)
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void i2c_init(u32 i2c_idx)
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void i2c_init(u32 i2c_idx)
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{
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{
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vu32 *base = (vu32 *)i2c_addrs[i2c_idx];
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vu32 *base = (vu32 *)(I2C_BASE + (u32)_i2c_base_offsets[i2c_idx]);
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base[I2C_CLK_DIVISOR] = (5 << 16) | 1; // SF mode Div: 6, HS mode div: 2.
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base[I2C_CLK_DIVISOR] = (5 << 16) | 1; // SF mode Div: 6, HS mode div: 2.
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base[I2C_BUS_CLEAR_CONFIG] = (9 << 16) | BC_TERMINATE | BC_ENABLE;
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base[I2C_BUS_CLEAR_CONFIG] = (9 << 16) | BC_TERMINATE | BC_ENABLE;
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162
bdk/soc/t210.h
162
bdk/soc/t210.h
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@ -20,17 +20,27 @@
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#include <utils/types.h>
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#include <utils/types.h>
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#define BOOTROM_BASE 0x100000
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#define IROM_BASE 0x100000
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#define IRAM_BASE 0x40000000
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#define IRAM_BASE 0x40000000
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#define HOST1X_BASE 0x50000000
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#define HOST1X_BASE 0x50000000
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#define BPMP_CACHE_BASE 0x50040000
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#define BPMP_CACHE_BASE 0x50040000
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#define MSELECT_BASE 0x50060000
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#define DPAUX1_BASE 0x54040000
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#define TSEC2_BASE 0x54100000
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#define DISPLAY_A_BASE 0x54200000
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#define DISPLAY_A_BASE 0x54200000
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#define DISPLAY_B_BASE 0x54240000
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#define DSI_BASE 0x54300000
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#define DSI_BASE 0x54300000
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#define VIC_BASE 0x54340000
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#define VIC_BASE 0x54340000
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#define NVJPG_BASE 0x54380000
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#define NVDEC_BASE 0x54480000
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#define NVDEC_BASE 0x54480000
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#define NVENC_BASE 0x544C0000
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#define TSEC_BASE 0x54500000
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#define TSEC_BASE 0x54500000
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#define SOR1_BASE 0x54580000
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#define SOR1_BASE 0x54580000
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#define MSELECT_BASE 0x50060000
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#define GPU_BASE 0x57000000
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#define GPU_USER_BASE 0x58000000
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#define RES_SEMAPH_BASE 0x60001000
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#define ARB_SEMAPH_BASE 0x60002000
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#define ARBPRI_BASE 0x60003000
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#define ICTLR_BASE 0x60004000
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#define ICTLR_BASE 0x60004000
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#define TMR_BASE 0x60005000
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#define TMR_BASE 0x60005000
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#define CLOCK_BASE 0x60006000
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#define CLOCK_BASE 0x60006000
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@ -40,27 +50,22 @@
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#define SB_BASE (SYSREG_BASE + 0x200)
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#define SB_BASE (SYSREG_BASE + 0x200)
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#define ACTMON_BASE 0x6000C800
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#define ACTMON_BASE 0x6000C800
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#define GPIO_BASE 0x6000D000
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#define GPIO_BASE 0x6000D000
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#define GPIO_1_BASE (GPIO_BASE)
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#define GPIO_2_BASE (GPIO_BASE + 0x100)
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#define GPIO_3_BASE (GPIO_BASE + 0x200)
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#define GPIO_4_BASE (GPIO_BASE + 0x300)
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#define GPIO_5_BASE (GPIO_BASE + 0x400)
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#define GPIO_6_BASE (GPIO_BASE + 0x500)
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#define GPIO_7_BASE (GPIO_BASE + 0x600)
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#define GPIO_8_BASE (GPIO_BASE + 0x700)
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#define EXCP_VEC_BASE 0x6000F000
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#define EXCP_VEC_BASE 0x6000F000
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#define IPATCH_BASE 0x6001DC00
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#define IPATCH_BASE 0x6001DC00
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#define APBDMA_BASE 0x60020000
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#define APBDMA_BASE 0x60020000
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#define VGPIO_BASE 0x60024000
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#define APB_MISC_BASE 0x70000000
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#define APB_MISC_BASE 0x70000000
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#define PINMUX_AUX_BASE 0x70003000
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#define PINMUX_AUX_BASE 0x70003000
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#define UART_BASE 0x70006000
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#define UART_BASE 0x70006000
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#define PWM_BASE 0x7000A000
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#define PWM_BASE 0x7000A000
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#define I2C_BASE 0x7000C000
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#define RTC_BASE 0x7000E000
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#define RTC_BASE 0x7000E000
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#define PMC_BASE 0x7000E400
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#define PMC_BASE 0x7000E400
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#define SYSCTR0_BASE 0x700F0000
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#define FUSE_BASE 0x7000F800
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#define FUSE_BASE 0x7000F800
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#define KFUSE_BASE 0x7000FC00
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#define KFUSE_BASE 0x7000FC00
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#define SE_BASE 0x70012000
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#define SE_BASE 0x70012000
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#define TSENSOR_BASE 0x70014000
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#define ATOMICS_BASE 0x70016000
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#define MC_BASE 0x70019000
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#define MC_BASE 0x70019000
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#define EMC_BASE 0x7001B000
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#define EMC_BASE 0x7001B000
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#define EMC0_BASE 0x7001E000
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#define EMC0_BASE 0x7001E000
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@ -68,72 +73,87 @@
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#define XUSB_HOST_BASE 0x70090000
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#define XUSB_HOST_BASE 0x70090000
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#define XUSB_PADCTL_BASE 0x7009F000
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#define XUSB_PADCTL_BASE 0x7009F000
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#define XUSB_DEV_BASE 0x700D0000
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#define XUSB_DEV_BASE 0x700D0000
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#define SDMMC_BASE 0x700B0000
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#define SOC_THERM_BASE 0x700E2000
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#define MIPI_CAL_BASE 0x700E3000
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#define MIPI_CAL_BASE 0x700E3000
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#define SYSCTR0_BASE 0x700F0000
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#define SYSCTR1_BASE 0x70100000
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#define CL_DVFS_BASE 0x70110000
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#define CL_DVFS_BASE 0x70110000
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#define APE_BASE 0x702C0000
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#define AHUB_BASE 0x702D0000
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#define AXBAR_BASE 0x702D0800
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#define I2S_BASE 0x702D1000
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#define I2S_BASE 0x702D1000
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#define ADMA_BASE 0x702E2000
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#define ADMA_BASE 0x702E2000
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#define SE2_BASE 0x70412000
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#define SE_PKA1_BASE 0x70420000
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#define TZRAM_BASE 0x7C010000
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#define TZRAM_BASE 0x7C010000
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#define TZRAM_SIZE 0x10000
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#define TZRAM_SIZE 0x10000
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#define TZRAM_T210B01_SIZE 0x3C000
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#define TZRAM_T210B01_SIZE 0x3C000
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#define USB_BASE 0x7D000000
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#define USB_BASE 0x7D000000
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#define USB_OTG_BASE USB_BASE
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#define USB_OTG_BASE USB_BASE
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#define USB1_BASE 0x7D004000
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#define USB1_BASE 0x7D004000
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#define EMEM_BASE 0x80000000
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#define _REG(base, off) *(vu32 *)((base) + (off))
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#define MMIO_REG32(base, off) *(vu32 *)((base) + (off))
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#define HOST1X(off) _REG(HOST1X_BASE, off)
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#define HOST1X(off) MMIO_REG32(HOST1X_BASE, off)
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#define BPMP_CACHE_CTRL(off) _REG(BPMP_CACHE_BASE, off)
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#define BPMP_CACHE_CTRL(off) MMIO_REG32(BPMP_CACHE_BASE, off)
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#define DISPLAY_A(off) _REG(DISPLAY_A_BASE, off)
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#define MSELECT(off) MMIO_REG32(MSELECT_BASE, off)
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#define DSI(off) _REG(DSI_BASE, off)
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#define DPAUX1(off) MMIO_REG32(DPAUX1_BASE, off)
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#define VIC(off) _REG(VIC_BASE, off)
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#define TSEC2(off) MMIO_REG32(TSEC2_BASE, off)
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#define NVDEC(off) _REG(NVDEC_BASE, off)
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#define DISPLAY_A(off) MMIO_REG32(DISPLAY_A_BASE, off)
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#define TSEC(off) _REG(TSEC_BASE, off)
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#define DISPLAY_B(off) MMIO_REG32(DISPLAY_B_BASE, off)
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#define SOR1(off) _REG(SOR1_BASE, off)
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#define DSI(off) MMIO_REG32(DSI_BASE, off)
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#define MSELECT(off) _REG(MSELECT_BASE, off)
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#define VIC(off) MMIO_REG32(VIC_BASE, off)
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#define ICTLR(cidx, off) _REG(ICTLR_BASE + (0x100 * (cidx)), off)
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#define NVJPG(off) MMIO_REG32(NVJPG_BASE, off)
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#define TMR(off) _REG(TMR_BASE, off)
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#define NVDEC(off) MMIO_REG32(NVDEC_BASE, off)
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#define CLOCK(off) _REG(CLOCK_BASE, off)
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#define NVENC(off) MMIO_REG32(NVENC_BASE, off)
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#define FLOW_CTLR(off) _REG(FLOW_CTLR_BASE, off)
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#define TSEC(off) MMIO_REG32(TSEC_BASE, off)
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#define SYSREG(off) _REG(SYSREG_BASE, off)
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#define SOR1(off) MMIO_REG32(SOR1_BASE, off)
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#define AHB_GIZMO(off) _REG(SYSREG_BASE, off)
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#define GPU(off) MMIO_REG32(GPU_BASE, off)
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#define SB(off) _REG(SB_BASE, off)
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#define GPU_USER(off) MMIO_REG32(GPU_USER_BASE, off)
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#define ACTMON(off) _REG(ACTMON_BASE, off)
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#define ICTLR(cidx, off) MMIO_REG32(ICTLR_BASE + (0x100 * (cidx)), off)
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#define GPIO(off) _REG(GPIO_BASE, off)
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#define TMR(off) MMIO_REG32(TMR_BASE, off)
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#define GPIO_1(off) _REG(GPIO_1_BASE, off)
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#define CLOCK(off) MMIO_REG32(CLOCK_BASE, off)
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#define GPIO_2(off) _REG(GPIO_2_BASE, off)
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#define FLOW_CTLR(off) MMIO_REG32(FLOW_CTLR_BASE, off)
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#define GPIO_3(off) _REG(GPIO_3_BASE, off)
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#define AHBDMA(off) MMIO_REG32(AHBDMA_BASE, off)
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#define GPIO_4(off) _REG(GPIO_4_BASE, off)
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#define SYSREG(off) MMIO_REG32(SYSREG_BASE, off)
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#define GPIO_5(off) _REG(GPIO_5_BASE, off)
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#define AHB_GIZMO(off) MMIO_REG32(SYSREG_BASE, off)
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#define GPIO_6(off) _REG(GPIO_6_BASE, off)
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#define SB(off) MMIO_REG32(SB_BASE, off)
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#define GPIO_7(off) _REG(GPIO_7_BASE, off)
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#define ACTMON(off) MMIO_REG32(ACTMON_BASE, off)
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#define GPIO_8(off) _REG(GPIO_8_BASE, off)
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#define GPIO(off) MMIO_REG32(GPIO_BASE, off)
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#define EXCP_VEC(off) _REG(EXCP_VEC_BASE, off)
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#define EXCP_VEC(off) MMIO_REG32(EXCP_VEC_BASE, off)
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#define APB_MISC(off) _REG(APB_MISC_BASE, off)
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#define APBDMA(off) MMIO_REG32(APBDMA_BASE, off)
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#define PINMUX_AUX(off) _REG(PINMUX_AUX_BASE, off)
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#define VGPIO(off) MMIO_REG32(VGPIO_BASE, off)
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#define PWM(off) _REG(PWM_BASE, off)
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#define APB_MISC(off) MMIO_REG32(APB_MISC_BASE, off)
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#define RTC(off) _REG(RTC_BASE, off)
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#define PINMUX_AUX(off) MMIO_REG32(PINMUX_AUX_BASE, off)
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#define PMC(off) _REG(PMC_BASE, off)
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#define PWM(off) MMIO_REG32(PWM_BASE, off)
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#define SYSCTR0(off) _REG(SYSCTR0_BASE, off)
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#define RTC(off) MMIO_REG32(RTC_BASE, off)
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#define FUSE(off) _REG(FUSE_BASE, off)
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#define PMC(off) MMIO_REG32(PMC_BASE, off)
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#define KFUSE(off) _REG(KFUSE_BASE, off)
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#define SYSCTR0(off) MMIO_REG32(SYSCTR0_BASE, off)
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#define SE(off) _REG(SE_BASE, off)
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#define SYSCTR1(off) MMIO_REG32(SYSCTR1_BASE, off)
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#define MC(off) _REG(MC_BASE, off)
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#define FUSE(off) MMIO_REG32(FUSE_BASE, off)
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#define EMC(off) _REG(EMC_BASE, off)
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#define KFUSE(off) MMIO_REG32(KFUSE_BASE, off)
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#define EMC_CH0(off) _REG(EMC0_BASE, off)
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#define SE(off) MMIO_REG32(SE_BASE, off)
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#define EMC_CH1(off) _REG(EMC1_BASE, off)
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#define MC(off) MMIO_REG32(MC_BASE, off)
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#define XUSB_HOST(off) _REG(XUSB_HOST_BASE, off)
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#define EMC(off) MMIO_REG32(EMC_BASE, off)
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#define XUSB_PADCTL(off) _REG(XUSB_PADCTL_BASE, off)
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#define EMC_CH0(off) MMIO_REG32(EMC0_BASE, off)
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#define XUSB_DEV(off) _REG(XUSB_DEV_BASE, off)
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#define EMC_CH1(off) MMIO_REG32(EMC1_BASE, off)
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#define XUSB_DEV_XHCI(off) _REG(XUSB_DEV_BASE, off)
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#define XUSB_HOST(off) MMIO_REG32(XUSB_HOST_BASE, off)
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#define XUSB_DEV_PCI(off) _REG(XUSB_DEV_BASE + 0x8000, off)
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#define XUSB_PADCTL(off) MMIO_REG32(XUSB_PADCTL_BASE, off)
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#define XUSB_DEV_DEV(off) _REG(XUSB_DEV_BASE + 0x9000, off)
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#define XUSB_DEV(off) MMIO_REG32(XUSB_DEV_BASE, off)
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#define MIPI_CAL(off) _REG(MIPI_CAL_BASE, off)
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#define XUSB_DEV_XHCI(off) MMIO_REG32(XUSB_DEV_BASE, off)
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#define CL_DVFS(off) _REG(CL_DVFS_BASE, off)
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#define XUSB_DEV_PCI(off) MMIO_REG32(XUSB_DEV_BASE + 0x8000, off)
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#define I2S(off) _REG(I2S_BASE, off)
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#define XUSB_DEV_DEV(off) MMIO_REG32(XUSB_DEV_BASE + 0x9000, off)
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#define ADMA(off) _REG(ADMA_BASE, off)
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#define MIPI_CAL(off) MMIO_REG32(MIPI_CAL_BASE, off)
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#define USB(off) _REG(USB_BASE, off)
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#define CL_DVFS(off) MMIO_REG32(CL_DVFS_BASE, off)
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||||||
#define USB1(off) _REG(USB1_BASE, off)
|
#define I2S(off) MMIO_REG32(I2S_BASE, off)
|
||||||
#define TEST_REG(off) _REG(0x0, off)
|
#define ADMA(off) MMIO_REG32(ADMA_BASE, off)
|
||||||
|
#define SE2(off) MMIO_REG32(SE2_BASE, off)
|
||||||
|
#define SE_PKA1(off) MMIO_REG32(SE_PKA1_BASE, off)
|
||||||
|
#define USB(off) MMIO_REG32(USB_BASE, off)
|
||||||
|
#define USB1(off) MMIO_REG32(USB1_BASE, off)
|
||||||
|
#define TEST_REG(off) MMIO_REG32(0x0, off)
|
||||||
|
|
||||||
/* HOST1X v3 registers. */
|
/* HOST1X v3 registers. */
|
||||||
#define HOST1X_CH0_SYNC_BASE 0x2100
|
#define HOST1X_CH0_SYNC_BASE 0x2100
|
||||||
|
|
@ -205,6 +225,12 @@
|
||||||
#define GP_HIDREV_MAJOR_T210 0x1
|
#define GP_HIDREV_MAJOR_T210 0x1
|
||||||
#define GP_HIDREV_MAJOR_T210B01 0x2
|
#define GP_HIDREV_MAJOR_T210B01 0x2
|
||||||
#define APB_MISC_GP_ASDBGREG 0x810
|
#define APB_MISC_GP_ASDBGREG 0x810
|
||||||
|
#define APB_MISC_GP_TRANSACTOR_SCRATCH 0x864
|
||||||
|
#define APB_MISC_GP_AVP_TRANSACTOR_SCRATCH 0x880
|
||||||
|
#define APB_MISC_GP_CPU0_TRANSACTOR_SCRATCH 0x884
|
||||||
|
#define APB_MISC_GP_CPU1_TRANSACTOR_SCRATCH 0x888
|
||||||
|
#define APB_MISC_GP_CPU2_TRANSACTOR_SCRATCH 0x88C
|
||||||
|
#define APB_MISC_GP_CPU3_TRANSACTOR_SCRATCH 0x890
|
||||||
#define APB_MISC_GP_AUD_MCLK_CFGPADCTRL 0x8F4
|
#define APB_MISC_GP_AUD_MCLK_CFGPADCTRL 0x8F4
|
||||||
#define APB_MISC_GP_LCD_BL_PWM_CFGPADCTRL 0xA34
|
#define APB_MISC_GP_LCD_BL_PWM_CFGPADCTRL 0xA34
|
||||||
#define APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL 0xA98
|
#define APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL 0xA98
|
||||||
|
|
@ -252,6 +278,12 @@
|
||||||
#define SYSCTR0_COUNTERID10 0xFF8
|
#define SYSCTR0_COUNTERID10 0xFF8
|
||||||
#define SYSCTR0_COUNTERID11 0xFFC
|
#define SYSCTR0_COUNTERID11 0xFFC
|
||||||
|
|
||||||
|
/*! IPATCH registers. */
|
||||||
|
#define IPATCH_CAM_VALID 0x0
|
||||||
|
#define IPATCH_CAM_BASE 0x4
|
||||||
|
#define IPATCH_CAM(i) (IPATCH_CAM_BASE + (i) * 4)
|
||||||
|
#define IPATCH_CAM_ENTRIES 12
|
||||||
|
|
||||||
/*! I2S registers. */
|
/*! I2S registers. */
|
||||||
#define I2S1_CG 0x88
|
#define I2S1_CG 0x88
|
||||||
#define I2S1_CTRL 0xA0
|
#define I2S1_CTRL 0xA0
|
||||||
|
|
|
||||||
|
|
@ -21,11 +21,11 @@
|
||||||
#include <soc/t210.h>
|
#include <soc/t210.h>
|
||||||
|
|
||||||
/* UART A, B, C, D and E. */
|
/* UART A, B, C, D and E. */
|
||||||
static const u32 uart_baseoff[5] = { 0, 0x40, 0x200, 0x300, 0x400 };
|
static const u16 _uart_base_offsets[5] = { 0, 0x40, 0x200, 0x300, 0x400 };
|
||||||
|
|
||||||
void uart_init(u32 idx, u32 baud, u32 mode)
|
void uart_init(u32 idx, u32 baud, u32 mode)
|
||||||
{
|
{
|
||||||
uart_t *uart = (uart_t *)(UART_BASE + uart_baseoff[idx]);
|
uart_t *uart = (uart_t *)(UART_BASE + (u32)_uart_base_offsets[idx]);
|
||||||
|
|
||||||
// Make sure no data is being sent.
|
// Make sure no data is being sent.
|
||||||
if (!(mode & (UART_MCR_CTS_EN | UART_MCR_DTR)))
|
if (!(mode & (UART_MCR_CTS_EN | UART_MCR_DTR)))
|
||||||
|
|
@ -70,7 +70,7 @@ void uart_init(u32 idx, u32 baud, u32 mode)
|
||||||
|
|
||||||
void uart_wait_xfer(u32 idx, u32 which)
|
void uart_wait_xfer(u32 idx, u32 which)
|
||||||
{
|
{
|
||||||
uart_t *uart = (uart_t *)(UART_BASE + uart_baseoff[idx]);
|
uart_t *uart = (uart_t *)(UART_BASE + (u32)_uart_base_offsets[idx]);
|
||||||
if (UART_TX_IDLE & which)
|
if (UART_TX_IDLE & which)
|
||||||
{
|
{
|
||||||
while (!(uart->UART_LSR & UART_LSR_TMTY))
|
while (!(uart->UART_LSR & UART_LSR_TMTY))
|
||||||
|
|
@ -85,7 +85,7 @@ void uart_wait_xfer(u32 idx, u32 which)
|
||||||
|
|
||||||
void uart_send(u32 idx, const u8 *buf, u32 len)
|
void uart_send(u32 idx, const u8 *buf, u32 len)
|
||||||
{
|
{
|
||||||
uart_t *uart = (uart_t *)(UART_BASE + uart_baseoff[idx]);
|
uart_t *uart = (uart_t *)(UART_BASE + (u32)_uart_base_offsets[idx]);
|
||||||
|
|
||||||
for (u32 i = 0; i != len; i++)
|
for (u32 i = 0; i != len; i++)
|
||||||
{
|
{
|
||||||
|
|
@ -97,7 +97,7 @@ void uart_send(u32 idx, const u8 *buf, u32 len)
|
||||||
|
|
||||||
u32 uart_recv(u32 idx, u8 *buf, u32 len)
|
u32 uart_recv(u32 idx, u8 *buf, u32 len)
|
||||||
{
|
{
|
||||||
uart_t *uart = (uart_t *)(UART_BASE + uart_baseoff[idx]);
|
uart_t *uart = (uart_t *)(UART_BASE + (u32)_uart_base_offsets[idx]);
|
||||||
bool manual_mode = uart->UART_MCR & UART_MCR_RTS;
|
bool manual_mode = uart->UART_MCR & UART_MCR_RTS;
|
||||||
u32 timeout = get_tmr_us() + 250;
|
u32 timeout = get_tmr_us() + 250;
|
||||||
u32 i;
|
u32 i;
|
||||||
|
|
@ -127,7 +127,7 @@ out:
|
||||||
|
|
||||||
void uart_invert(u32 idx, bool enable, u32 invert_mask)
|
void uart_invert(u32 idx, bool enable, u32 invert_mask)
|
||||||
{
|
{
|
||||||
uart_t *uart = (uart_t *)(UART_BASE + uart_baseoff[idx]);
|
uart_t *uart = (uart_t *)(UART_BASE + (u32)_uart_base_offsets[idx]);
|
||||||
|
|
||||||
if (enable)
|
if (enable)
|
||||||
uart->UART_IRDA_CSR |= invert_mask;
|
uart->UART_IRDA_CSR |= invert_mask;
|
||||||
|
|
@ -138,7 +138,7 @@ void uart_invert(u32 idx, bool enable, u32 invert_mask)
|
||||||
|
|
||||||
void uart_set_mode(u32 idx, u32 mode)
|
void uart_set_mode(u32 idx, u32 mode)
|
||||||
{
|
{
|
||||||
uart_t *uart = (uart_t *)(UART_BASE + uart_baseoff[idx]);
|
uart_t *uart = (uart_t *)(UART_BASE + (u32)_uart_base_offsets[idx]);
|
||||||
|
|
||||||
uart->UART_MCR = mode;
|
uart->UART_MCR = mode;
|
||||||
(void)uart->UART_SPR;
|
(void)uart->UART_SPR;
|
||||||
|
|
@ -146,7 +146,7 @@ void uart_set_mode(u32 idx, u32 mode)
|
||||||
|
|
||||||
u32 uart_get_IIR(u32 idx)
|
u32 uart_get_IIR(u32 idx)
|
||||||
{
|
{
|
||||||
uart_t *uart = (uart_t *)(UART_BASE + uart_baseoff[idx]);
|
uart_t *uart = (uart_t *)(UART_BASE + (u32)_uart_base_offsets[idx]);
|
||||||
|
|
||||||
u32 iir = uart->UART_IIR_FCR & UART_IIR_INT_MASK;
|
u32 iir = uart->UART_IIR_FCR & UART_IIR_INT_MASK;
|
||||||
|
|
||||||
|
|
@ -158,7 +158,7 @@ u32 uart_get_IIR(u32 idx)
|
||||||
|
|
||||||
void uart_set_IIR(u32 idx)
|
void uart_set_IIR(u32 idx)
|
||||||
{
|
{
|
||||||
uart_t *uart = (uart_t *)(UART_BASE + uart_baseoff[idx]);
|
uart_t *uart = (uart_t *)(UART_BASE + (u32)_uart_base_offsets[idx]);
|
||||||
|
|
||||||
uart->UART_IER_DLAB &= ~UART_IER_DLAB_IE_EORD;
|
uart->UART_IER_DLAB &= ~UART_IER_DLAB_IE_EORD;
|
||||||
(void)uart->UART_SPR;
|
(void)uart->UART_SPR;
|
||||||
|
|
@ -168,7 +168,7 @@ void uart_set_IIR(u32 idx)
|
||||||
|
|
||||||
void uart_empty_fifo(u32 idx, u32 which)
|
void uart_empty_fifo(u32 idx, u32 which)
|
||||||
{
|
{
|
||||||
uart_t *uart = (uart_t *)(UART_BASE + uart_baseoff[idx]);
|
uart_t *uart = (uart_t *)(UART_BASE + (u32)_uart_base_offsets[idx]);
|
||||||
|
|
||||||
uart->UART_MCR = 0;
|
uart->UART_MCR = 0;
|
||||||
(void)uart->UART_SPR;
|
(void)uart->UART_SPR;
|
||||||
|
|
|
||||||
|
|
@ -39,12 +39,7 @@
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/*! SCMMC controller base addresses. */
|
/*! SCMMC controller base addresses. */
|
||||||
static const u32 _sdmmc_bases[4] = {
|
static const u16 _sdmmc_base_offsets[4] = { 0x0, 0x200, 0x400, 0x600 };
|
||||||
0x700B0000,
|
|
||||||
0x700B0200,
|
|
||||||
0x700B0400,
|
|
||||||
0x700B0600,
|
|
||||||
};
|
|
||||||
|
|
||||||
int sdmmc_get_io_power(sdmmc_t *sdmmc)
|
int sdmmc_get_io_power(sdmmc_t *sdmmc)
|
||||||
{
|
{
|
||||||
|
|
@ -1380,7 +1375,7 @@ int sdmmc_init(sdmmc_t *sdmmc, u32 id, u32 power, u32 bus_width, u32 type)
|
||||||
|
|
||||||
memset(sdmmc, 0, sizeof(sdmmc_t));
|
memset(sdmmc, 0, sizeof(sdmmc_t));
|
||||||
|
|
||||||
sdmmc->regs = (t210_sdmmc_t *)_sdmmc_bases[id];
|
sdmmc->regs = (t210_sdmmc_t *)(SDMMC_BASE + (u32)_sdmmc_base_offsets[id]);
|
||||||
sdmmc->id = id;
|
sdmmc->id = id;
|
||||||
sdmmc->clock_stopped = 1;
|
sdmmc->clock_stopped = 1;
|
||||||
sdmmc->t210b01 = hw_get_chip_id() == GP_HIDREV_MAJOR_T210B01;
|
sdmmc->t210b01 = hw_get_chip_id() == GP_HIDREV_MAJOR_T210B01;
|
||||||
|
|
|
||||||
Loading…
Reference in a new issue