bdk: minerva: add emc src div disable

bdk/mem/emc.h

@@ -2,7 +2,7 @@
  * arch/arm/mach-tegra/tegra21_emc.h
  *
  * Copyright (c) 2014-2015, NVIDIA CORPORATION.  All rights reserved.
- * Copyright (c) 2019-2020, CTCaer.
+ * Copyright (c) 2019-2024, CTCaer.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -23,6 +23,7 @@
 #ifndef _EMC_H_
 #define _EMC_H_
 
+#define EMC_INTSTATUS                             0x0
 #define EMC_DBG                                   0x8
 #define EMC_CFG                                   0xC
 #define EMC_CONFIG_SAMPLE_DELAY                   0x5f0

bdk/mem/sdram.c

@@ -184,6 +184,41 @@ emc_mr_data_t sdram_read_mrx(emc_mr_t mrx)
 	return data;
 }
 
+void sdram_div_disable(bool enable)
+{
+	static bool enabled = false;
+
+	if (hw_get_chip_id() == GP_HIDREV_MAJOR_T210 && enable == enabled)
+		return;
+
+	enabled = enable;
+
+	// Clear CC interrupt.
+	EMC(EMC_INTSTATUS) = BIT(4);
+	(void)EMC(EMC_INTSTATUS);
+
+	u32 clk_src_emc = _dram_cfg_08_10_12_14_samsung_hynix_4gb.emc_clock_source;
+
+	if (enable)
+	{
+		// Check if clock source is not the expected one.
+		if (CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_EMC) != clk_src_emc)
+			return;
+
+		// Clear div.
+		CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_EMC) = clk_src_emc & ~0xF;
+	}
+	else
+	{
+		// Restore MC/EMC clock.
+		CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_EMC) = clk_src_emc;
+	}
+
+	// Wait for CC interrupt.
+	while (!(EMC(EMC_INTSTATUS) & BIT(4)))
+		;
+}
+
 static void _sdram_config_t210(const sdram_params_t210_t *params)
 {
 	// Program DPD3/DPD4 regs (coldboot path).

bdk/mem/sdram.h

@@ -135,6 +135,7 @@ void sdram_init();
 void *sdram_get_params_patched();
 void *sdram_get_params_t210b01();
 void sdram_lp0_save_params(const void *params);
+void sdram_div_disable(bool enable);
 emc_mr_data_t sdram_read_mrx(emc_mr_t mrx);
 
 #endif