From 138da26a9ab54914289535c2dec7170b7cc21d40 Mon Sep 17 00:00:00 2001 From: "ctcaer@gmail.com" Date: Sat, 6 Jul 2019 22:22:47 +0300 Subject: [PATCH] [BPMP] Fix cache coherency issues + Fix framebuffer memfetcher for some SoC revisions. --- bootloader/soc/bpmp.c | 13 +++++++------ nyx/nyx_gui/soc/bpmp.c | 11 ++++++----- 2 files changed, 13 insertions(+), 11 deletions(-) diff --git a/bootloader/soc/bpmp.c b/bootloader/soc/bpmp.c index 4615c36..1794696 100644 --- a/bootloader/soc/bpmp.c +++ b/bootloader/soc/bpmp.c @@ -83,15 +83,15 @@ void bpmp_mmu_maintenance(u32 op) if (!(BPMP_CACHE_CTRL(BPMP_CACHE_CONFIG) & CFG_ENABLE)) return; - //BPMP_CACHE_CTRL(BPMP_CACHE_INT_CLEAR) = INT_CLR_MAINT_DONE; + BPMP_CACHE_CTRL(BPMP_CACHE_INT_CLEAR) = INT_CLR_MAINT_DONE; // This is a blocking operation. BPMP_CACHE_CTRL(BPMP_CACHE_MAINT_REQ) = MAINT_REQ_WAY_BITMAP(0xF) | op; - //while(!(BPMP_CACHE_CTRL(BPMP_CACHE_INT_RAW_EVENT) & INT_RAW_EVENT_MAINT_DONE)) - // ; + while(!(BPMP_CACHE_CTRL(BPMP_CACHE_INT_RAW_EVENT) & INT_RAW_EVENT_MAINT_DONE)) + ; - //BPMP_CACHE_CTRL(BPMP_CACHE_INT_CLEAR) = BPMP_CACHE_CTRL(BPMP_CACHE_INT_RAW_EVENT); + BPMP_CACHE_CTRL(BPMP_CACHE_INT_CLEAR) = BPMP_CACHE_CTRL(BPMP_CACHE_INT_RAW_EVENT); } void bpmp_mmu_set_entry(int idx, bpmp_mmu_entry_t *entry, bool apply) @@ -156,11 +156,12 @@ void bpmp_mmu_disable() bpmp_mmu_maintenance(BPMP_MMU_MAINT_INVALID_WAY); } -static u8 pllc4_divn[] = { +const u8 pllc4_divn[] = { 0, // BPMP_CLK_NORMAL: 408MHz 0% - 136MHz APB. 85, // BPMP_CLK_LOW_BOOST: 544MHz 33% - 136MHz APB. 90, // BPMP_CLK_MID_BOOST: 576MHz 41% - 144MHz APB. - 95 // BPMP_CLK_SUPER_BOOST: 608MHz 49% - 152MHz APB. + 94 // BPMP_CLK_SUPER_BOOST: 602MHz 48% - 150MHz APB. + //95 // BPMP_CLK_SUPER_BOOST: 608MHz 49% - 152MHz APB. }; bpmp_freq_t bpmp_clock_set = BPMP_CLK_NORMAL; diff --git a/nyx/nyx_gui/soc/bpmp.c b/nyx/nyx_gui/soc/bpmp.c index a0551d1..b5a8f07 100644 --- a/nyx/nyx_gui/soc/bpmp.c +++ b/nyx/nyx_gui/soc/bpmp.c @@ -86,15 +86,15 @@ void bpmp_mmu_maintenance(u32 op) if (!(BPMP_CACHE_CTRL(BPMP_CACHE_CONFIG) & CFG_ENABLE)) return; - //BPMP_CACHE_CTRL(BPMP_CACHE_INT_CLEAR) = INT_CLR_MAINT_DONE; + BPMP_CACHE_CTRL(BPMP_CACHE_INT_CLEAR) = INT_CLR_MAINT_DONE; // This is a blocking operation. BPMP_CACHE_CTRL(BPMP_CACHE_MAINT_REQ) = MAINT_REQ_WAY_BITMAP(0xF) | op; - //while(!(BPMP_CACHE_CTRL(BPMP_CACHE_INT_RAW_EVENT) & INT_RAW_EVENT_MAINT_DONE)) - // ; + while(!(BPMP_CACHE_CTRL(BPMP_CACHE_INT_RAW_EVENT) & INT_RAW_EVENT_MAINT_DONE)) + ; - //BPMP_CACHE_CTRL(BPMP_CACHE_INT_CLEAR) = BPMP_CACHE_CTRL(BPMP_CACHE_INT_RAW_EVENT); + BPMP_CACHE_CTRL(BPMP_CACHE_INT_CLEAR) = BPMP_CACHE_CTRL(BPMP_CACHE_INT_RAW_EVENT); } void bpmp_mmu_set_entry(int idx, bpmp_mmu_entry_t *entry, bool apply) @@ -163,7 +163,8 @@ const u8 pllc4_divn[] = { 0, // BPMP_CLK_NORMAL: 408MHz 0% - 136MHz APB. 85, // BPMP_CLK_LOW_BOOST: 544MHz 33% - 136MHz APB. 90, // BPMP_CLK_MID_BOOST: 576MHz 41% - 144MHz APB. - 95 // BPMP_CLK_SUPER_BOOST: 608MHz 49% - 152MHz APB. + 94 // BPMP_CLK_SUPER_BOOST: 602MHz 48% - 150MHz APB. + //95 // BPMP_CLK_SUPER_BOOST: 608MHz 49% - 152MHz APB. }; bpmp_freq_t bpmp_clock_set = BPMP_CLK_NORMAL;