From 10b479dc1c403980b599785edc30a2930d97dfae Mon Sep 17 00:00:00 2001
From: CTCaer <ctcaer@gmail.com>
Date: Thu, 20 Jan 2022 12:32:57 +0200
Subject: [PATCH] bdk: clock: add apb/ahb clock control

---
 bdk/soc/clock.c | 28 ++++++++++++++++++++++++++++
 bdk/soc/clock.h |  4 ++++
 2 files changed, 32 insertions(+)

diff --git a/bdk/soc/clock.c b/bdk/soc/clock.c
index d01ffd2..b122cf9 100644
--- a/bdk/soc/clock.c
+++ b/bdk/soc/clock.c
@@ -100,6 +100,14 @@ static clock_t _clock_sdmmc_legacy_tm = {
 	CLK_RST_CONTROLLER_RST_DEVICES_Y, CLK_RST_CONTROLLER_CLK_OUT_ENB_Y, CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM, CLK_Y_SDMMC_LEGACY_TM, 4, 66
 };
 
+static clock_t _clock_apbdma = {
+	CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_NO_SOURCE,                         CLK_H_APBDMA,  0, 0
+};
+
+static clock_t _clock_ahbdma = {
+	CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_NO_SOURCE,                         CLK_H_AHBDMA,  0, 0
+};
+
 static clock_t _clock_actmon = {
 	CLK_RST_CONTROLLER_RST_DEVICES_V, CLK_RST_CONTROLLER_CLK_OUT_ENB_V, CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON,  CLK_V_ACTMON,  6, 0 // 19.2MHz.
 };
@@ -283,6 +291,26 @@ void clock_disable_pwm()
 	clock_disable(&_clock_pwm);
 }
 
+void clock_enable_apbdma()
+{
+	clock_enable(&_clock_apbdma);
+}
+
+void clock_disable_apbdma()
+{
+	clock_disable(&_clock_apbdma);
+}
+
+void clock_enable_ahbdma()
+{
+	clock_enable(&_clock_ahbdma);
+}
+
+void clock_disable_ahbdma()
+{
+	clock_disable(&_clock_ahbdma);
+}
+
 void clock_enable_actmon()
 {
 	clock_enable(&_clock_actmon);
diff --git a/bdk/soc/clock.h b/bdk/soc/clock.h
index 23ee53f..6b504f8 100644
--- a/bdk/soc/clock.h
+++ b/bdk/soc/clock.h
@@ -660,6 +660,10 @@ void clock_enable_coresight();
 void clock_disable_coresight();
 void clock_enable_pwm();
 void clock_disable_pwm();
+void clock_enable_apbdma();
+void clock_disable_apbdma();
+void clock_enable_ahbdma();
+void clock_disable_ahbdma();
 void clock_enable_actmon();
 void clock_disable_actmon();