diff --git a/bdk/soc/clock.c b/bdk/soc/clock.c
index 227f595..2130407 100644
--- a/bdk/soc/clock.c
+++ b/bdk/soc/clock.c
@@ -388,6 +388,22 @@ void clock_disable_pllu()
 	CLOCK(CLK_RST_CONTROLLER_PLLU_MISC) &= ~0x20000000; // Enable reference clock.
 }
 
+void clock_enable_utmipll()
+{
+	// Set UTMIPLL dividers and config based on OSC and enable it to 960 MHz.
+	CLOCK(CLK_RST_CONTROLLER_UTMIP_PLL_CFG0) = (CLOCK(CLK_RST_CONTROLLER_UTMIP_PLL_CFG0) & 0xFF0000FF) | (25 << 16) | (1 << 8); // 38.4Mhz * (25 / 1) = 960 MHz.
+	CLOCK(CLK_RST_CONTROLLER_UTMIP_PLL_CFG2) = (CLOCK(CLK_RST_CONTROLLER_UTMIP_PLL_CFG2) & 0xFF00003F) | (24 << 18); // Set delay count for 38.4Mhz osc crystal.
+	CLOCK(CLK_RST_CONTROLLER_UTMIP_PLL_CFG1) = (CLOCK(CLK_RST_CONTROLLER_UTMIP_PLL_CFG1) &  0x7FFA000) | (1 << 15) | 375;
+
+	// Wait for UTMIPLL to stabilize.
+	u32 retries = 10; // Wait 20us
+	while (!(CLOCK(CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0) & UTMIPLL_LOCK) && retries)
+	{
+		usleep(1);
+		retries--;
+	}
+}
+
 static int _clock_sdmmc_is_reset(u32 id)
 {
 	switch (id)
diff --git a/bdk/soc/clock.h b/bdk/soc/clock.h
index fbce54e..f44860f 100644
--- a/bdk/soc/clock.h
+++ b/bdk/soc/clock.h
@@ -171,6 +171,8 @@
 #define PLLC4_OUT3_CLKEN     (1 << 1)
 #define PLLC4_OUT3_RSTN_CLR  (1 << 0)
 
+#define UTMIPLL_LOCK         (1 << 31)
+
 /*
  * CLOCK Peripherals:
  * L   0 -  31
@@ -480,6 +482,7 @@ void clock_enable_pllc(u32 divn);
 void clock_disable_pllc();
 void clock_enable_pllu();
 void clock_disable_pllu();
+void clock_enable_utmipll();
 void clock_sdmmc_config_clock_source(u32 *pclock, u32 id, u32 val);
 void clock_sdmmc_get_card_clock_div(u32 *pclock, u16 *pdivisor, u32 type);
 int  clock_sdmmc_is_not_reset_and_enabled(u32 id);
diff --git a/bdk/usb/usbd.c b/bdk/usb/usbd.c
index 5dbfe4e..0fd66ce 100644
--- a/bdk/usb/usbd.c
+++ b/bdk/usb/usbd.c
@@ -278,18 +278,8 @@ int usb_device_init()
 	USB(USB1_IF_USB_PHY_VBUS_SENSORS) |= 0x1000;
 	USB(USB1_IF_USB_PHY_VBUS_SENSORS) |= 0x800;
 
-	// Set UTMIPLL dividers and enable it.
-	CLOCK(CLK_RST_CONTROLLER_UTMIP_PLL_CFG0) = (CLOCK(CLK_RST_CONTROLLER_UTMIP_PLL_CFG0) & 0xFF0000FF) | 0x190000 | 0x100;
-	CLOCK(CLK_RST_CONTROLLER_UTMIP_PLL_CFG2) = (CLOCK(CLK_RST_CONTROLLER_UTMIP_PLL_CFG2) & 0xFF00003F) | 0x600000; // Set delay count for 38.4Mhz osc crystal.
-	CLOCK(CLK_RST_CONTROLLER_UTMIP_PLL_CFG1) = ((CLOCK(CLK_RST_CONTROLLER_UTMIP_PLL_CFG1) & 0x7FFF000) | 0x8000 | 0x177) & 0xFFFFAFFF;
-
-	// Wait for UTMIPLL to stabilize.
-	u32 retries = 10; // Wait 20us
-	while (!(CLOCK(CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0) & 0x80000000) && retries)
-	{
-		usleep(1);
-		retries--;
-	}
+	// Set UTMIPLL dividers and config based on OSC and enable it to 960 MHz.
+	clock_enable_utmipll();
 
 	// Configure UTMIP Transceiver Cells.
 	u32 fuse_usb_calib = FUSE(FUSE_USB_CALIB);