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Small refactor and bugfixes

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This commit is contained in:
CTCaer 2019-12-04 21:31:39 +02:00
parent 168de9ddd8
commit 0b1eebefe1
38 changed files with 1315 additions and 1273 deletions
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30
bootloader/main.c
View file

@ -393,7 +393,7 @@ void launch_tools()
i++; i++;
} }
} }
if (i > 0) if (i > 0)
{ {
memset(&ments[i + 2], 0, sizeof(ment_t)); memset(&ments[i + 2], 0, sizeof(ment_t));
@ -407,6 +407,7 @@ void launch_tools()
free(dir); free(dir);
free(filelist); free(filelist);
sd_unmount(); sd_unmount();
return; return;
} }
} }
@ -427,11 +428,8 @@ void launch_tools()
memcpy(dir + strlen(dir), "/", 2); memcpy(dir + strlen(dir), "/", 2);
memcpy(dir + strlen(dir), file_sec, strlen(file_sec) + 1); memcpy(dir + strlen(dir), file_sec, strlen(file_sec) + 1);
if (launch_payload(dir, false)) launch_payload(dir, false);
{ EPRINTF("Failed to launch payload.");
EPRINTF("Failed to launch payload.");
free(dir);
}
} }
out: out:
@ -531,11 +529,9 @@ void ini_list_launcher()
if (payload_path) if (payload_path)
{ {
if (launch_payload(payload_path, false)) launch_payload(payload_path, false);
{ EPRINTF("Failed to launch payload.");
EPRINTF("Failed to launch payload."); free(payload_path);
free(payload_path);
}
} }
else if (!hos_launch(cfg_sec)) else if (!hos_launch(cfg_sec))
{ {
@ -665,11 +661,9 @@ void launch_firmware()
if (payload_path) if (payload_path)
{ {
if (launch_payload(payload_path, false)) launch_payload(payload_path, false);
{ EPRINTF("Failed to launch payload.");
EPRINTF("Failed to launch payload."); free(payload_path);
free(payload_path);
}
} }
else if (!hos_launch(cfg_sec)) else if (!hos_launch(cfg_sec))
EPRINTF("Failed to launch firmware."); EPRINTF("Failed to launch firmware.");
@ -1014,8 +1008,8 @@ skip_list:
if (payload_path) if (payload_path)
{ {
if (launch_payload(payload_path, false)) launch_payload(payload_path, false);
free(payload_path); free(payload_path);
} }
else else
{ {

1186
bootloader/mem/emc.h
View file

File diff suppressed because it is too large Load diff

2
bootloader/mem/heap.c
View file

@ -18,7 +18,7 @@
#include <string.h> #include <string.h>
#include "heap.h" #include "heap.h"
#include "../gfx/gfx.h" #include "../gfx/gfx.h"
#include "../../../common/common_heap.h" #include "../../common/common_heap.h"
static void _heap_create(heap_t *heap, u32 start) static void _heap_create(heap_t *heap, u32 start)
{ {

2
bootloader/mem/heap.h
View file

@ -18,7 +18,7 @@
#define _HEAP_H_ #define _HEAP_H_
#include "../utils/types.h" #include "../utils/types.h"
#include "../../../common/common_heap.h" #include "../../common/common_heap.h"
void heap_init(u32 base); void heap_init(u32 base);
void *malloc(u32 size); void *malloc(u32 size);

1
bootloader/mem/sdram.c
View file

@ -71,6 +71,7 @@ static void _sdram_config(const sdram_params_t *params)
// Start clocks. // Start clocks.
CLOCK(CLK_RST_CONTROLLER_PLLM_MISC1) = params->pllm_setup_control; CLOCK(CLK_RST_CONTROLLER_PLLM_MISC1) = params->pllm_setup_control;
CLOCK(CLK_RST_CONTROLLER_PLLM_MISC2) = 0; CLOCK(CLK_RST_CONTROLLER_PLLM_MISC2) = 0;
// u32 tmp = (params->pllm_feedback_divider << 8) | params->pllm_input_divider | ((params->pllm_post_divider & 0xFFFF) << 20); // u32 tmp = (params->pllm_feedback_divider << 8) | params->pllm_input_divider | ((params->pllm_post_divider & 0xFFFF) << 20);
// CLOCK(CLK_RST_CONTROLLER_PLLM_BASE) = tmp; // CLOCK(CLK_RST_CONTROLLER_PLLM_BASE) = tmp;
// CLOCK(CLK_RST_CONTROLLER_PLLM_BASE) = tmp | 0x40000000; // CLOCK(CLK_RST_CONTROLLER_PLLM_BASE) = tmp | 0x40000000;

2
bootloader/sec/tsec.c
View file

@ -212,7 +212,7 @@ int tsec_query(u8 *tsec_keys, u8 kb, tsec_ctxt_t *tsec_ctxt)
res = -6; res = -6;
smmu_deinit_for_tsec(); smmu_deinit_for_tsec();
goto out; goto out_free;
} }
// Give some extra time to make sure PKG1.1 is decrypted. // Give some extra time to make sure PKG1.1 is decrypted.

13
bootloader/soc/clock.c
View file

@ -29,6 +29,7 @@ static const clock_t _clock_uart[] = {
/* UART E */ { CLK_RST_CONTROLLER_RST_DEVICES_Y, CLK_RST_CONTROLLER_CLK_OUT_ENB_Y, CLK_RST_CONTROLLER_CLK_SOURCE_UARTAPE, 20, 0, 2 } /* UART E */ { CLK_RST_CONTROLLER_RST_DEVICES_Y, CLK_RST_CONTROLLER_CLK_OUT_ENB_Y, CLK_RST_CONTROLLER_CLK_SOURCE_UARTAPE, 20, 0, 2 }
}; };
//I2C default parameters - TLOW: 4, THIGH: 2, DEBOUNCE: 0 FM_DIV: 26.
static const clock_t _clock_i2c[] = { static const clock_t _clock_i2c[] = {
/* I2C1 */ { CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_I2C1, 12, 6, 0 }, // 0, 19 }, // 100KHz /* I2C1 */ { CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_I2C1, 12, 6, 0 }, // 0, 19 }, // 100KHz
/* I2C2 */ { 0 }, /* I2C2 */ { 0 },
@ -73,7 +74,7 @@ static clock_t _clock_coresight = {
}; };
static clock_t _clock_pwm = { static clock_t _clock_pwm = {
CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_PWM, 17, 6, 4 // Freference: 6.2MHz. CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_PWM, 17, 6, 4 // Fref: 6.2MHz.
}; };
void clock_enable(const clock_t *clk) void clock_enable(const clock_t *clk)
@ -366,7 +367,7 @@ static void _clock_sdmmc_clear_enable(u32 id)
static u32 _clock_sdmmc_table[8] = { 0 }; static u32 _clock_sdmmc_table[8] = { 0 };
#define PLLP_OUT0 0x0 #define PLLP_OUT0 0x0
static int _clock_sdmmc_config_clock_source_inner(u32 *pout, u32 id, u32 val) static int _clock_sdmmc_config_clock_host(u32 *pout, u32 id, u32 val)
{ {
u32 divisor = 0; u32 divisor = 0;
u32 source = PLLP_OUT0; u32 source = PLLP_OUT0;
@ -414,6 +415,7 @@ static int _clock_sdmmc_config_clock_source_inner(u32 *pout, u32 id, u32 val)
_clock_sdmmc_table[2 * id] = val; _clock_sdmmc_table[2 * id] = val;
_clock_sdmmc_table[2 * id + 1] = *pout; _clock_sdmmc_table[2 * id + 1] = *pout;
// Set SDMMC clock.
switch (id) switch (id)
{ {
case SDMMC_1: case SDMMC_1:
@ -444,15 +446,16 @@ void clock_sdmmc_config_clock_source(u32 *pout, u32 id, u32 val)
int is_enabled = _clock_sdmmc_is_enabled(id); int is_enabled = _clock_sdmmc_is_enabled(id);
if (is_enabled) if (is_enabled)
_clock_sdmmc_clear_enable(id); _clock_sdmmc_clear_enable(id);
_clock_sdmmc_config_clock_source_inner(pout, id, val); _clock_sdmmc_config_clock_host(pout, id, val);
if (is_enabled) if (is_enabled)
_clock_sdmmc_set_enable(id); _clock_sdmmc_set_enable(id);
_clock_sdmmc_is_reset(id); _clock_sdmmc_is_reset(id);
} }
} }
void clock_sdmmc_get_params(u32 *pout, u16 *pdivisor, u32 type) void clock_sdmmc_get_card_clock_div(u32 *pout, u16 *pdivisor, u32 type)
{ {
// Get Card clock divisor.
switch (type) switch (type)
{ {
case 0: case 0:
@ -513,7 +516,7 @@ void clock_sdmmc_enable(u32 id, u32 val)
if (_clock_sdmmc_is_enabled(id)) if (_clock_sdmmc_is_enabled(id))
_clock_sdmmc_clear_enable(id); _clock_sdmmc_clear_enable(id);
_clock_sdmmc_set_reset(id); _clock_sdmmc_set_reset(id);
_clock_sdmmc_config_clock_source_inner(&div, id, val); _clock_sdmmc_config_clock_host(&div, id, val);
_clock_sdmmc_set_enable(id); _clock_sdmmc_set_enable(id);
_clock_sdmmc_is_reset(id); _clock_sdmmc_is_reset(id);
usleep((100000 + div - 1) / div); usleep((100000 + div - 1) / div);

3
bootloader/soc/clock.h
View file

@ -104,6 +104,7 @@
#define CLK_RST_CONTROLLER_CLK_SOURCE_SYS 0x400 #define CLK_RST_CONTROLLER_CLK_SOURCE_SYS 0x400
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1 0x410 #define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1 0x410
#define CLK_RST_CONTROLLER_CLK_SOURCE_SE 0x42C #define CLK_RST_CONTROLLER_CLK_SOURCE_SE 0x42C
#define CLK_RST_CONTROLLER_RST_DEV_V_CLR 0x434
#define CLK_RST_CONTROLLER_CLK_ENB_V_SET 0x440 #define CLK_RST_CONTROLLER_CLK_ENB_V_SET 0x440
#define CLK_RST_CONTROLLER_CLK_ENB_V_CLR 0x444 #define CLK_RST_CONTROLLER_CLK_ENB_V_CLR 0x444
#define CLK_RST_CONTROLLER_CLK_ENB_W_SET 0x448 #define CLK_RST_CONTROLLER_CLK_ENB_W_SET 0x448
@ -181,7 +182,7 @@ void clock_disable_coresight();
void clock_enable_pwm(); void clock_enable_pwm();
void clock_disable_pwm(); void clock_disable_pwm();
void clock_sdmmc_config_clock_source(u32 *pout, u32 id, u32 val); void clock_sdmmc_config_clock_source(u32 *pout, u32 id, u32 val);
void clock_sdmmc_get_params(u32 *pout, u16 *pdivisor, u32 type); void clock_sdmmc_get_card_clock_div(u32 *pout, u16 *pdivisor, u32 type);
int clock_sdmmc_is_not_reset_and_enabled(u32 id); int clock_sdmmc_is_not_reset_and_enabled(u32 id);
void clock_sdmmc_enable(u32 id, u32 val); void clock_sdmmc_enable(u32 id, u32 val);
void clock_sdmmc_disable(u32 id); void clock_sdmmc_disable(u32 id);

7
bootloader/soc/cluster.c
View file

@ -80,9 +80,9 @@ void cluster_boot_cpu0(u32 entry)
_cluster_enable_power(); _cluster_enable_power();
if (!(CLOCK(CLK_RST_CONTROLLER_PLLX_BASE) & 0x40000000)) if (!(CLOCK(CLK_RST_CONTROLLER_PLLX_BASE) & 0x40000000)) // PLLX_ENABLE.
{ {
CLOCK(CLK_RST_CONTROLLER_PLLX_MISC_3) &= 0xFFFFFFF7; CLOCK(CLK_RST_CONTROLLER_PLLX_MISC_3) &= 0xFFFFFFF7; // Disable IDDQ.
usleep(2); usleep(2);
CLOCK(CLK_RST_CONTROLLER_PLLX_BASE) = 0x80404E02; CLOCK(CLK_RST_CONTROLLER_PLLX_BASE) = 0x80404E02;
CLOCK(CLK_RST_CONTROLLER_PLLX_BASE) = 0x404E02; CLOCK(CLK_RST_CONTROLLER_PLLX_BASE) = 0x404E02;
@ -127,6 +127,9 @@ void cluster_boot_cpu0(u32 entry)
SB(SB_CSR) = SB_CSR_NS_RST_VEC_WR_DIS; SB(SB_CSR) = SB_CSR_NS_RST_VEC_WR_DIS;
(void)SB(SB_CSR); (void)SB(SB_CSR);
// Tighten up the security aperture.
// MC(MC_TZ_SECURITY_CTRL) = 1;
// Clear MSELECT reset. // Clear MSELECT reset.
CLOCK(CLK_RST_CONTROLLER_RST_DEVICES_V) &= 0xFFFFFFF7; CLOCK(CLK_RST_CONTROLLER_RST_DEVICES_V) &= 0xFFFFFFF7;
// Clear NONCPU reset. // Clear NONCPU reset.

1
bootloader/soc/fuse.h
View file

@ -54,6 +54,7 @@
#define FUSE_PRIVATE_KEY3 0x1B0 #define FUSE_PRIVATE_KEY3 0x1B0
#define FUSE_PRIVATE_KEY4 0x1B4 #define FUSE_PRIVATE_KEY4 0x1B4
#define FUSE_RESERVED_SW 0x1C0 #define FUSE_RESERVED_SW 0x1C0
#define FUSE_SKU_DIRECT_CONFIG 0x1F4
#define FUSE_OPT_VENDOR_CODE 0x200 #define FUSE_OPT_VENDOR_CODE 0x200
#define FUSE_OPT_FAB_CODE 0x204 #define FUSE_OPT_FAB_CODE 0x204
#define FUSE_OPT_LOT_CODE_0 0x208 #define FUSE_OPT_LOT_CODE_0 0x208

1
bootloader/soc/hw_init.c
View file

@ -275,6 +275,7 @@ void config_hw()
// Enable fuse clock. // Enable fuse clock.
clock_enable_fuse(true); clock_enable_fuse(true);
// Disable fuse programming. // Disable fuse programming.
fuse_disable_program(); fuse_disable_program();

2
bootloader/soc/smmu.c
View file

@ -106,7 +106,7 @@ bool smmu_is_used()
void smmu_exit() void smmu_exit()
{ {
*(uint32_t *)(smmu_payload + 0x14) = _NOP(); *(u32 *)(smmu_payload + 0x14) = _NOP();
} }
u32 *smmu_init_domain4(u32 dev_base, u32 asid) u32 *smmu_init_domain4(u32 dev_base, u32 asid)

10
bootloader/soc/t210.h
View file

@ -108,6 +108,14 @@
/*! EVP registers. */ /*! EVP registers. */
#define EVP_CPU_RESET_VECTOR 0x100 #define EVP_CPU_RESET_VECTOR 0x100
#define EVP_COP_RESET_VECTOR 0x200
#define EVP_COP_UNDEF_VECTOR 0x204
#define EVP_COP_SWI_VECTOR 0x208
#define EVP_COP_PREFETCH_ABORT_VECTOR 0x20C
#define EVP_COP_DATA_ABORT_VECTOR 0x210
#define EVP_COP_RSVD_VECTOR 0x214
#define EVP_COP_IRQ_VECTOR 0x218
#define EVP_COP_FIQ_VECTOR 0x21C
/*! Misc registers. */ /*! Misc registers. */
#define APB_MISC_PP_STRAPPING_OPT_A 0x08 #define APB_MISC_PP_STRAPPING_OPT_A 0x08
@ -208,7 +216,7 @@
#define HALT_COP_JTAG (1 << 28) #define HALT_COP_JTAG (1 << 28)
#define HALT_COP_WAIT_EVENT (1 << 30) #define HALT_COP_WAIT_EVENT (1 << 30)
#define HALT_COP_WAIT_IRQ (1 << 31) #define HALT_COP_WAIT_IRQ (1 << 31)
#define HALT_COP_MAX_CNT 0xFF #define HALT_COP_MAX_CNT 0xFF
#define FLOW_CTLR_HALT_CPU0_EVENTS 0x0 #define FLOW_CTLR_HALT_CPU0_EVENTS 0x0
#define FLOW_CTLR_HALT_CPU1_EVENTS 0x14 #define FLOW_CTLR_HALT_CPU1_EVENTS 0x14
#define FLOW_CTLR_HALT_CPU2_EVENTS 0x1C #define FLOW_CTLR_HALT_CPU2_EVENTS 0x1C

2
bootloader/storage/nx_emmc.c
View file

@ -36,7 +36,7 @@ void nx_emmc_gpt_parse(link_t *gpt, sdmmc_storage_t *storage)
part->lba_end = ent->lba_end; part->lba_end = ent->lba_end;
part->attrs = ent->attrs; part->attrs = ent->attrs;
//HACK // ASCII conversion. Copy only the LSByte of the UTF-16LE name.
for (u32 i = 0; i < 36; i++) for (u32 i = 0; i < 36; i++)
part->name[i] = ent->name[i]; part->name[i] = ent->name[i];
part->name[36] = 0; part->name[36] = 0;

2
bootloader/storage/sd.h
View file

@ -40,7 +40,9 @@
#define SD_ROCR_S18A SD_OCR_S18R /* 1.8V switching accepted by card */ #define SD_ROCR_S18A SD_OCR_S18R /* 1.8V switching accepted by card */
#define SD_OCR_XPC (1 << 28) /* SDXC power control */ #define SD_OCR_XPC (1 << 28) /* SDXC power control */
#define SD_OCR_CCS (1 << 30) /* Card Capacity Status */ #define SD_OCR_CCS (1 << 30) /* Card Capacity Status */
#define SD_OCR_VDD_27_34 (0x7F << 15) /* VDD voltage 2.7 ~ 3.4 */
#define SD_OCR_VDD_32_33 (1 << 20) /* VDD voltage 3.2 ~ 3.3 */ #define SD_OCR_VDD_32_33 (1 << 20) /* VDD voltage 3.2 ~ 3.3 */
#define SD_OCR_VDD_18 (1 << 7) /* VDD voltage 1.8 */
/* /*
* SD_SWITCH argument format: * SD_SWITCH argument format:

32
bootloader/storage/sdmmc.c
View file

@ -220,10 +220,10 @@ static int _mmc_storage_get_op_cond_inner(sdmmc_storage_t *storage, u32 *pout, u
switch (power) switch (power)
{ {
case SDMMC_POWER_1_8: case SDMMC_POWER_1_8:
arg = 0x40000080; //Sector access, voltage. arg = SD_OCR_CCS | SD_OCR_VDD_18;
break; break;
case SDMMC_POWER_3_3: case SDMMC_POWER_3_3:
arg = 0x403F8000; //Sector access, voltage. arg = SD_OCR_CCS | SD_OCR_VDD_27_34;
break; break;
default: default:
return 0; return 0;
@ -248,7 +248,7 @@ static int _mmc_storage_get_op_cond(sdmmc_storage_t *storage, u32 power)
if (cond & MMC_CARD_BUSY) if (cond & MMC_CARD_BUSY)
{ {
if (cond & 0x40000000) if (cond & SD_OCR_CCS)
storage->has_sector_access = 1; storage->has_sector_access = 1;
return 1; return 1;
@ -569,7 +569,7 @@ DPRINTF("[MMC] BKOPS disabled\n");
if (!_mmc_storage_enable_highspeed(storage, storage->ext_csd.card_type, type)) if (!_mmc_storage_enable_highspeed(storage, storage->ext_csd.card_type, type))
return 0; return 0;
DPRINTF("[MMC] succesfully switched to highspeed mode\n"); DPRINTF("[MMC] succesfully switched to HS mode\n");
sdmmc_sd_clock_ctrl(storage->sdmmc, 1); sdmmc_sd_clock_ctrl(storage->sdmmc, 1);
@ -819,17 +819,17 @@ void _sd_storage_set_current_limit(sdmmc_storage_t *storage, u8 *buf)
switch (pwr) switch (pwr)
{ {
case SD_SET_CURRENT_LIMIT_800: case SD_SET_CURRENT_LIMIT_800:
DPRINTF("[SD] Power limit raised to 800mA\n"); DPRINTF("[SD] power limit raised to 800mA\n");
break; break;
case SD_SET_CURRENT_LIMIT_600: case SD_SET_CURRENT_LIMIT_600:
DPRINTF("[SD] Power limit raised to 600mA\n"); DPRINTF("[SD] power limit raised to 600mA\n");
break; break;
case SD_SET_CURRENT_LIMIT_400: case SD_SET_CURRENT_LIMIT_400:
DPRINTF("[SD] Power limit raised to 800mA\n"); DPRINTF("[SD] power limit raised to 800mA\n");
break; break;
default: default:
case SD_SET_CURRENT_LIMIT_200: case SD_SET_CURRENT_LIMIT_200:
DPRINTF("[SD] Power limit defaulted to 200mA\n"); DPRINTF("[SD] power limit defaulted to 200mA\n");
break; break;
} }
} }
@ -857,7 +857,7 @@ DPRINTF("[SD] SD supports selected (U)HS mode\n");
return 1; return 1;
} }
int _sd_storage_enable_highspeed_low_volt(sdmmc_storage_t *storage, u32 type, u8 *buf) int _sd_storage_enable_uhs_low_volt(sdmmc_storage_t *storage, u32 type, u8 *buf)
{ {
// Try to raise the current limit to let the card perform better. // Try to raise the current limit to let the card perform better.
_sd_storage_set_current_limit(storage, buf); _sd_storage_set_current_limit(storage, buf);
@ -878,7 +878,7 @@ int _sd_storage_enable_highspeed_low_volt(sdmmc_storage_t *storage, u32 type, u8
{ {
type = 11; type = 11;
hs_type = UHS_SDR104_BUS_SPEED; hs_type = UHS_SDR104_BUS_SPEED;
DPRINTF("[SD] Bus speed set to SDR104\n"); DPRINTF("[SD] bus speed set to SDR104\n");
storage->csd.busspeed = 104; storage->csd.busspeed = 104;
break; break;
} }
@ -887,7 +887,7 @@ DPRINTF("[SD] Bus speed set to SDR104\n");
{ {
type = 10; type = 10;
hs_type = UHS_SDR50_BUS_SPEED; hs_type = UHS_SDR50_BUS_SPEED;
DPRINTF("[SD] Bus speed set to SDR50\n"); DPRINTF("[SD] bus speed set to SDR50\n");
storage->csd.busspeed = 50; storage->csd.busspeed = 50;
break; break;
} }
@ -896,7 +896,7 @@ DPRINTF("[SD] Bus speed set to SDR50\n");
return 0; return 0;
type = 8; type = 8;
hs_type = UHS_SDR12_BUS_SPEED; hs_type = UHS_SDR12_BUS_SPEED;
DPRINTF("[SD] Bus speed set to SDR12\n"); DPRINTF("[SD] bus speed set to SDR12\n");
storage->csd.busspeed = 12; storage->csd.busspeed = 12;
break; break;
default: default:
@ -916,7 +916,7 @@ DPRINTF("[SD] config tuning\n");
return _sdmmc_storage_check_status(storage); return _sdmmc_storage_check_status(storage);
} }
int _sd_storage_enable_highspeed_high_volt(sdmmc_storage_t *storage, u8 *buf) int _sd_storage_enable_hs_high_volt(sdmmc_storage_t *storage, u8 *buf)
{ {
if (!_sd_storage_switch_get(storage, buf)) if (!_sd_storage_switch_get(storage, buf))
return 0; return 0;
@ -1065,7 +1065,7 @@ int sdmmc_storage_init_sd(sdmmc_storage_t *storage, sdmmc_t *sdmmc, u32 id, u32
{ {
int is_version_1 = 0; int is_version_1 = 0;
// Some cards (Sandisk U1), do not like a fast power cycle. Wait min 100ms. // Some cards (SanDisk U1), do not like a fast power cycle. Wait min 100ms.
sdmmc_storage_init_wait_sd(); sdmmc_storage_init_wait_sd();
memset(storage, 0, sizeof(sdmmc_storage_t)); memset(storage, 0, sizeof(sdmmc_storage_t));
@ -1166,7 +1166,7 @@ DPRINTF("[SD] SD does not support wide bus width\n");
if (storage->is_low_voltage) if (storage->is_low_voltage)
{ {
if (!_sd_storage_enable_highspeed_low_volt(storage, type, buf)) if (!_sd_storage_enable_uhs_low_volt(storage, type, buf))
{ {
free(buf); free(buf);
return 0; return 0;
@ -1175,7 +1175,7 @@ DPRINTF("[SD] enabled UHS\n");
} }
else if (type != 6 && (storage->scr.sda_vsn & 0xF) != 0) else if (type != 6 && (storage->scr.sda_vsn & 0xF) != 0)
{ {
if (!_sd_storage_enable_highspeed_high_volt(storage, buf)) if (!_sd_storage_enable_hs_high_volt(storage, buf))
{ {
free(buf); free(buf);
return 0; return 0;

4
bootloader/storage/sdmmc_driver.c
View file

@ -252,7 +252,7 @@ int sdmmc_setup_clock(sdmmc_t *sdmmc, u32 type)
u32 tmp; u32 tmp;
u16 divisor; u16 divisor;
clock_sdmmc_get_params(&tmp, &divisor, type); clock_sdmmc_get_card_clock_div(&tmp, &divisor, type);
clock_sdmmc_config_clock_source(&tmp, sdmmc->id, tmp); clock_sdmmc_config_clock_source(&tmp, sdmmc->id, tmp);
sdmmc->divisor = (tmp + divisor - 1) / divisor; sdmmc->divisor = (tmp + divisor - 1) / divisor;
@ -1015,7 +1015,7 @@ int sdmmc_init(sdmmc_t *sdmmc, u32 id, u32 power, u32 bus_width, u32 type, int n
u32 clock; u32 clock;
u16 divisor; u16 divisor;
clock_sdmmc_get_params(&clock, &divisor, type); clock_sdmmc_get_card_clock_div(&clock, &divisor, type);
clock_sdmmc_enable(id, clock); clock_sdmmc_enable(id, clock);
sdmmc->clock_stopped = 0; sdmmc->clock_stopped = 0;

1
bootloader/utils/types.h
View file

@ -20,6 +20,7 @@
#define NULL ((void *)0) #define NULL ((void *)0)
#define ALIGN(x, a) (((x) + (a) - 1) & ~((a) - 1)) #define ALIGN(x, a) (((x) + (a) - 1) & ~((a) - 1))
#define ALIGN_DOWN(x, a) (((x) - ((a) - 1)) & ~((a) - 1))
#define MAX(a, b) ((a) > (b) ? (a) : (b)) #define MAX(a, b) ((a) > (b) ? (a) : (b))
#define MIN(a, b) ((a) < (b) ? (a) : (b)) #define MIN(a, b) ((a) < (b) ? (a) : (b))

2
bootloader/utils/util.c
View file

@ -126,7 +126,7 @@ void power_off()
max77620_rtc_stop_alarm(); max77620_rtc_stop_alarm();
i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_ONOFFCNFG1, MAX77620_ONOFFCNFG1_PWR_OFF); i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_ONOFFCNFG1, MAX77620_ONOFFCNFG1_PWR_OFF);
while (true) while (true)
bpmp_halt(); bpmp_halt();
} }

4
nyx/nyx_gui/frontend/gui.c
View file

@ -177,7 +177,7 @@ static void _disp_fb_flush(int32_t x1, int32_t y1, int32_t x2, int32_t y2, const
static touch_event touchpad; static touch_event touchpad;
static bool _fts_touch_read(lv_indev_data_t *data) static bool _fts_touch_read(lv_indev_data_t *data)
{ {
touch_poll(&touchpad); touch_poll(&touchpad);
@ -1572,7 +1572,7 @@ static void _nyx_main_menu(lv_theme_t * th)
static lv_style_t line_style; static lv_style_t line_style;
lv_style_copy(&line_style, &lv_style_plain_color); lv_style_copy(&line_style, &lv_style_plain_color);
line_style.body.main_color = LV_COLOR_HEX3(0xDDD); // 0x505050 line_style.body.main_color = LV_COLOR_HEX(0xDDDDDD); // 0x505050
line_style.body.grad_color = line_style.body.main_color; line_style.body.grad_color = line_style.body.main_color;
line_style.body.shadow.width = 0; line_style.body.shadow.width = 0;

2
nyx/nyx_gui/frontend/gui_info.c
View file

@ -1067,7 +1067,7 @@ void create_tab_info(lv_theme_t *th, lv_obj_t *parent)
static lv_style_t line_style; static lv_style_t line_style;
lv_style_copy(&line_style, th->line.decor); lv_style_copy(&line_style, th->line.decor);
line_style.line.color = LV_COLOR_HEX3(0x444); line_style.line.color = LV_COLOR_HEX(0x444444);
line_sep = lv_line_create(h1, line_sep); line_sep = lv_line_create(h1, line_sep);
lv_obj_align(line_sep, label_txt2, LV_ALIGN_OUT_BOTTOM_LEFT, -(LV_DPI / 4), LV_DPI / 16); lv_obj_align(line_sep, label_txt2, LV_ALIGN_OUT_BOTTOM_LEFT, -(LV_DPI / 4), LV_DPI / 16);

2
nyx/nyx_gui/frontend/gui_tools.c
View file

@ -824,7 +824,7 @@ static void _create_tab_tools_arc_autorcm(lv_theme_t *th, lv_obj_t *parent)
label_btn = lv_label_create(btn3, NULL); label_btn = lv_label_create(btn3, NULL);
lv_btn_set_fit(btn3, true, true); lv_btn_set_fit(btn3, true, true);
lv_label_set_recolor(label_btn, true); lv_label_set_recolor(label_btn, true);
lv_label_set_static_text(label_btn, SYMBOL_REFRESH" AutoRCM #00ffc9 ON #"); lv_label_set_static_text(label_btn, SYMBOL_REFRESH" AutoRCM #00FFC9 ON #");
lv_obj_align(btn3, line_sep, LV_ALIGN_OUT_BOTTOM_LEFT, LV_DPI / 4, LV_DPI / 4); lv_obj_align(btn3, line_sep, LV_ALIGN_OUT_BOTTOM_LEFT, LV_DPI / 4, LV_DPI / 4);
lv_btn_set_action(btn3, LV_BTN_ACTION_CLICK, _create_mbox_autorcm_status); lv_btn_set_action(btn3, LV_BTN_ACTION_CLICK, _create_mbox_autorcm_status);

3
nyx/nyx_gui/libs/lv_conf.h
View file

@ -144,7 +144,6 @@
#define LV_ATTRIBUTE_TICK_INC /* Define a custom attribute to `lv_tick_inc` function */ #define LV_ATTRIBUTE_TICK_INC /* Define a custom attribute to `lv_tick_inc` function */
#define LV_ATTRIBUTE_TASK_HANDLER /* Define a custom attribute to `lv_task_handler` function */ #define LV_ATTRIBUTE_TASK_HANDLER /* Define a custom attribute to `lv_task_handler` function */
#define LV_COMPILER_VLA_SUPPORTED 1 /* 1: Variable length array is supported*/ #define LV_COMPILER_VLA_SUPPORTED 1 /* 1: Variable length array is supported*/
#define LV_COMPILER_NON_CONST_INIT_SUPPORTED 1 /* 1: Initialization with non constant values are supported */
/*HAL settings*/ /*HAL settings*/
#define LV_TICK_CUSTOM 1 /*1: use a custom tick source (removing the need to manually update the tick with `lv_tick_inc`) */ #define LV_TICK_CUSTOM 1 /*1: use a custom tick source (removing the need to manually update the tick with `lv_tick_inc`) */
@ -231,7 +230,7 @@
#define USE_LV_IMG 1 #define USE_LV_IMG 1
#if USE_LV_IMG != 0 #if USE_LV_IMG != 0
# define LV_IMG_CF_INDEXED 0 /*Enable indexed (palette) images*/ # define LV_IMG_CF_INDEXED 0 /*Enable indexed (palette) images*/
# define LV_IMG_CF_ALPHA 1 /*Enable alpha indexed images*/ # define LV_IMG_CF_ALPHA 0 /*Enable alpha indexed images*/
#endif #endif
/*Line (dependencies: -*/ /*Line (dependencies: -*/

1186
nyx/nyx_gui/mem/emc.h
View file

File diff suppressed because it is too large Load diff

4
nyx/nyx_gui/mem/sdram.c
View file

@ -65,6 +65,10 @@ static void _sdram_config(const sdram_params_t *params)
// Start clocks. // Start clocks.
CLOCK(CLK_RST_CONTROLLER_PLLM_MISC1) = params->pllm_setup_control; CLOCK(CLK_RST_CONTROLLER_PLLM_MISC1) = params->pllm_setup_control;
CLOCK(CLK_RST_CONTROLLER_PLLM_MISC2) = 0; CLOCK(CLK_RST_CONTROLLER_PLLM_MISC2) = 0;
// u32 tmp = (params->pllm_feedback_divider << 8) | params->pllm_input_divider | ((params->pllm_post_divider & 0xFFFF) << 20);
// CLOCK(CLK_RST_CONTROLLER_PLLM_BASE) = tmp;
// CLOCK(CLK_RST_CONTROLLER_PLLM_BASE) = tmp | 0x40000000;
CLOCK(CLK_RST_CONTROLLER_PLLM_BASE) = (params->pllm_feedback_divider << 8) | params->pllm_input_divider | 0x40000000 | ((params->pllm_post_divider & 0xFFFF) << 20); CLOCK(CLK_RST_CONTROLLER_PLLM_BASE) = (params->pllm_feedback_divider << 8) | params->pllm_input_divider | 0x40000000 | ((params->pllm_post_divider & 0xFFFF) << 20);
u32 wait_end = get_tmr_us() + 300; u32 wait_end = get_tmr_us() + 300;

5
nyx/nyx_gui/nyx.c
View file

@ -411,8 +411,13 @@ void ipl_main()
//Tegra/Horizon configuration goes to 0x80000000+, package2 goes to 0xA9800000, we place our heap in between. //Tegra/Horizon configuration goes to 0x80000000+, package2 goes to 0xA9800000, we place our heap in between.
heap_init(IPL_HEAP_START); heap_init(IPL_HEAP_START);
b_cfg = (boot_cfg_t *)(nyx_str->hekate + 0x94); b_cfg = (boot_cfg_t *)(nyx_str->hekate + 0x94);
// Important: Preserve version header!
__asm__ ("" : : "" (ipl_ver));
#if (LV_LOG_PRINTF == 1) #if (LV_LOG_PRINTF == 1)
gpio_config(GPIO_PORT_G, GPIO_PIN_0, GPIO_MODE_SPIO); gpio_config(GPIO_PORT_G, GPIO_PIN_0, GPIO_MODE_SPIO);
gpio_config(GPIO_PORT_D, GPIO_PIN_1, GPIO_MODE_GPIO); gpio_config(GPIO_PORT_D, GPIO_PIN_1, GPIO_MODE_GPIO);

2
nyx/nyx_gui/sec/tsec.c
View file

@ -212,7 +212,7 @@ int tsec_query(u8 *tsec_keys, u8 kb, tsec_ctxt_t *tsec_ctxt)
res = -6; res = -6;
smmu_deinit_for_tsec(); smmu_deinit_for_tsec();
goto out; goto out_free;
} }
// Give some extra time to make sure PKG1.1 is decrypted. // Give some extra time to make sure PKG1.1 is decrypted.

13
nyx/nyx_gui/soc/clock.c
View file

@ -32,6 +32,7 @@ static const clock_t _clock_uart[] = {
/* UART E */ { CLK_RST_CONTROLLER_RST_DEVICES_Y, CLK_RST_CONTROLLER_CLK_OUT_ENB_Y, CLK_RST_CONTROLLER_CLK_SOURCE_UARTAPE, 20, 0, 2 } /* UART E */ { CLK_RST_CONTROLLER_RST_DEVICES_Y, CLK_RST_CONTROLLER_CLK_OUT_ENB_Y, CLK_RST_CONTROLLER_CLK_SOURCE_UARTAPE, 20, 0, 2 }
}; };
//I2C default parameters - TLOW: 4, THIGH: 2, DEBOUNCE: 0 FM_DIV: 26.
static const clock_t _clock_i2c[] = { static const clock_t _clock_i2c[] = {
/* I2C1 */ { CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_I2C1, 12, 0, 19 }, //20.4MHz -> 100KHz /* I2C1 */ { CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_I2C1, 12, 0, 19 }, //20.4MHz -> 100KHz
/* I2C2 */ { CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_RST_CONTROLLER_CLK_SOURCE_I2C2, 22, 0, 4 }, //81.6MHz -> 400KHz /* I2C2 */ { CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_RST_CONTROLLER_CLK_SOURCE_I2C2, 22, 0, 4 }, //81.6MHz -> 400KHz
@ -76,7 +77,7 @@ static clock_t _clock_coresight = {
}; };
static clock_t _clock_pwm = { static clock_t _clock_pwm = {
CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_PWM, 17, 6, 4 // Freference: 6.2MHz. CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_PWM, 17, 6, 4 // Fref: 6.2MHz.
}; };
void clock_enable(const clock_t *clk) void clock_enable(const clock_t *clk)
@ -369,7 +370,7 @@ static void _clock_sdmmc_clear_enable(u32 id)
static u32 _clock_sdmmc_table[8] = { 0 }; static u32 _clock_sdmmc_table[8] = { 0 };
#define PLLP_OUT0 0x0 #define PLLP_OUT0 0x0
static int _clock_sdmmc_config_clock_source_inner(u32 *pout, u32 id, u32 val) static int _clock_sdmmc_config_clock_host(u32 *pout, u32 id, u32 val)
{ {
u32 divisor = 0; u32 divisor = 0;
u32 source = PLLP_OUT0; u32 source = PLLP_OUT0;
@ -417,6 +418,7 @@ static int _clock_sdmmc_config_clock_source_inner(u32 *pout, u32 id, u32 val)
_clock_sdmmc_table[2 * id] = val; _clock_sdmmc_table[2 * id] = val;
_clock_sdmmc_table[2 * id + 1] = *pout; _clock_sdmmc_table[2 * id + 1] = *pout;
// Set SDMMC clock.
switch (id) switch (id)
{ {
case SDMMC_1: case SDMMC_1:
@ -447,15 +449,16 @@ void clock_sdmmc_config_clock_source(u32 *pout, u32 id, u32 val)
int is_enabled = _clock_sdmmc_is_enabled(id); int is_enabled = _clock_sdmmc_is_enabled(id);
if (is_enabled) if (is_enabled)
_clock_sdmmc_clear_enable(id); _clock_sdmmc_clear_enable(id);
_clock_sdmmc_config_clock_source_inner(pout, id, val); _clock_sdmmc_config_clock_host(pout, id, val);
if (is_enabled) if (is_enabled)
_clock_sdmmc_set_enable(id); _clock_sdmmc_set_enable(id);
_clock_sdmmc_is_reset(id); _clock_sdmmc_is_reset(id);
} }
} }
void clock_sdmmc_get_params(u32 *pout, u16 *pdivisor, u32 type) void clock_sdmmc_get_card_clock_div(u32 *pout, u16 *pdivisor, u32 type)
{ {
// Get Card clock divisor.
switch (type) switch (type)
{ {
case 0: case 0:
@ -516,7 +519,7 @@ void clock_sdmmc_enable(u32 id, u32 val)
if (_clock_sdmmc_is_enabled(id)) if (_clock_sdmmc_is_enabled(id))
_clock_sdmmc_clear_enable(id); _clock_sdmmc_clear_enable(id);
_clock_sdmmc_set_reset(id); _clock_sdmmc_set_reset(id);
_clock_sdmmc_config_clock_source_inner(&div, id, val); _clock_sdmmc_config_clock_host(&div, id, val);
_clock_sdmmc_set_enable(id); _clock_sdmmc_set_enable(id);
_clock_sdmmc_is_reset(id); _clock_sdmmc_is_reset(id);
usleep((100000 + div - 1) / div); usleep((100000 + div - 1) / div);

3
nyx/nyx_gui/soc/clock.h
View file

@ -104,6 +104,7 @@
#define CLK_RST_CONTROLLER_CLK_SOURCE_SYS 0x400 #define CLK_RST_CONTROLLER_CLK_SOURCE_SYS 0x400
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1 0x410 #define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1 0x410
#define CLK_RST_CONTROLLER_CLK_SOURCE_SE 0x42C #define CLK_RST_CONTROLLER_CLK_SOURCE_SE 0x42C
#define CLK_RST_CONTROLLER_RST_DEV_V_CLR 0x434
#define CLK_RST_CONTROLLER_CLK_ENB_V_SET 0x440 #define CLK_RST_CONTROLLER_CLK_ENB_V_SET 0x440
#define CLK_RST_CONTROLLER_CLK_ENB_V_CLR 0x444 #define CLK_RST_CONTROLLER_CLK_ENB_V_CLR 0x444
#define CLK_RST_CONTROLLER_CLK_ENB_W_SET 0x448 #define CLK_RST_CONTROLLER_CLK_ENB_W_SET 0x448
@ -181,7 +182,7 @@ void clock_disable_coresight();
void clock_enable_pwm(); void clock_enable_pwm();
void clock_disable_pwm(); void clock_disable_pwm();
void clock_sdmmc_config_clock_source(u32 *pout, u32 id, u32 val); void clock_sdmmc_config_clock_source(u32 *pout, u32 id, u32 val);
void clock_sdmmc_get_params(u32 *pout, u16 *pdivisor, u32 type); void clock_sdmmc_get_card_clock_div(u32 *pout, u16 *pdivisor, u32 type);
int clock_sdmmc_is_not_reset_and_enabled(u32 id); int clock_sdmmc_is_not_reset_and_enabled(u32 id);
void clock_sdmmc_enable(u32 id, u32 val); void clock_sdmmc_enable(u32 id, u32 val);
void clock_sdmmc_disable(u32 id); void clock_sdmmc_disable(u32 id);

7
nyx/nyx_gui/soc/cluster.c
View file

@ -83,9 +83,9 @@ void cluster_boot_cpu0(u32 entry)
_cluster_enable_power(); _cluster_enable_power();
if (!(CLOCK(CLK_RST_CONTROLLER_PLLX_BASE) & 0x40000000)) if (!(CLOCK(CLK_RST_CONTROLLER_PLLX_BASE) & 0x40000000)) // PLLX_ENABLE.
{ {
CLOCK(CLK_RST_CONTROLLER_PLLX_MISC_3) &= 0xFFFFFFF7; CLOCK(CLK_RST_CONTROLLER_PLLX_MISC_3) &= 0xFFFFFFF7; // Disable IDDQ.
usleep(2); usleep(2);
CLOCK(CLK_RST_CONTROLLER_PLLX_BASE) = 0x80404E02; CLOCK(CLK_RST_CONTROLLER_PLLX_BASE) = 0x80404E02;
CLOCK(CLK_RST_CONTROLLER_PLLX_BASE) = 0x404E02; CLOCK(CLK_RST_CONTROLLER_PLLX_BASE) = 0x404E02;
@ -130,6 +130,9 @@ void cluster_boot_cpu0(u32 entry)
SB(SB_CSR) = SB_CSR_NS_RST_VEC_WR_DIS; SB(SB_CSR) = SB_CSR_NS_RST_VEC_WR_DIS;
(void)SB(SB_CSR); (void)SB(SB_CSR);
// Tighten up the security aperture.
// MC(MC_TZ_SECURITY_CTRL) = 1;
// Clear MSELECT reset. // Clear MSELECT reset.
CLOCK(CLK_RST_CONTROLLER_RST_DEVICES_V) &= 0xFFFFFFF7; CLOCK(CLK_RST_CONTROLLER_RST_DEVICES_V) &= 0xFFFFFFF7;
// Clear NONCPU reset. // Clear NONCPU reset.

1
nyx/nyx_gui/soc/fuse.h
View file

@ -54,6 +54,7 @@
#define FUSE_PRIVATE_KEY3 0x1B0 #define FUSE_PRIVATE_KEY3 0x1B0
#define FUSE_PRIVATE_KEY4 0x1B4 #define FUSE_PRIVATE_KEY4 0x1B4
#define FUSE_RESERVED_SW 0x1C0 #define FUSE_RESERVED_SW 0x1C0
#define FUSE_SKU_DIRECT_CONFIG 0x1F4
#define FUSE_OPT_VENDOR_CODE 0x200 #define FUSE_OPT_VENDOR_CODE 0x200
#define FUSE_OPT_FAB_CODE 0x204 #define FUSE_OPT_FAB_CODE 0x204
#define FUSE_OPT_LOT_CODE_0 0x208 #define FUSE_OPT_LOT_CODE_0 0x208

2
nyx/nyx_gui/soc/smmu.c
View file

@ -106,7 +106,7 @@ bool smmu_is_used()
void smmu_exit() void smmu_exit()
{ {
*(uint32_t *)(smmu_payload + 0x14) = _NOP(); *(u32 *)(smmu_payload + 0x14) = _NOP();
} }
u32 *smmu_init_domain4(u32 dev_base, u32 asid) u32 *smmu_init_domain4(u32 dev_base, u32 asid)

10
nyx/nyx_gui/soc/t210.h
View file

@ -108,6 +108,14 @@
/*! EVP registers. */ /*! EVP registers. */
#define EVP_CPU_RESET_VECTOR 0x100 #define EVP_CPU_RESET_VECTOR 0x100
#define EVP_COP_RESET_VECTOR 0x200
#define EVP_COP_UNDEF_VECTOR 0x204
#define EVP_COP_SWI_VECTOR 0x208
#define EVP_COP_PREFETCH_ABORT_VECTOR 0x20C
#define EVP_COP_DATA_ABORT_VECTOR 0x210
#define EVP_COP_RSVD_VECTOR 0x214
#define EVP_COP_IRQ_VECTOR 0x218
#define EVP_COP_FIQ_VECTOR 0x21C
/*! Misc registers. */ /*! Misc registers. */
#define APB_MISC_PP_STRAPPING_OPT_A 0x08 #define APB_MISC_PP_STRAPPING_OPT_A 0x08
@ -208,7 +216,7 @@
#define HALT_COP_JTAG (1 << 28) #define HALT_COP_JTAG (1 << 28)
#define HALT_COP_WAIT_EVENT (1 << 30) #define HALT_COP_WAIT_EVENT (1 << 30)
#define HALT_COP_WAIT_IRQ (1 << 31) #define HALT_COP_WAIT_IRQ (1 << 31)
#define HALT_COP_MAX_CNT 0xFF #define HALT_COP_MAX_CNT 0xFF
#define FLOW_CTLR_HALT_CPU0_EVENTS 0x0 #define FLOW_CTLR_HALT_CPU0_EVENTS 0x0
#define FLOW_CTLR_HALT_CPU1_EVENTS 0x14 #define FLOW_CTLR_HALT_CPU1_EVENTS 0x14
#define FLOW_CTLR_HALT_CPU2_EVENTS 0x1C #define FLOW_CTLR_HALT_CPU2_EVENTS 0x1C

2
nyx/nyx_gui/storage/nx_emmc.c
View file

@ -35,7 +35,7 @@ void nx_emmc_gpt_parse(link_t *gpt, sdmmc_storage_t *storage)
part->lba_end = ent->lba_end; part->lba_end = ent->lba_end;
part->attrs = ent->attrs; part->attrs = ent->attrs;
//HACK // ASCII conversion. Copy only the LSByte of the UTF-16LE name.
for (u32 i = 0; i < 36; i++) for (u32 i = 0; i < 36; i++)
part->name[i] = ent->name[i]; part->name[i] = ent->name[i];
part->name[36] = 0; part->name[36] = 0;

2
nyx/nyx_gui/storage/sd.h
View file

@ -40,7 +40,9 @@
#define SD_ROCR_S18A SD_OCR_S18R /* 1.8V switching accepted by card */ #define SD_ROCR_S18A SD_OCR_S18R /* 1.8V switching accepted by card */
#define SD_OCR_XPC (1 << 28) /* SDXC power control */ #define SD_OCR_XPC (1 << 28) /* SDXC power control */
#define SD_OCR_CCS (1 << 30) /* Card Capacity Status */ #define SD_OCR_CCS (1 << 30) /* Card Capacity Status */
#define SD_OCR_VDD_27_34 (0x7F << 15) /* VDD voltage 2.7 ~ 3.4 */
#define SD_OCR_VDD_32_33 (1 << 20) /* VDD voltage 3.2 ~ 3.3 */ #define SD_OCR_VDD_32_33 (1 << 20) /* VDD voltage 3.2 ~ 3.3 */
#define SD_OCR_VDD_18 (1 << 7) /* VDD voltage 1.8 */
/* /*
* SD_SWITCH argument format: * SD_SWITCH argument format:

32
nyx/nyx_gui/storage/sdmmc.c
View file

@ -223,10 +223,10 @@ static int _mmc_storage_get_op_cond_inner(sdmmc_storage_t *storage, u32 *pout, u
switch (power) switch (power)
{ {
case SDMMC_POWER_1_8: case SDMMC_POWER_1_8:
arg = 0x40000080; //Sector access, voltage. arg = SD_OCR_CCS | SD_OCR_VDD_18;
break; break;
case SDMMC_POWER_3_3: case SDMMC_POWER_3_3:
arg = 0x403F8000; //Sector access, voltage. arg = SD_OCR_CCS | SD_OCR_VDD_27_34;
break; break;
default: default:
return 0; return 0;
@ -251,7 +251,7 @@ static int _mmc_storage_get_op_cond(sdmmc_storage_t *storage, u32 power)
if (cond & MMC_CARD_BUSY) if (cond & MMC_CARD_BUSY)
{ {
if (cond & 0x40000000) if (cond & SD_OCR_CCS)
storage->has_sector_access = 1; storage->has_sector_access = 1;
return 1; return 1;
@ -572,7 +572,7 @@ DPRINTF("[MMC] BKOPS disabled\n");
if (!_mmc_storage_enable_highspeed(storage, storage->ext_csd.card_type, type)) if (!_mmc_storage_enable_highspeed(storage, storage->ext_csd.card_type, type))
return 0; return 0;
DPRINTF("[MMC] succesfully switched to highspeed mode\n"); DPRINTF("[MMC] succesfully switched to HS mode\n");
sdmmc_sd_clock_ctrl(storage->sdmmc, 1); sdmmc_sd_clock_ctrl(storage->sdmmc, 1);
@ -822,17 +822,17 @@ void _sd_storage_set_current_limit(sdmmc_storage_t *storage, u8 *buf)
switch (pwr) switch (pwr)
{ {
case SD_SET_CURRENT_LIMIT_800: case SD_SET_CURRENT_LIMIT_800:
DPRINTF("[SD] Power limit raised to 800mA\n"); DPRINTF("[SD] power limit raised to 800mA\n");
break; break;
case SD_SET_CURRENT_LIMIT_600: case SD_SET_CURRENT_LIMIT_600:
DPRINTF("[SD] Power limit raised to 600mA\n"); DPRINTF("[SD] power limit raised to 600mA\n");
break; break;
case SD_SET_CURRENT_LIMIT_400: case SD_SET_CURRENT_LIMIT_400:
DPRINTF("[SD] Power limit raised to 800mA\n"); DPRINTF("[SD] power limit raised to 800mA\n");
break; break;
default: default:
case SD_SET_CURRENT_LIMIT_200: case SD_SET_CURRENT_LIMIT_200:
DPRINTF("[SD] Power limit defaulted to 200mA\n"); DPRINTF("[SD] power limit defaulted to 200mA\n");
break; break;
} }
} }
@ -860,7 +860,7 @@ DPRINTF("[SD] SD supports selected (U)HS mode\n");
return 1; return 1;
} }
int _sd_storage_enable_highspeed_low_volt(sdmmc_storage_t *storage, u32 type, u8 *buf) int _sd_storage_enable_uhs_low_volt(sdmmc_storage_t *storage, u32 type, u8 *buf)
{ {
// Try to raise the current limit to let the card perform better. // Try to raise the current limit to let the card perform better.
_sd_storage_set_current_limit(storage, buf); _sd_storage_set_current_limit(storage, buf);
@ -881,7 +881,7 @@ int _sd_storage_enable_highspeed_low_volt(sdmmc_storage_t *storage, u32 type, u8
{ {
type = 11; type = 11;
hs_type = UHS_SDR104_BUS_SPEED; hs_type = UHS_SDR104_BUS_SPEED;
DPRINTF("[SD] Bus speed set to SDR104\n"); DPRINTF("[SD] bus speed set to SDR104\n");
storage->csd.busspeed = 104; storage->csd.busspeed = 104;
break; break;
} }
@ -890,7 +890,7 @@ DPRINTF("[SD] Bus speed set to SDR104\n");
{ {
type = 10; type = 10;
hs_type = UHS_SDR50_BUS_SPEED; hs_type = UHS_SDR50_BUS_SPEED;
DPRINTF("[SD] Bus speed set to SDR50\n"); DPRINTF("[SD] bus speed set to SDR50\n");
storage->csd.busspeed = 50; storage->csd.busspeed = 50;
break; break;
} }
@ -899,7 +899,7 @@ DPRINTF("[SD] Bus speed set to SDR50\n");
return 0; return 0;
type = 8; type = 8;
hs_type = UHS_SDR12_BUS_SPEED; hs_type = UHS_SDR12_BUS_SPEED;
DPRINTF("[SD] Bus speed set to SDR12\n"); DPRINTF("[SD] bus speed set to SDR12\n");
storage->csd.busspeed = 12; storage->csd.busspeed = 12;
break; break;
default: default:
@ -919,7 +919,7 @@ DPRINTF("[SD] config tuning\n");
return _sdmmc_storage_check_status(storage); return _sdmmc_storage_check_status(storage);
} }
int _sd_storage_enable_highspeed_high_volt(sdmmc_storage_t *storage, u8 *buf) int _sd_storage_enable_hs_high_volt(sdmmc_storage_t *storage, u8 *buf)
{ {
if (!_sd_storage_switch_get(storage, buf)) if (!_sd_storage_switch_get(storage, buf))
return 0; return 0;
@ -1068,7 +1068,7 @@ int sdmmc_storage_init_sd(sdmmc_storage_t *storage, sdmmc_t *sdmmc, u32 id, u32
{ {
int is_version_1 = 0; int is_version_1 = 0;
// Some cards (Sandisk U1), do not like a fast power cycle. Wait min 100ms. // Some cards (SanDisk U1), do not like a fast power cycle. Wait min 100ms.
sdmmc_storage_init_wait_sd(); sdmmc_storage_init_wait_sd();
memset(storage, 0, sizeof(sdmmc_storage_t)); memset(storage, 0, sizeof(sdmmc_storage_t));
@ -1169,7 +1169,7 @@ DPRINTF("[SD] SD does not support wide bus width\n");
if (storage->is_low_voltage) if (storage->is_low_voltage)
{ {
if (!_sd_storage_enable_highspeed_low_volt(storage, type, buf)) if (!_sd_storage_enable_uhs_low_volt(storage, type, buf))
{ {
free(buf); free(buf);
return 0; return 0;
@ -1178,7 +1178,7 @@ DPRINTF("[SD] enabled UHS\n");
} }
else if (type != 6 && (storage->scr.sda_vsn & 0xF) != 0) else if (type != 6 && (storage->scr.sda_vsn & 0xF) != 0)
{ {
if (!_sd_storage_enable_highspeed_high_volt(storage, buf)) if (!_sd_storage_enable_hs_high_volt(storage, buf))
{ {
free(buf); free(buf);
return 0; return 0;

4
nyx/nyx_gui/storage/sdmmc_driver.c
View file

@ -252,7 +252,7 @@ int sdmmc_setup_clock(sdmmc_t *sdmmc, u32 type)
u32 tmp; u32 tmp;
u16 divisor; u16 divisor;
clock_sdmmc_get_params(&tmp, &divisor, type); clock_sdmmc_get_card_clock_div(&tmp, &divisor, type);
clock_sdmmc_config_clock_source(&tmp, sdmmc->id, tmp); clock_sdmmc_config_clock_source(&tmp, sdmmc->id, tmp);
sdmmc->divisor = (tmp + divisor - 1) / divisor; sdmmc->divisor = (tmp + divisor - 1) / divisor;
@ -1015,7 +1015,7 @@ int sdmmc_init(sdmmc_t *sdmmc, u32 id, u32 power, u32 bus_width, u32 type, int n
u32 clock; u32 clock;
u16 divisor; u16 divisor;
clock_sdmmc_get_params(&clock, &divisor, type); clock_sdmmc_get_card_clock_div(&clock, &divisor, type);
clock_sdmmc_enable(id, clock); clock_sdmmc_enable(id, clock);
sdmmc->clock_stopped = 0; sdmmc->clock_stopped = 0;

1
nyx/nyx_gui/utils/types.h
View file

@ -20,6 +20,7 @@
#define NULL ((void *)0) #define NULL ((void *)0)
#define ALIGN(x, a) (((x) + (a) - 1) & ~((a) - 1)) #define ALIGN(x, a) (((x) + (a) - 1) & ~((a) - 1))
#define ALIGN_DOWN(x, a) (((x) - ((a) - 1)) & ~((a) - 1))
#define MAX(a, b) ((a) > (b) ? (a) : (b)) #define MAX(a, b) ((a) > (b) ? (a) : (b))
#define MIN(a, b) ((a) < (b) ? (a) : (b)) #define MIN(a, b) ((a) < (b) ? (a) : (b))