nold/hekate
1
0
Fork 0
mirror of https://github.com/CTCaer/hekate synced 2024-12-22 03:11:16 +00:00
Code Issues Projects Releases Packages Wiki Activity

lib: minerva: normalize output frequency

Browse source 
Allow frequencies that are not exact to receive proper dividers from the supported ones from table.
This commit is contained in:
CTCaer 2023-06-08 04:56:14 +03:00
parent d8d15bde44
commit 066efda4cd
1 changed files with 4 additions and 5 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

9
modules/hekate_libsys_minerva/sys_sdrammtc.c
View file

@ -1186,16 +1186,15 @@ static u32 _pllm_clk_base_cfg(u32 rate_KHz, u32 clk_src_emc, bool new_src_is_PLL
u32 i = 0; u32 i = 0;
u32 pll_ref = 38400; // Only 38.4MHz crystal is supported for T210. u32 pll_ref = 38400; // Only 38.4MHz crystal is supported for T210.
pllm_clk_config_t *pllm_clk_config; pllm_clk_config_t *pllm_clk_config = NULL;
for (i = 0; pllm_clk_config_table[i].pll_osc_in; i++) for (i = 0; pllm_clk_config_table[i].pll_osc_in; i++)
{ {
if (pllm_clk_config_table[i].pll_osc_in == pll_ref && pllm_clk_config_table[i].pll_out == rate_KHz) if (pllm_clk_config_table[i].pll_osc_in == pll_ref && (pllm_clk_config_table[i].pll_out - 19200) <= rate_KHz)
break; pllm_clk_config = &pllm_clk_config_table[i];
} }
pllm_clk_config = &pllm_clk_config_table[i]; if (pllm_clk_config && pllm_clk_config->pll_osc_in)
if (pllm_clk_config->pll_osc_in)
{ {
dividers = pllm_clk_config->pll_input_div | (pllm_clk_config->pll_feedback_div << 8) | ((pllm_clk_config->pll_post_div & 0x1F) << 20); dividers = pllm_clk_config->pll_input_div | (pllm_clk_config->pll_feedback_div << 8) | ((pllm_clk_config->pll_post_div & 0x1F) << 20);
if (new_src_is_PLLMB) if (new_src_is_PLLMB)