mirror of
https://github.com/CTCaer/hekate
synced 2024-07-03 23:13:30 +00:00
[Nyx] Prep hekate main for nyx
This commit is contained in:
ctcaer@gmail.com
parent
52478833de
commit
03872e814a
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@ -42,6 +42,8 @@ void set_default_configuration()
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h_cfg.backlight = 100;
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h_cfg.autohosoff = 0;
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h_cfg.autonogc = 1;
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h_cfg.brand = NULL;
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h_cfg.tagline = NULL;
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h_cfg.errors = 0;
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h_cfg.sept_run = EMC(EMC_SCRATCH0) & EMC_SEPT_RUN;
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h_cfg.rcm_patched = true;
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@ -104,6 +106,16 @@ int create_config_entry()
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f_puts("\nautonogc=", &fp);
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itoa(h_cfg.autonogc, lbuf, 10);
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f_puts(lbuf, &fp);
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if (h_cfg.brand)
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{
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f_puts("\nbrand=", &fp);
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f_puts(h_cfg.brand, &fp);
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}
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if (h_cfg.tagline)
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{
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f_puts("\ntagline=", &fp);
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f_puts(h_cfg.tagline, &fp);
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}
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f_puts("\n", &fp);
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if (mainIniFound)
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@ -29,6 +29,8 @@ typedef struct _hekate_config
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u32 backlight;
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u32 autohosoff;
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u32 autonogc;
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char *brand;
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char *tagline;
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// Global temporary config.
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bool se_keygen_done;
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u32 sbar_time_keeping;
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@ -32,6 +32,7 @@
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#include "../sec/se.h"
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#include "../sec/se_t210.h"
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#include "../sec/tsec.h"
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#include "../soc/bpmp.h"
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#include "../soc/cluster.h"
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#include "../soc/fuse.h"
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#include "../soc/pmc.h"
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@ -677,6 +678,9 @@ int hos_launch(ini_sec_t *cfg)
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// Clear EMC_SCRATCH0.
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EMC(EMC_SCRATCH0) = 0;
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// Flush cache and disable MMU.
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bpmp_mmu_disable();
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bpmp_clk_rate_set(BPMP_CLK_NORMAL);
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minerva_change_freq(FREQ_800);
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// Wait for secmon to get ready.
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@ -35,6 +35,7 @@
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#include "mem/sdram.h"
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#include "power/max77620.h"
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#include "rtc/max77620-rtc.h"
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#include "soc/bpmp.h"
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#include "soc/fuse.h"
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#include "soc/hw_init.h"
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#include "soc/i2c.h"
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@ -71,6 +72,8 @@ const volatile ipl_ver_meta_t __attribute__((section ("._ipl_version"))) ipl_ver
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.rsvd1 = 0
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};
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volatile nyx_storage_t *nyx_str = (nyx_storage_t *)NYX_STORAGE_ADDR;
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bool sd_mount()
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{
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if (sd_mounted)
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@ -691,8 +694,56 @@ out:
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btn_wait();
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}
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void nyx_load_run()
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{
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sd_mount();
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u8 *nyx = sd_file_read("bootloader/sys/nyx.bin", false);
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if (!nyx)
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return;
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sd_unmount();
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gfx_clear_grey(0x1B);
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u8 *BOOTLOGO = (void *)malloc(0x4000);
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blz_uncompress_srcdest(BOOTLOGO_BLZ, SZ_BOOTLOGO_BLZ, BOOTLOGO, SZ_BOOTLOGO);
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gfx_set_rect_grey(BOOTLOGO, X_BOOTLOGO, Y_BOOTLOGO, 326, 544);
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free(BOOTLOGO);
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display_backlight_brightness(h_cfg.backlight, 1000);
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nyx_str->cfg = 0;
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if (b_cfg.extra_cfg & EXTRA_CFG_NYX_DUMP)
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{
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b_cfg.extra_cfg &= ~(EXTRA_CFG_NYX_DUMP);
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nyx_str->cfg |= NYX_CFG_DUMP;
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}
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if (nyx_str->mtc_cfg.mtc_table)
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nyx_str->cfg |= NYX_CFG_MINERVA;
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nyx_str->version = ipl_ver.version - 0x303030;
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memcpy((u8 *)nyx_str->irama, (void *)IRAM_BASE, 0x8000);
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volatile reloc_meta_t *reloc = (reloc_meta_t *)(IPL_LOAD_ADDR + RELOC_META_OFF);
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memcpy((u8 *)nyx_str->hekate, (u8 *)reloc->start, reloc->end - reloc->start);
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void (*nyx_ptr)() = (void *)nyx;
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bpmp_mmu_disable();
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bpmp_clk_rate_set(BPMP_CLK_NORMAL);
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msleep(100);
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minerva_periodic_training();
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(*nyx_ptr)();
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}
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void auto_launch_firmware()
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{
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if(!h_cfg.sept_run && (b_cfg.extra_cfg & EXTRA_CFG_NYX_DUMP))
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{
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EMC(EMC_SCRATCH0) |= EMC_HEKA_UPD;
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check_sept();
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}
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if (!h_cfg.sept_run)
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auto_launch_update();
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@ -756,6 +807,16 @@ void auto_launch_firmware()
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h_cfg.autohosoff = atoi(kv->val);
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else if (!strcmp("autonogc", kv->key))
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h_cfg.autonogc = atoi(kv->val);
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else if (!strcmp("brand", kv->key))
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{
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h_cfg.brand = malloc(strlen(kv->val) + 1);
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strcpy(h_cfg.brand, kv->val);
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}
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else if (!strcmp("tagline", kv->key))
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{
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h_cfg.tagline = malloc(strlen(kv->val) + 1);
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strcpy(h_cfg.tagline, kv->val);
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}
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}
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boot_entry_id++;
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@ -949,6 +1010,9 @@ out:
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b_cfg.boot_cfg &= ~(BOOT_CFG_AUTOBOOT_EN | BOOT_CFG_FROM_LAUNCH);
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h_cfg.emummc_force_disable = false;
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nyx_load_run();
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sd_unmount();
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}
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@ -1197,6 +1261,9 @@ void ipl_main()
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display_backlight_pwm_init();
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//display_backlight_brightness(h_cfg.backlight, 1000);
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// Overclock BPMP.
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bpmp_clk_rate_set(BPMP_CLK_SUPER_BOOST);
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// Check if we had a panic while in CFW.
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secmon_exo_check_panic();
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217
bootloader/soc/bpmp.c
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217
bootloader/soc/bpmp.c
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@ -0,0 +1,217 @@
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/*
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* BPMP-Lite Cache/MMU driver for Tegra X1
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*
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* Copyright (c) 2019 CTCaer
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "bpmp.h"
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#include "clock.h"
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#include "t210.h"
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#include "../utils/util.h"
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#define BPMP_CACHE_CONFIG 0x0
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#define CFG_ENABLE (1 << 0)
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#define CFG_FORCE_WRITE_THROUGH (1 << 3)
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#define CFG_DISABLE_WRITE_BUFFER (1 << 10)
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#define CFG_DISABLE_READ_BUFFER (1 << 11)
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#define CFG_FULL_LINE_DIRTY (1 << 13)
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#define CFG_TAG_CHK_ABRT_ON_ERR (1 << 14)
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#define BPMP_CACHE_LOCK 0x4
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#define BPMP_CACHE_SIZE 0xC
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#define BPMP_CACHE_LFSR 0x10
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#define BPMP_CACHE_TAG_STATUS 0x14
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#define BPMP_CACHE_CLKEN_OVERRIDE 0x18
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#define BPMP_CACHE_MAINT_ADDR 0x20
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#define BPMP_CACHE_MAINT_DATA 0x24
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#define BPMP_CACHE_MAINT_REQ 0x28
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#define MAINT_REQ_WAY_BITMAP(x) ((x) << 8)
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#define BPMP_CACHE_INT_MASK 0x40
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#define BPMP_CACHE_INT_CLEAR 0x44
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#define INT_CLR_MAINT_DONE (1 << 0)
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#define BPMP_CACHE_INT_RAW_EVENT 0x48
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#define INT_RAW_EVENT_MAINT_DONE (1 << 0)
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#define BPMP_CACHE_INT_STATUS 0x4C
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#define BPMP_CACHE_RB_CFG 0x80
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#define BPMP_CACHE_WB_CFG 0x84
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#define BPMP_CACHE_MMU_FALLBACK_ENTRY 0xA0
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#define BPMP_CACHE_MMU_SHADOW_COPY_MASK 0xA4
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#define BPMP_CACHE_MMU_CFG 0xAC
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#define MMU_CFG_SEQ_EN (1 << 1)
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#define MMU_CFG_TLB_EN (1 << 2)
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#define MMU_CFG_ABORT_STORE_LAST (1 << 4)
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#define BPMP_CACHE_MMU_CMD 0xB0
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#define MMU_CMD_NOP 0
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#define MMU_CMD_INIT 1
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#define MMU_CMD_COPY_SHADOW 2
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#define BPMP_CACHE_MMU_ABORT_STAT 0xB4
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#define BPMP_CACHE_MMU_ABORT_ADDR 0xB8
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#define BPMP_CACHE_MMU_ACTIVE_ENTRIES 0xBC
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#define BPMP_MMU_SHADOW_ENTRY_BASE (BPMP_CACHE_BASE + 0x400)
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#define BPMP_MMU_MAIN_ENTRY_BASE (BPMP_CACHE_BASE + 0x800)
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#define MMU_ENTRY_ADDR_MASK 0xFFFFFFE0
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#define MMU_EN_CACHED (1 << 0)
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#define MMU_EN_EXEC (1 << 1)
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#define MMU_EN_READ (1 << 2)
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#define MMU_EN_WRITE (1 << 3)
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bpmp_mmu_entry_t mmu_entries[] =
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{
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{ 0x80000000, 0xFFFFFFFF, MMU_EN_READ | MMU_EN_WRITE | MMU_EN_EXEC | MMU_EN_CACHED, true },
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{ IPL_LOAD_ADDR, 0x40040000, MMU_EN_READ | MMU_EN_WRITE | MMU_EN_EXEC | MMU_EN_CACHED, true }
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};
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void bpmp_mmu_maintenance(u32 op)
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{
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if (!(BPMP_CACHE_CTRL(BPMP_CACHE_CONFIG) & CFG_ENABLE))
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return;
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//BPMP_CACHE_CTRL(BPMP_CACHE_INT_CLEAR) = INT_CLR_MAINT_DONE;
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// This is a blocking operation.
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BPMP_CACHE_CTRL(BPMP_CACHE_MAINT_REQ) = MAINT_REQ_WAY_BITMAP(0xF) | op;
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//while(!(BPMP_CACHE_CTRL(BPMP_CACHE_INT_RAW_EVENT) & INT_RAW_EVENT_MAINT_DONE))
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// ;
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//BPMP_CACHE_CTRL(BPMP_CACHE_INT_CLEAR) = BPMP_CACHE_CTRL(BPMP_CACHE_INT_RAW_EVENT);
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}
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void bpmp_mmu_set_entry(int idx, bpmp_mmu_entry_t *entry, bool apply)
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{
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if (idx > 31)
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return;
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volatile bpmp_mmu_entry_t *mmu_entry = (bpmp_mmu_entry_t *)(BPMP_MMU_SHADOW_ENTRY_BASE + sizeof(bpmp_mmu_entry_t) * idx);
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if (entry->enable)
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{
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mmu_entry->min_addr = entry->min_addr & MMU_ENTRY_ADDR_MASK;
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mmu_entry->max_addr = entry->max_addr & MMU_ENTRY_ADDR_MASK;
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mmu_entry->attr = entry->attr;
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BPMP_CACHE_CTRL(BPMP_CACHE_MMU_SHADOW_COPY_MASK) |= (1 << idx);
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if (apply)
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BPMP_CACHE_CTRL(BPMP_CACHE_MMU_CMD) = MMU_CMD_COPY_SHADOW;
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}
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}
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void bpmp_mmu_enable()
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{
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if (BPMP_CACHE_CTRL(BPMP_CACHE_CONFIG) & CFG_ENABLE)
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return;
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// Init BPMP MMU.
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BPMP_CACHE_CTRL(BPMP_CACHE_MMU_CMD) = MMU_CMD_INIT;
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BPMP_CACHE_CTRL(BPMP_CACHE_MMU_FALLBACK_ENTRY) = MMU_EN_READ | MMU_EN_WRITE | MMU_EN_EXEC; // RWX for non-defined regions.
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BPMP_CACHE_CTRL(BPMP_CACHE_MMU_CFG) = MMU_CFG_SEQ_EN | MMU_CFG_TLB_EN | MMU_CFG_ABORT_STORE_LAST;
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// Init BPMP MMU entries.
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BPMP_CACHE_CTRL(BPMP_CACHE_MMU_SHADOW_COPY_MASK) = 0;
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for (u32 idx = 0; idx < (sizeof(mmu_entries) / sizeof(bpmp_mmu_entry_t)); idx++)
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bpmp_mmu_set_entry(idx, &mmu_entries[idx], false);
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BPMP_CACHE_CTRL(BPMP_CACHE_MMU_CMD) = MMU_CMD_COPY_SHADOW;
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// Invalidate cache.
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bpmp_mmu_maintenance(BPMP_MMU_MAINT_INVALID_WAY);
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// Enable cache.
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BPMP_CACHE_CTRL(BPMP_CACHE_CONFIG) = CFG_ENABLE | CFG_FORCE_WRITE_THROUGH | CFG_TAG_CHK_ABRT_ON_ERR;
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// HW bug. Invalidate cache again.
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bpmp_mmu_maintenance(BPMP_MMU_MAINT_INVALID_WAY);
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}
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void bpmp_mmu_disable()
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{
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if (!(BPMP_CACHE_CTRL(BPMP_CACHE_CONFIG) & CFG_ENABLE))
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return;
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// Clean and invalidate cache.
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bpmp_mmu_maintenance(BPMP_MMU_MAINT_CLN_INV_WAY);
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// Enable cache.
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BPMP_CACHE_CTRL(BPMP_CACHE_CONFIG) = 0;
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// HW bug. Invalidate cache again.
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bpmp_mmu_maintenance(BPMP_MMU_MAINT_INVALID_WAY);
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}
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static u8 pllc4_divn[] = {
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0, // BPMP_CLK_NORMAL: 408MHz 0% - 136MHz APB.
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85, // BPMP_CLK_LOW_BOOST: 544MHz 33% - 136MHz APB.
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90, // BPMP_CLK_MID_BOOST: 576MHz 41% - 144MHz APB.
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95 // BPMP_CLK_SUPER_BOOST: 608MHz 49% - 152MHz APB.
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};
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bpmp_freq_t bpmp_clock_set = BPMP_CLK_NORMAL;
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void bpmp_clk_rate_set(bpmp_freq_t fid)
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{
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if (fid > (BPMP_CLK_MAX - 1))
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fid = BPMP_CLK_MAX - 1;
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if (bpmp_clock_set == fid)
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return;
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if (fid)
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{
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if (bpmp_clock_set)
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{
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// Restore to PLLP source during PLLC4 configuration.
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CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) =
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(CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) & 0xFFFF8888) | 0x3333; // PLLP_OUT.
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// Wait a bit for clock source change.
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msleep(10);
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}
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CLOCK(CLK_RST_CONTROLLER_PLLC4_MISC) = (1 << 30);
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CLOCK(CLK_RST_CONTROLLER_PLLC4_BASE) = 4 | (pllc4_divn[fid] << 8) | (1 << 30); // DIVM: 4, DIVP: 1.
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while (!(CLOCK(CLK_RST_CONTROLLER_PLLC4_BASE) & (1 << 27)))
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;
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CLOCK(CLK_RST_CONTROLLER_PLLC4_OUT) = (1 << 8) | (1 << 1); // 1.5 div.
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CLOCK(CLK_RST_CONTROLLER_PLLC4_OUT) |= 1; // Get divider out of reset.
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// Wait a bit for PLLC4 to stabilize.
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msleep(10);
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CLOCK(CLK_RST_CONTROLLER_CLK_SYSTEM_RATE) = 3; // PCLK = HCLK / 4.
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CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) =
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(CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) & 0xFFFF8888) | 0x3323; // PLLC4_OUT3.
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bpmp_clock_set = fid;
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}
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else
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{
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CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) =
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(CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) & 0xFFFF8888) | 0x3333; // PLLP_OUT.
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// Wait a bit for clock source change.
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msleep(10);
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CLOCK(CLK_RST_CONTROLLER_CLK_SYSTEM_RATE) = 2; // PCLK = HCLK / 3.
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CLOCK(CLK_RST_CONTROLLER_PLLC4_BASE) &= ~(1<<30);
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bpmp_clock_set = BPMP_CLK_NORMAL;
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}
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}
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51
bootloader/soc/bpmp.h
Normal file
51
bootloader/soc/bpmp.h
Normal file
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@ -0,0 +1,51 @@
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/*
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* BPMP-Lite Cache/MMU driver for Tegra X1
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*
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* Copyright (c) 2019 CTCaer
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*
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* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _BPMP_H_
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#define _BPMP_H_
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#include "../utils/types.h"
|
||||
|
||||
#define BPMP_MMU_MAINT_CLEAN_WAY 17
|
||||
#define BPMP_MMU_MAINT_INVALID_WAY 18
|
||||
#define BPMP_MMU_MAINT_CLN_INV_WAY 19
|
||||
|
||||
typedef struct _bpmp_mmu_entry_t
|
||||
{
|
||||
u32 min_addr;
|
||||
u32 max_addr;
|
||||
u32 attr;
|
||||
u32 enable;
|
||||
} bpmp_mmu_entry_t;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
BPMP_CLK_NORMAL, // 408MHz 0% - 136MHz APB.
|
||||
BPMP_CLK_LOW_BOOST, // 544MHz 33% - 136MHz APB.
|
||||
BPMP_CLK_MID_BOOST, // 576MHz 41% - 144MHz APB.
|
||||
BPMP_CLK_SUPER_BOOST, // 608MHz 49% - 152MHz APB.
|
||||
BPMP_CLK_MAX
|
||||
} bpmp_freq_t;
|
||||
|
||||
void bpmp_mmu_maintenance(u32 op);
|
||||
void bpmp_mmu_set_entry(int idx, bpmp_mmu_entry_t *entry, bool apply);
|
||||
void bpmp_mmu_enable();
|
||||
void bpmp_mmu_disable();
|
||||
void bpmp_clk_rate_set(bpmp_freq_t fid);
|
||||
|
||||
#endif
|
||||
|
|
@ -18,6 +18,7 @@
|
|||
#include <string.h>
|
||||
|
||||
#include "hw_init.h"
|
||||
#include "bpmp.h"
|
||||
#include "clock.h"
|
||||
#include "fuse.h"
|
||||
#include "gpio.h"
|
||||
|
|
@ -248,10 +249,15 @@ void config_hw()
|
|||
CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = (CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) & 0xFFFF8888) | 0x3333;
|
||||
|
||||
sdram_init();
|
||||
|
||||
bpmp_mmu_enable();
|
||||
}
|
||||
|
||||
void reconfig_hw_workaround(bool extra_reconfig, u32 magic)
|
||||
{
|
||||
// Flush and disable MMU.
|
||||
bpmp_mmu_disable();
|
||||
bpmp_clk_rate_set(BPMP_CLK_NORMAL);
|
||||
minerva_change_freq(FREQ_204);
|
||||
|
||||
// Re-enable clocks to Audio Processing Engine as a workaround to hanging.
|
||||
|
|
|
|||
|
|
@ -59,6 +59,9 @@ typedef int bool;
|
|||
#define EXTRA_CFG_PAYLOAD (1 << 1)
|
||||
#define EXTRA_CFG_MODULE (1 << 2)
|
||||
|
||||
#define EXTRA_CFG_NYX_RELOAD (1 << 6)
|
||||
#define EXTRA_CFG_NYX_DUMP (1 << 7)
|
||||
|
||||
typedef struct __attribute__((__packed__)) _boot_cfg_t
|
||||
{
|
||||
u8 boot_cfg;
|
||||
|
|
|
|||
|
|
@ -19,6 +19,7 @@
|
|||
#include "../gfx/di.h"
|
||||
#include "../power/max77620.h"
|
||||
#include "../rtc/max77620-rtc.h"
|
||||
#include "../soc/bpmp.h"
|
||||
#include "../soc/i2c.h"
|
||||
#include "../soc/pmc.h"
|
||||
#include "../soc/t210.h"
|
||||
|
|
@ -78,6 +79,8 @@ void panic(u32 val)
|
|||
|
||||
void reboot_normal()
|
||||
{
|
||||
bpmp_mmu_disable();
|
||||
|
||||
sd_unmount();
|
||||
display_end();
|
||||
|
||||
|
|
@ -86,6 +89,8 @@ void reboot_normal()
|
|||
|
||||
void reboot_rcm()
|
||||
{
|
||||
bpmp_mmu_disable();
|
||||
|
||||
sd_unmount();
|
||||
display_end();
|
||||
|
||||
|
|
|
|||
|
|
@ -19,6 +19,10 @@
|
|||
#define _UTIL_H_
|
||||
|
||||
#include "types.h"
|
||||
#include "../mem/minerva.h"
|
||||
|
||||
#define NYX_CFG_DUMP (1 << 7)
|
||||
#define NYX_CFG_MINERVA (1 << 8)
|
||||
|
||||
#define byte_swap_32(num) (((num >> 24) & 0xff) | ((num << 8) & 0xff0000) | \
|
||||
((num >> 8 )& 0xff00) | ((num << 24) & 0xff000000))
|
||||
|
|
@ -29,6 +33,16 @@ typedef struct _cfg_op_t
|
|||
u32 val;
|
||||
} cfg_op_t;
|
||||
|
||||
typedef struct _nyx_storage_t
|
||||
{
|
||||
u32 version;
|
||||
u32 cfg;
|
||||
u8 irama[0x8000];
|
||||
u8 hekate[0x30000];
|
||||
u8 rsvd[0x800000];
|
||||
mtc_config_t mtc_cfg;
|
||||
} nyx_storage_t;
|
||||
|
||||
u32 get_tmr_us();
|
||||
u32 get_tmr_ms();
|
||||
u32 get_tmr_s();
|
||||
|
|
|
|||
Loading…
Reference in a new issue