2018-03-26 23:04:16 +00:00
|
|
|
/*
|
|
|
|
|
* Copyright (c) 2018 naehrwert
|
|
|
|
|
*
|
|
|
|
|
* This program is free software; you can redistribute it and/or modify it
|
|
|
|
|
* under the terms and conditions of the GNU General Public License,
|
|
|
|
|
* version 2, as published by the Free Software Foundation.
|
|
|
|
|
*
|
|
|
|
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
|
|
|
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
|
|
|
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
|
|
|
|
* more details.
|
|
|
|
|
*
|
|
|
|
|
* You should have received a copy of the GNU General Public License
|
|
|
|
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
|
|
|
|
*/
|
|
|
|
|
|
2018-03-07 01:11:46 +00:00
|
|
|
#ifndef _T210_H_
|
|
|
|
|
#define _T210_H_
|
|
|
|
|
|
|
|
|
|
#include "types.h"
|
|
|
|
|
|
|
|
|
|
#define HOST1X_BASE 0x50000000
|
|
|
|
|
#define DISPLAY_A_BASE 0x54200000
|
|
|
|
|
#define DSI_BASE 0x54300000
|
|
|
|
|
#define VIC_BASE 0x54340000
|
2018-03-14 23:26:19 +00:00
|
|
|
#define TSEC_BASE 0x54500000
|
|
|
|
|
#define SOR1_BASE 0x54580000
|
2018-03-07 01:11:46 +00:00
|
|
|
#define TMR_BASE 0x60005000
|
|
|
|
|
#define CLOCK_BASE 0x60006000
|
2018-03-14 23:26:19 +00:00
|
|
|
#define FLOW_CTLR_BASE 0x60007000
|
2018-03-07 01:11:46 +00:00
|
|
|
#define SYSREG_BASE 0x6000C000
|
2018-03-14 23:26:19 +00:00
|
|
|
#define SB_BASE (SYSREG_BASE + 0x200)
|
2018-03-07 01:11:46 +00:00
|
|
|
#define GPIO_BASE 0x6000D000
|
|
|
|
|
#define GPIO_1_BASE (GPIO_BASE)
|
|
|
|
|
#define GPIO_2_BASE (GPIO_BASE + 0x100)
|
|
|
|
|
#define GPIO_3_BASE (GPIO_BASE + 0x200)
|
2018-05-01 05:15:48 +00:00
|
|
|
#define GPIO_4_BASE (GPIO_BASE + 0x300)
|
|
|
|
|
#define GPIO_5_BASE (GPIO_BASE + 0x400)
|
2018-03-07 01:11:46 +00:00
|
|
|
#define GPIO_6_BASE (GPIO_BASE + 0x500)
|
2018-05-01 05:15:48 +00:00
|
|
|
#define GPIO_7_BASE (GPIO_BASE + 0x600)
|
|
|
|
|
#define GPIO_8_BASE (GPIO_BASE + 0x700)
|
2018-03-14 23:26:19 +00:00
|
|
|
#define EXCP_VEC_BASE 0x6000F000
|
2018-05-01 05:15:48 +00:00
|
|
|
#define APB_MISC_BASE 0x70000000
|
2018-03-07 01:11:46 +00:00
|
|
|
#define PINMUX_AUX_BASE 0x70003000
|
|
|
|
|
#define UART_BASE 0x70006000
|
|
|
|
|
#define PMC_BASE 0x7000E400
|
|
|
|
|
#define SYSCTR0_BASE 0x7000F000
|
|
|
|
|
#define FUSE_BASE 0x7000F800
|
2018-05-01 05:15:48 +00:00
|
|
|
#define KFUSE_BASE 0x7000FC00
|
|
|
|
|
#define SE_BASE 0x70012000
|
2018-03-07 01:11:46 +00:00
|
|
|
#define MC_BASE 0x70019000
|
|
|
|
|
#define EMC_BASE 0x7001B000
|
|
|
|
|
#define MIPI_CAL_BASE 0x700E3000
|
|
|
|
|
#define I2S_BASE 0x702D1000
|
|
|
|
|
|
|
|
|
|
#define _REG(base, off) *(vu32 *)((base) + (off))
|
|
|
|
|
|
|
|
|
|
#define HOST1X(off) _REG(HOST1X_BASE, off)
|
|
|
|
|
#define DISPLAY_A(off) _REG(DISPLAY_A_BASE, off)
|
|
|
|
|
#define DSI(off) _REG(DSI_BASE, off)
|
|
|
|
|
#define VIC(off) _REG(VIC_BASE, off)
|
2018-03-14 23:26:19 +00:00
|
|
|
#define TSEC(off) _REG(TSEC_BASE, off)
|
|
|
|
|
#define SOR1(off) _REG(SOR1_BASE, off)
|
2018-03-07 01:11:46 +00:00
|
|
|
#define TMR(off) _REG(TMR_BASE, off)
|
|
|
|
|
#define CLOCK(off) _REG(CLOCK_BASE, off)
|
2018-03-14 23:26:19 +00:00
|
|
|
#define FLOW_CTLR(off) _REG(FLOW_CTLR_BASE, off)
|
2018-03-07 01:11:46 +00:00
|
|
|
#define SYSREG(off) _REG(SYSREG_BASE, off)
|
2018-03-14 23:26:19 +00:00
|
|
|
#define SB(off) _REG(SB_BASE, off)
|
2018-05-01 05:15:48 +00:00
|
|
|
#define GPIO(off) _REG(GPIO_BASE, off)
|
2018-03-07 01:11:46 +00:00
|
|
|
#define GPIO_1(off) _REG(GPIO_1_BASE, off)
|
|
|
|
|
#define GPIO_2(off) _REG(GPIO_2_BASE, off)
|
|
|
|
|
#define GPIO_3(off) _REG(GPIO_3_BASE, off)
|
2018-05-01 05:15:48 +00:00
|
|
|
#define GPIO_4(off) _REG(GPIO_4_BASE, off)
|
|
|
|
|
#define GPIO_5(off) _REG(GPIO_5_BASE, off)
|
2018-03-07 01:11:46 +00:00
|
|
|
#define GPIO_6(off) _REG(GPIO_6_BASE, off)
|
2018-05-01 05:15:48 +00:00
|
|
|
#define GPIO_7(off) _REG(GPIO_7_BASE, off)
|
|
|
|
|
#define GPIO_8(off) _REG(GPIO_8_BASE, off)
|
2018-03-14 23:26:19 +00:00
|
|
|
#define EXCP_VEC(off) _REG(EXCP_VEC_BASE, off)
|
2018-05-01 05:15:48 +00:00
|
|
|
#define APB_MISC(off) _REG(APB_MISC_BASE, off)
|
2018-03-07 01:11:46 +00:00
|
|
|
#define PINMUX_AUX(off) _REG(PINMUX_AUX_BASE, off)
|
|
|
|
|
#define PMC(off) _REG(PMC_BASE, off)
|
|
|
|
|
#define SYSCTR0(off) _REG(SYSCTR0_BASE, off)
|
|
|
|
|
#define FUSE(off) _REG(FUSE_BASE, off)
|
2018-05-01 05:15:48 +00:00
|
|
|
#define KFUSE(off) _REG(KFUSE_BASE, off)
|
|
|
|
|
#define SE(off) _REG(SE_BASE, off)
|
2018-03-07 01:11:46 +00:00
|
|
|
#define MC(off) _REG(MC_BASE, off)
|
|
|
|
|
#define EMC(off) _REG(EMC_BASE, off)
|
|
|
|
|
#define MIPI_CAL(off) _REG(MIPI_CAL_BASE, off)
|
|
|
|
|
#define I2S(off) _REG(I2S_BASE, off)
|
|
|
|
|
|
|
|
|
|
/*! System registers. */
|
|
|
|
|
#define AHB_ARBITRATION_XBAR_CTRL 0xE0
|
|
|
|
|
|
2018-03-14 23:26:19 +00:00
|
|
|
/*! Secure boot registers. */
|
2018-05-01 05:15:48 +00:00
|
|
|
#define SB_CSR 0x0
|
2018-03-14 23:26:19 +00:00
|
|
|
#define SB_AA64_RESET_LOW 0x30
|
|
|
|
|
#define SB_AA64_RESET_HIGH 0x34
|
|
|
|
|
|
2018-03-07 01:11:46 +00:00
|
|
|
/*! SYSCTR0 registers. */
|
|
|
|
|
#define SYSCTR0_CNTFID0 0x20
|
|
|
|
|
|
|
|
|
|
#endif
|
