mirror of
https://github.com/Atmosphere-NX/Atmosphere
synced 2024-11-16 09:59:28 +00:00
f66b41c027
exo2: Implement uncompressor stub and boot code up to Main(). exo2: implement some more init (uart/gic) exo2: implement more of init exo2: improve reg api, add keyslot flag setters exo2: implement se aes decryption/enc exo2: fix bugs in loader stub/mmu mappings exo2: start skeletoning bootconfig/global context types arch: fix makefile flags exo2: implement through master key derivation exo2: implement device master keygen exo2: more init through start of SetupSocSecurity exo2: implement pmc secure scratch management se: implement sticky bit validation libexosphere: fix building for arm32 libexo: fix makefile flags libexo: support building for arm64/arm sc7fw: skeleton binary sc7fw: skeleton a little more sc7fw: implement all non-dram functionality exo2: fix DivideUp error sc7fw: implement more dram code, fix reg library errors sc7fw: complete sc7fw impl. exo2: skeleton the rest of SetupSocSecurity exo2: implement fiq interrupt handler exo2: implement all exception handlers exo2: skeleton the entire smc api, implement the svc invoker exo2: implement rest of SetupSocSecurity exo2: correct slave security errors exo2: fix register definition exo2: minor fixes
180 lines
7.2 KiB
C++
180 lines
7.2 KiB
C++
/*
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* Copyright (c) 2018-2020 Atmosphère-NX
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <exosphere.hpp>
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namespace ams::uart {
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struct UartRegisters {
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union {
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u32 thr;
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u32 rbr;
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u32 dll;
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};
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union {
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u32 ier;
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u32 dlh;
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};
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union {
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u32 iir;
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u32 fcr;
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};
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u32 lcr;
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u32 mcr;
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u32 lsr;
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u32 msr;
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u32 spr;
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u32 irda_csr;
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u32 rx_fifo_cfg;
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u32 mie;
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u32 vendor_status;
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u32 reserved_30;
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u32 reserved_34;
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u32 reserved_38;
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u32 asr;
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};
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static_assert(util::is_pod<UartRegisters>::value);
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static_assert(sizeof(UartRegisters) == 0x40);
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/* 36.3.12 UART_VENDOR_STATUS_0_0 */
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enum UartVendorStatus {
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UART_VENDOR_STATE_TX_IDLE = 1 << 0,
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UART_VENDOR_STATE_RX_IDLE = 1 << 1,
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/* This bit is set to 1 when a read is issued to an empty FIFO and gets cleared on register read (sticky bit until read)
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0 = NO_UNDERRUN
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1 = UNDERRUN
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*/
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UART_VENDOR_STATE_RX_UNDERRUN = 1 << 2,
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/* This bit is set to 1 when write data is issued to the TX FIFO when it is already full and gets cleared on register read (sticky bit until read)
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0 = NO_OVERRUN
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1 = OVERRUN
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*/
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UART_VENDOR_STATE_TX_OVERRUN = 1 << 3,
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UART_VENDOR_STATE_RX_FIFO_COUNTER = 0b111111 << 16, /* reflects number of current entries in RX FIFO */
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UART_VENDOR_STATE_TX_FIFO_COUNTER = 0b111111 << 24 /* reflects number of current entries in TX FIFO */
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};
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/* 36.3.6 UART_LSR_0 */
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enum UartLineStatus {
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UART_LSR_RDR = 1 << 0, /* Receiver Data Ready */
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UART_LSR_OVRF = 1 << 1, /* Receiver Overrun Error */
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UART_LSR_PERR = 1 << 2, /* Parity Error */
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UART_LSR_FERR = 1 << 3, /* Framing Error */
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UART_LSR_BRK = 1 << 4, /* BREAK condition detected on line */
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UART_LSR_THRE = 1 << 5, /* Transmit Holding Register is Empty -- OK to write data */
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UART_LSR_TMTY = 1 << 6, /* Transmit Shift Register empty status */
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UART_LSR_FIFOE = 1 << 7, /* Receive FIFO Error */
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UART_LSR_TX_FIFO_FULL = 1 << 8, /* Transmitter FIFO full status */
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UART_LSR_RX_FIFO_EMPTY = 1 << 9, /* Receiver FIFO empty status */
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};
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/* 36.3.4 UART_LCR_0 */
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enum UartLineControl {
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UART_LCR_WD_LENGTH_5 = 0, /* word length 5 */
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UART_LCR_WD_LENGTH_6 = 1, /* word length 6 */
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UART_LCR_WD_LENGTH_7 = 2, /* word length 7 */
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UART_LCR_WD_LENGTH_8 = 3, /* word length 8 */
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/* STOP:
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0 = Transmit 1 stop bit
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1 = Transmit 2 stop bits (receiver always checks for 1 stop bit)
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*/
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UART_LCR_STOP = 1 << 2,
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UART_LCR_PAR = 1 << 3, /* Parity enabled */
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UART_LCR_EVEN = 1 << 4, /* Even parity format. There will always be an even number of 1s in the binary representation (PAR = 1) */
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UART_LCR_SET_P = 1 << 5, /* Set (force) parity to value in LCR[4] */
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UART_LCR_SET_B = 1 << 6, /* Set BREAK condition -- Transmitter sends all zeroes to indicate BREAK */
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UART_LCR_DLAB = 1 << 7, /* Divisor Latch Access Bit (set to allow programming of the DLH, DLM Divisors) */
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};
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/* 36.3.3 UART_IIR_FCR_0 */
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enum UartFifoControl {
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UART_FCR_FCR_EN_FIFO = 1 << 0, /* Enable the transmit and receive FIFOs. This bit should be enabled */
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UART_FCR_RX_CLR = 1 << 1, /* Clears the contents of the receive FIFO and resets its counter logic to 0 (the receive shift register is not cleared or altered). This bit returns to 0 after clearing the FIFOs */
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UART_FCR_TX_CLR = 1 << 2, /* Clears the contents of the transmit FIFO and resets its counter logic to 0 (the transmit shift register is not cleared or altered). This bit returns to 0 after clearing the FIFOs */
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/* DMA:
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0 = DMA_MODE_0
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1 = DMA_MODE_1
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*/
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UART_FCR_DMA = 1 << 3,
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/* TX_TRIG
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0 = FIFO_COUNT_GREATER_16
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1 = FIFO_COUNT_GREATER_8
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2 = FIFO_COUNT_GREATER_4
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3 = FIFO_COUNT_GREATER_1
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*/
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UART_FCR_TX_TRIG = 3 << 4,
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UART_FCR_TX_TRIG_FIFO_COUNT_GREATER_16 = 0 << 4,
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UART_FCR_TX_TRIG_FIFO_COUNT_GREATER_8 = 1 << 4,
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UART_FCR_TX_TRIG_FIFO_COUNT_GREATER_4 = 2 << 4,
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UART_FCR_TX_TRIG_FIFO_COUNT_GREATER_1 = 3 << 4,
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/* RX_TRIG
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0 = FIFO_COUNT_GREATER_1
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1 = FIFO_COUNT_GREATER_4
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2 = FIFO_COUNT_GREATER_8
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3 = FIFO_COUNT_GREATER_16
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*/
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UART_FCR_RX_TRIG = 3 << 6,
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UART_FCR_RX_TRIG_FIFO_COUNT_GREATER_1 = 0 << 6,
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UART_FCR_RX_TRIG_FIFO_COUNT_GREATER_4 = 1 << 6,
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UART_FCR_RX_TRIG_FIFO_COUNT_GREATER_8 = 2 << 6,
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UART_FCR_RX_TRIG_FIFO_COUNT_GREATER_16 = 3 << 6,
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};
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/* 36.3.2 UART_IER_DLAB_0_0 */
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enum UartInterruptEnable {
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UART_IER_IE_RHR = 1 << 0, /* Interrupt enable for Received Data Interrupt */
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UART_IER_IE_THR = 1 << 1, /* Interrupt enable for Transmitter Holding Register Empty interrupt */
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UART_IER_IE_RXS = 1 << 2, /* Interrupt enable for Receiver Line Status Interrupt */
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UART_IER_IE_MSI = 1 << 3, /* Interrupt enable for Modem Status Interrupt */
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UART_IER_IE_RX_TIMEOUT = 1 << 4, /* Interrupt enable for RX FIFO timeout */
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UART_IER_IE_EORD = 1 << 5, /* Interrupt enable for Interrupt Enable for End of Received Data */
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};
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/* 36.3.3 UART_IIR_FCR_0 */
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enum UartInterruptIdentification {
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UART_IIR_IS_STA = 1 << 0, /* Interrupt Pending if ZERO */
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UART_IIR_IS_PRI0 = 1 << 1, /* Encoded Interrupt ID Refer to IIR[3:0] table [36.3.3] */
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UART_IIR_IS_PRI1 = 1 << 2, /* Encoded Interrupt ID Refer to IIR[3:0] table */
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UART_IIR_IS_PRI2 = 1 << 3, /* Encoded Interrupt ID Refer to IIR[3:0] table */
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/* FIFO Mode Status
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0 = 16450 mode (no FIFO)
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1 = 16550 mode (FIFO)
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*/
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UART_IIR_EN_FIFO = 3 << 6,
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UART_IIR_MODE_16450 = 0 << 6,
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UART_IIR_MODE_16550 = 1 << 6,
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};
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/* 36.3.9 UART_IRDA_CSR_0 */
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enum UartIrDAPulseCodingCSR {
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UART_IRDA_CSR_INVERT_RXD = 1 << 0,
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UART_IRDA_CSR_INVERT_TXD = 1 << 1,
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UART_IRDA_CSR_INVERT_CTS = 1 << 2,
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UART_IRDA_CSR_INVERT_RTS = 1 << 3,
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UART_IRDA_CSR_PWT_A_BAUD_PULSE_3_14 = 0 << 6,
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UART_IRDA_CSR_PWT_A_BAUD_PULSE_4_14 = 1 << 6,
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UART_IRDA_CSR_SIR_A = 1 << 7,
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};
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}
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