mirror of
https://github.com/Atmosphere-NX/Atmosphere
synced 2024-09-19 22:59:00 +00:00
166318ba77
* sdmmc: begin skeletoning sdmmc driver * sdmmc: add most of SdHostStandardController * sdmmc: implement most of SdmmcController * sdmmc: Sdmmc2Controller * sdmmc: skeleton implementation of Sdmmc1Controller * sdmmc: complete abstract logic for Sdmmc1 power controller * sdmmc: implement gpio handling for sdmmc1-register-control * sdmmc: implement pinmux handling for sdmmc1-register-control * sdmmc: fix building for arm32 and in stratosphere context * sdmmc: implement voltage enable/set for sdmmc1-register-control * util: move T(V)SNPrintf from kernel to util * sdmmc: implement BaseDeviceAccessor * sdmmc: implement MmcDeviceAccessor * sdmmc: implement clock reset controller for register api * sdmmc: fix bug in WaitWhileCommandInhibit, add mmc accessors * exo: add sdmmc test program * sdmmc: fix speed mode extension, add CheckMmcConnection for debug * sdmmc: add DeviceDetector, gpio: implement client api * gpio: modernize client api instead of doing it the lazy way * sdmmc: SdCardDeviceAccessor impl * sdmmc: update test program to read first two sectors of sd card * sdmmc: fix vref sel * sdmmc: finish outward-facing api (untested) * ams: changes for libvapours including tegra register defs * sdmmc: remove hwinit
195 lines
14 KiB
PHP
195 lines
14 KiB
PHP
/*
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* Copyright (c) 2018-2020 Atmosphère-NX
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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SetRegisterAllowed(MC_INTSTATUS); /* 0x000 */
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SetRegisterAllowed(MC_INTMASK); /* 0x004 */
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SetRegisterAllowed(MC_ERR_STATUS); /* 0x008 */
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SetRegisterAllowed(MC_ERR_ADR); /* 0x00C */
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SetRegisterAllowed(MC_SMMU_CONFIG); /* 0x010 */
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SetRegisterAllowed(MC_SMMU_PTB_ASID); /* 0x01C */
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SetRegisterAllowed(MC_SMMU_PTB_DATA); /* 0x020 */
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SetRegisterAllowed(MC_SMMU_TLB_FLUSH); /* 0x030 */
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SetRegisterAllowed(MC_SMMU_PTC_FLUSH_0); /* 0x034 */
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SetRegisterAllowed(MC_EMEM_CFG); /* 0x050 */
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SetRegisterAllowed(MC_EMEM_ADR_CFG); /* 0x054 */
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SetRegisterAllowed(MC_EMEM_ARB_CFG); /* 0x090 */
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SetRegisterAllowed(MC_EMEM_ARB_OUTSTANDING_REQ); /* 0x094 */
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SetRegisterAllowed(MC_EMEM_ARB_TIMING_RCD); /* 0x098 */
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SetRegisterAllowed(MC_EMEM_ARB_TIMING_RP); /* 0x09C */
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SetRegisterAllowed(MC_EMEM_ARB_TIMING_RC); /* 0x0A0 */
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SetRegisterAllowed(MC_EMEM_ARB_TIMING_RAS); /* 0x0A4 */
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SetRegisterAllowed(MC_EMEM_ARB_TIMING_FAW); /* 0x0A8 */
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SetRegisterAllowed(MC_EMEM_ARB_TIMING_RRD); /* 0x0AC */
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SetRegisterAllowed(MC_EMEM_ARB_TIMING_RAP2PRE); /* 0x0B0 */
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SetRegisterAllowed(MC_EMEM_ARB_TIMING_WAP2PRE); /* 0x0B4 */
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SetRegisterAllowed(MC_EMEM_ARB_TIMING_R2R); /* 0x0B8 */
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SetRegisterAllowed(MC_EMEM_ARB_TIMING_W2W); /* 0x0BC */
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SetRegisterAllowed(MC_EMEM_ARB_TIMING_R2W); /* 0x0C0 */
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SetRegisterAllowed(MC_EMEM_ARB_TIMING_W2R); /* 0x0C4 */
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SetRegisterAllowed(MC_EMEM_ARB_MISC2); /* 0x0C8 */
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SetRegisterAllowed(MC_EMEM_ARB_DA_TURNS); /* 0x0D0 */
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SetRegisterAllowed(MC_EMEM_ARB_DA_COVERS); /* 0x0D4 */
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SetRegisterAllowed(MC_EMEM_ARB_MISC0); /* 0x0D8 */
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SetRegisterAllowed(MC_EMEM_ARB_MISC1); /* 0x0DC */
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SetRegisterAllowed(MC_EMEM_ARB_RING1_THROTTLE); /* 0x0E0 */
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SetRegisterAllowed(MC_CLIENT_HOTRESET_CTRL); /* 0x200 */
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SetRegisterAllowed(MC_CLIENT_HOTRESET_STATUS); /* 0x204 */
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SetRegisterAllowed(MC_SMMU_AFI_ASID); /* 0x238 */
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SetRegisterAllowed(MC_SMMU_DC_ASID); /* 0x240 */
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SetRegisterAllowed(MC_SMMU_DCB_ASID); /* 0x244 */
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SetRegisterAllowed(MC_SMMU_HC_ASID); /* 0x250 */
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SetRegisterAllowed(MC_SMMU_HDA_ASID); /* 0x254 */
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SetRegisterAllowed(MC_SMMU_ISP2_ASID); /* 0x258 */
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SetRegisterAllowed(MC_SMMU_MSENC_NVENC_ASID); /* 0x264 */
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SetRegisterAllowed(MC_SMMU_NV_ASID); /* 0x268 */
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SetRegisterAllowed(MC_SMMU_NV2_ASID); /* 0x26C */
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SetRegisterAllowed(MC_SMMU_PPCS_ASID); /* 0x270 */
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SetRegisterAllowed(MC_SMMU_SATA_ASID); /* 0x274 */
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SetRegisterAllowed(MC_SMMU_VI_ASID); /* 0x280 */
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SetRegisterAllowed(MC_SMMU_VIC_ASID); /* 0x284 */
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SetRegisterAllowed(MC_SMMU_XUSB_HOST_ASID); /* 0x288 */
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SetRegisterAllowed(MC_SMMU_XUSB_DEV_ASID); /* 0x28C */
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SetRegisterAllowed(MC_SMMU_TSEC_ASID); /* 0x294 */
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SetRegisterAllowed(MC_LATENCY_ALLOWANCE_AVPC_0); /* 0x2E4 */
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SetRegisterAllowed(MC_LATENCY_ALLOWANCE_DC_0); /* 0x2E8 */
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SetRegisterAllowed(MC_LATENCY_ALLOWANCE_DC_1); /* 0x2EC */
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SetRegisterAllowed(MC_LATENCY_ALLOWANCE_DCB_0); /* 0x2F4 */
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SetRegisterAllowed(MC_LATENCY_ALLOWANCE_DCB_1); /* 0x2F8 */
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SetRegisterAllowed(MC_LATENCY_ALLOWANCE_HC_0); /* 0x310 */
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SetRegisterAllowed(MC_LATENCY_ALLOWANCE_HC_1); /* 0x314 */
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SetRegisterAllowed(MC_LATENCY_ALLOWANCE_MPCORE_0); /* 0x320 */
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SetRegisterAllowed(MC_LATENCY_ALLOWANCE_NVENC_0); /* 0x328 */
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SetRegisterAllowed(MC_LATENCY_ALLOWANCE_PPCS_0); /* 0x344 */
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SetRegisterAllowed(MC_LATENCY_ALLOWANCE_PPCS_1); /* 0x348 */
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SetRegisterAllowed(MC_LATENCY_ALLOWANCE_ISP2_0); /* 0x370 */
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SetRegisterAllowed(MC_LATENCY_ALLOWANCE_ISP2_1); /* 0x374 */
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SetRegisterAllowed(MC_LATENCY_ALLOWANCE_XUSB_0); /* 0x37C */
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SetRegisterAllowed(MC_LATENCY_ALLOWANCE_XUSB_1); /* 0x380 */
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SetRegisterAllowed(MC_LATENCY_ALLOWANCE_TSEC_0); /* 0x390 */
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SetRegisterAllowed(MC_LATENCY_ALLOWANCE_VIC_0); /* 0x394 */
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SetRegisterAllowed(MC_LATENCY_ALLOWANCE_VI2_0); /* 0x398 */
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SetRegisterAllowed(MC_LATENCY_ALLOWANCE_GPU_0); /* 0x3AC */
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SetRegisterAllowed(MC_LATENCY_ALLOWANCE_SDMMCA_0); /* 0x3B8 */
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SetRegisterAllowed(MC_LATENCY_ALLOWANCE_SDMMCAA_0); /* 0x3BC */
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SetRegisterAllowed(MC_LATENCY_ALLOWANCE_SDMMC_0); /* 0x3C0 */
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SetRegisterAllowed(MC_LATENCY_ALLOWANCE_SDMMCAB_0); /* 0x3C4 */
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SetRegisterAllowed(MC_LATENCY_ALLOWANCE_NVDEC_0); /* 0x3D8 */
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SetRegisterAllowed(MC_LATENCY_ALLOWANCE_GPU2_0); /* 0x3E8 */
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SetRegisterAllowed(MC_DIS_PTSA_RATE); /* 0x41C */
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SetRegisterAllowed(MC_DIS_PTSA_MIN); /* 0x420 */
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SetRegisterAllowed(MC_DIS_PTSA_MAX); /* 0x424 */
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SetRegisterAllowed(MC_DISB_PTSA_RATE); /* 0x428 */
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SetRegisterAllowed(MC_DISB_PTSA_MIN); /* 0x42C */
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SetRegisterAllowed(MC_DISB_PTSA_MAX); /* 0x430 */
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SetRegisterAllowed(MC_VE_PTSA_RATE); /* 0x434 */
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SetRegisterAllowed(MC_VE_PTSA_MIN); /* 0x438 */
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SetRegisterAllowed(MC_VE_PTSA_MAX); /* 0x43C */
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SetRegisterAllowed(MC_MLL_MPCORER_PTSA_RATE); /* 0x44C */
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SetRegisterAllowed(MC_RING1_PTSA_RATE); /* 0x47C */
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SetRegisterAllowed(MC_RING1_PTSA_MIN); /* 0x480 */
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SetRegisterAllowed(MC_RING1_PTSA_MAX); /* 0x484 */
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SetRegisterAllowed(MC_PCX_PTSA_RATE); /* 0x4AC */
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SetRegisterAllowed(MC_PCX_PTSA_MIN); /* 0x4B0 */
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SetRegisterAllowed(MC_PCX_PTSA_MAX); /* 0x4B4 */
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SetRegisterAllowed(MC_MSE_PTSA_RATE); /* 0x4C4 */
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SetRegisterAllowed(MC_MSE_PTSA_MIN); /* 0x4C8 */
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SetRegisterAllowed(MC_MSE_PTSA_MAX); /* 0x4CC */
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SetRegisterAllowed(MC_AHB_PTSA_RATE); /* 0x4DC */
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SetRegisterAllowed(MC_AHB_PTSA_MIN); /* 0x4E0 */
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SetRegisterAllowed(MC_AHB_PTSA_MAX); /* 0x4E4 */
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SetRegisterAllowed(MC_APB_PTSA_RATE); /* 0x4E8 */
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SetRegisterAllowed(MC_APB_PTSA_MIN); /* 0x4EC */
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SetRegisterAllowed(MC_APB_PTSA_MAX); /* 0x4F0 */
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SetRegisterAllowed(MC_FTOP_PTSA_RATE); /* 0x50C */
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SetRegisterAllowed(MC_HOST_PTSA_RATE); /* 0x518 */
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SetRegisterAllowed(MC_HOST_PTSA_MIN); /* 0x51C */
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SetRegisterAllowed(MC_HOST_PTSA_MAX); /* 0x520 */
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SetRegisterAllowed(MC_USBX_PTSA_RATE); /* 0x524 */
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SetRegisterAllowed(MC_USBX_PTSA_MIN); /* 0x528 */
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SetRegisterAllowed(MC_USBX_PTSA_MAX); /* 0x52C */
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SetRegisterAllowed(MC_USBD_PTSA_RATE); /* 0x530 */
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SetRegisterAllowed(MC_USBD_PTSA_MIN); /* 0x534 */
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SetRegisterAllowed(MC_USBD_PTSA_MAX); /* 0x538 */
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SetRegisterAllowed(MC_GK_PTSA_RATE); /* 0x53C */
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SetRegisterAllowed(MC_GK_PTSA_MIN); /* 0x540 */
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SetRegisterAllowed(MC_GK_PTSA_MAX); /* 0x544 */
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SetRegisterAllowed(MC_AUD_PTSA_RATE); /* 0x548 */
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SetRegisterAllowed(MC_AUD_PTSA_MIN); /* 0x54C */
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SetRegisterAllowed(MC_AUD_PTSA_MAX); /* 0x550 */
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SetRegisterAllowed(MC_VICPC_PTSA_RATE); /* 0x554 */
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SetRegisterAllowed(MC_VICPC_PTSA_MIN); /* 0x558 */
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SetRegisterAllowed(MC_VICPC_PTSA_MAX); /* 0x55C */
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SetRegisterAllowed(MC_JPG_PTSA_RATE); /* 0x584 */
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SetRegisterAllowed(MC_JPG_PTSA_MIN); /* 0x588 */
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SetRegisterAllowed(MC_JPG_PTSA_MAX); /* 0x58C */
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SetRegisterAllowed(MC_GK2_PTSA_RATE); /* 0x610 */
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SetRegisterAllowed(MC_GK2_PTSA_MIN); /* 0x614 */
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SetRegisterAllowed(MC_GK2_PTSA_MAX); /* 0x618 */
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SetRegisterAllowed(MC_SDM_PTSA_RATE); /* 0x61C */
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SetRegisterAllowed(MC_SDM_PTSA_MIN); /* 0x620 */
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SetRegisterAllowed(MC_SDM_PTSA_MAX); /* 0x624 */
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SetRegisterAllowed(MC_HDAPC_PTSA_RATE); /* 0x628 */
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SetRegisterAllowed(MC_HDAPC_PTSA_MIN); /* 0x62C */
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SetRegisterAllowed(MC_HDAPC_PTSA_MAX); /* 0x630 */
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SetRegisterAllowed(MC_SEC_CARVEOUT_BOM); /* 0x670 */
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SetRegisterAllowed(MC_SEC_CARVEOUT_SIZE_MB); /* 0x674 */
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SetRegisterAllowed(MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A); /* 0x690 */
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SetRegisterAllowed(MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB); /* 0x694 */
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SetRegisterAllowed(MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B); /* 0x698 */
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SetRegisterAllowed(MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB); /* 0x69C */
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SetRegisterAllowed(MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C); /* 0x6A0 */
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SetRegisterAllowed(MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB); /* 0x6A4 */
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SetRegisterAllowed(MC_EMEM_ARB_TIMING_RFCPB); /* 0x6C0 */
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SetRegisterAllowed(MC_EMEM_ARB_TIMING_CCDMW); /* 0x6C4 */
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SetRegisterAllowed(MC_EMEM_ARB_REFPB_HP_CTRL); /* 0x6F0 */
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SetRegisterAllowed(MC_EMEM_ARB_REFPB_BANK_CTRL); /* 0x6F4 */
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SetRegisterAllowed(MC_PTSA_GRANT_DECREMENT); /* 0x960 */
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SetRegisterAllowed(MC_CLIENT_HOTRESET_CTRL_1); /* 0x970 */
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SetRegisterAllowed(MC_CLIENT_HOTRESET_STATUS_1); /* 0x974 */
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SetRegisterAllowed(MC_SMMU_PTC_FLUSH_1); /* 0x9B8 */
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SetRegisterAllowed(MC_SMMU_DC1_ASID); /* 0xA88 */
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SetRegisterAllowed(MC_SMMU_SDMMC1A_ASID); /* 0xA94 */
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SetRegisterAllowed(MC_SMMU_SDMMC2A_ASID); /* 0xA98 */
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SetRegisterAllowed(MC_SMMU_SDMMC3A_ASID); /* 0xA9C */
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SetRegisterAllowed(MC_SMMU_SDMMC4A_ASID); /* 0xAA0 */
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SetRegisterAllowed(MC_SMMU_ISP2B_ASID); /* 0xAA4 */
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SetRegisterAllowed(MC_SMMU_GPU_ASID); /* 0xAA8 */
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SetRegisterAllowed(MC_SMMU_GPUB_ASID); /* 0xAAC */
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SetRegisterAllowed(MC_SMMU_PPCS2_ASID); /* 0xAB0 */
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SetRegisterAllowed(MC_SMMU_NVDEC_ASID); /* 0xAB4 */
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SetRegisterAllowed(MC_SMMU_APE_ASID); /* 0xAB8 */
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SetRegisterAllowed(MC_SMMU_SE_ASID); /* 0xABC */
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SetRegisterAllowed(MC_SMMU_NVJPG_ASID); /* 0xAC0 */
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SetRegisterAllowed(MC_SMMU_HC1_ASID); /* 0xAC4 */
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SetRegisterAllowed(MC_SMMU_SE1_ASID); /* 0xAC8 */
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SetRegisterAllowed(MC_SMMU_AXIAP_ASID); /* 0xACC */
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SetRegisterAllowed(MC_SMMU_ETR_ASID); /* 0xAD0 */
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SetRegisterAllowed(MC_SMMU_TSECB_ASID); /* 0xAD4 */
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SetRegisterAllowed(MC_SMMU_TSEC1_ASID); /* 0xAD8 */
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SetRegisterAllowed(MC_SMMU_TSECB1_ASID); /* 0xADC */
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SetRegisterAllowed(MC_SMMU_NVDEC1_ASID); /* 0xAE0 */
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SetRegisterAllowed(MC_EMEM_ARB_DHYST_CTRL); /* 0xBCC */
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SetRegisterAllowed(MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0); /* 0xBD0 */
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SetRegisterAllowed(MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1); /* 0xBD4 */
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SetRegisterAllowed(MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2); /* 0xBD8 */
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SetRegisterAllowed(MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3); /* 0xBDC */
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SetRegisterAllowed(MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4); /* 0xBE0 */
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SetRegisterAllowed(MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5); /* 0xBE4 */
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SetRegisterAllowed(MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6); /* 0xBE8 */
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SetRegisterAllowed(MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7); /* 0xBEC */
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SetRegisterAllowed(MC_ERR_GENERALIZED_CARVEOUT_STATUS); /* 0xC00 */
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SetRegisterAllowed(MC_SECURITY_CARVEOUT2_BOM); /* 0xC5C */
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SetRegisterAllowed(MC_SECURITY_CARVEOUT3_BOM); /* 0xCAC */ |