mirror of
https://github.com/Atmosphere-NX/Atmosphere
synced 2024-09-20 15:18:59 +00:00
243 lines
11 KiB
C++
243 lines
11 KiB
C++
/*
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* Copyright (c) 2018-2020 Atmosphère-NX
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <exosphere.hpp>
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#include "../fusee_fatal.hpp"
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#include "fusee_mtc.hpp"
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#include "fusee_mtc_timing_table_erista.hpp"
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namespace ams::nxboot {
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namespace {
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constexpr inline const uintptr_t CLKRST = secmon::MemoryRegionPhysicalDeviceClkRst.GetAddress();
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static constinit bool g_next_pll = false;
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#include "fusee_mtc_tables_erista.inc"
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using EmcDvfsTimingTable = erista::EmcDvfsTimingTable;
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EmcDvfsTimingTable *GetEmcDvfsTimingTables() {
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const auto index = GetMemoryTrainingTableIndex();
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switch (index) {
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case 0:
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case 3:
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return reinterpret_cast<EmcDvfsTimingTable *>(T210SdevEmcDvfsTableS4gb01);
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case 1:
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return reinterpret_cast<EmcDvfsTimingTable *>(T210SdevEmcDvfsTableS6gb01);
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case 2:
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return reinterpret_cast<EmcDvfsTimingTable *>(T210SdevEmcDvfsTableH4gb01);
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default:
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ShowFatalError("Unknown EmcDvfsTimingTableIndex: %d\n", index);
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}
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}
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bool IsSamePll(u32 next_2x, u32 prev_2x) {
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if (next_2x == prev_2x) {
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return true;
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} else if ((next_2x == PLLM_OUT0 || next_2x == PLLM_UD) && (prev_2x == PLLM_OUT0 || prev_2x == PLLM_UD)) {
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return true;
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} else {
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return false;
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}
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}
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bool PllReprogram(u32 next_rate_khz, u32 next_clk_src, u32 prev_rate_khz, u32 prev_clk_src) {
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/* Get current pll/divp value. */
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u32 pll_base, pll_p;
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switch (reg::GetValue(CLKRST + CLK_RST_CONTROLLER_CLK_SOURCE_EMC, CLK_RST_REG_BITS_MASK(CLK_SOURCE_EMC_EMC_2X_CLK_SRC))) {
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case PLLM_UD:
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case PLLM_OUT0:
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pll_base = reg::Read(CLKRST + CLK_RST_CONTROLLER_PLLM_BASE);
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pll_p = reg::GetField(pll_base, CLK_RST_REG_BITS_MASK(PLLM_BASE_PLLM_DIVP));
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break;
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case PLLMB_UD:
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case PLLMB_OUT0:
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pll_base = reg::Read(CLKRST + CLK_RST_CONTROLLER_PLLMB_BASE);
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pll_p = reg::GetField(pll_base, CLK_RST_REG_BITS_MASK(PLLMB_BASE_PLLMB_DIVP));
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break;
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default:
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pll_base = 0;
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pll_p = 0;
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}
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/* Check pll divp. */
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if (pll_p > 5) {
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ShowFatalError("Invalid PLL divp: %" PRIu32 "\n", pll_p);
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}
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/* Get clk src/divisor. */
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const u32 next_2x = reg::GetField(next_clk_src, CLK_RST_REG_BITS_MASK(CLK_SOURCE_EMC_EMC_2X_CLK_SRC));
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const u32 prev_2x = reg::GetField(prev_clk_src, CLK_RST_REG_BITS_MASK(CLK_SOURCE_EMC_EMC_2X_CLK_SRC));
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u32 next_div = reg::GetField(next_clk_src, CLK_RST_REG_BITS_MASK(CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR));
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u32 prev_div = reg::GetField(prev_clk_src, CLK_RST_REG_BITS_MASK(CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR));
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/* Update divisor, if necessary. */
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if (next_2x == PLLM_UD || next_2x == PLLMB_UD) {
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next_div = 0;
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}
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if (prev_2x == PLLM_UD || prev_2x == PLLMB_UD) {
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prev_div = 0;
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}
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/* If the pll is different, reprogramming is necessary. */
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if (!IsSamePll(next_2x, prev_2x)) {
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return true;
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}
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/* Return whether the ratios are different. */
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const float next_freq = next_rate_khz * (1 + (next_div >> 1) + (0.5 * (next_div & 1))) * (pll_p + 1);
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const float prev_freq = prev_rate_khz * (1 + (prev_div >> 1) + (0.5 * (prev_div & 1))) * (pll_p + 1);
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const float ratio = prev_freq / next_freq;
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return ratio > 1.01 || ratio < 0.99;
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}
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u32 ProgramPllm(u32 next_rate_khz, u32 next_clk_src, bool is_pllmb) {
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/* Hardcode values for 1600MHz. */
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if (next_rate_khz != 1600000) {
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ShowFatalError("Unexpected ProgramPllm next rate %" PRIu32 "\n", next_rate_khz);
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}
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const u32 divn = 0x7D;
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const u32 divm = 0x03;
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const u32 divp = 0x00;
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const auto next_2x = reg::GetField(next_clk_src, CLK_RST_REG_BITS_MASK(CLK_SOURCE_EMC_EMC_2X_CLK_SRC));
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if (is_pllmb) {
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/* Set divisors. */
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reg::Write(CLKRST + CLK_RST_CONTROLLER_PLLMB_BASE, CLK_RST_REG_BITS_VALUE(PLLMB_BASE_PLLMB_DIVM, divm),
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CLK_RST_REG_BITS_VALUE(PLLMB_BASE_PLLMB_DIVN, divn),
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CLK_RST_REG_BITS_VALUE(PLLMB_BASE_PLLMB_DIVP, divp));
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reg::Read(CLKRST + CLK_RST_CONTROLLER_PLLMB_BASE);
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/* Set enable. */
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reg::ReadWrite(CLKRST + CLK_RST_CONTROLLER_PLLMB_BASE, CLK_RST_REG_BITS_ENUM(PLLMB_BASE_PLLMB_ENABLE, ENABLE));
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/* Adjust next clock source. */
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if (next_2x == PLLM_UD) {
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reg::SetField(next_clk_src, CLK_RST_REG_BITS_VALUE(CLK_SOURCE_EMC_EMC_2X_CLK_SRC, PLLMB_UD));
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} else if (next_2x == PLLM_OUT0) {
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reg::SetField(next_clk_src, CLK_RST_REG_BITS_VALUE(CLK_SOURCE_EMC_EMC_2X_CLK_SRC, PLLMB_OUT0));
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}
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/* Wait for pll to lock. */
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while (!reg::HasValue(CLKRST + CLK_RST_CONTROLLER_PLLMB_BASE, CLK_RST_REG_BITS_ENUM(PLLMB_BASE_PLLMB_LOCK, LOCK))) {
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/* ... */
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}
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} else {
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/* Set divisors. */
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reg::Write(CLKRST + CLK_RST_CONTROLLER_PLLM_BASE, CLK_RST_REG_BITS_VALUE(PLLM_BASE_PLLM_DIVM, divm),
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CLK_RST_REG_BITS_VALUE(PLLM_BASE_PLLM_DIVN, divn),
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CLK_RST_REG_BITS_VALUE(PLLM_BASE_PLLM_DIVP, divp));
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reg::Read(CLKRST + CLK_RST_CONTROLLER_PLLM_BASE);
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/* Set LKCDET. */
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reg::ReadWrite(CLKRST + CLK_RST_CONTROLLER_PLLM_MISC2, CLK_RST_REG_BITS_ENUM(PLLM_MISC2_PLLM_EN_LCKDET, ENABLE));
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/* Set enable. */
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reg::ReadWrite(CLKRST + CLK_RST_CONTROLLER_PLLM_BASE, CLK_RST_REG_BITS_ENUM(PLLM_BASE_PLLM_ENABLE, ENABLE));
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/* Adjust next clock source. */
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if (next_2x == PLLM_UD) {
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reg::SetField(next_clk_src, CLK_RST_REG_BITS_VALUE(CLK_SOURCE_EMC_EMC_2X_CLK_SRC, PLLM_UD));
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} else if (next_2x == PLLM_OUT0) {
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reg::SetField(next_clk_src, CLK_RST_REG_BITS_VALUE(CLK_SOURCE_EMC_EMC_2X_CLK_SRC, PLLM_OUT0));
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}
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/* Wait for pll to lock. */
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while (!reg::HasValue(CLKRST + CLK_RST_CONTROLLER_PLLM_BASE, CLK_RST_REG_BITS_ENUM(PLLM_BASE_PLLM_LOCK, LOCK))) {
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/* ... */
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}
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}
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return next_clk_src;
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}
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void Dvfs(EmcDvfsTimingTable *dst_timing_tables, EmcDvfsTimingTable *src_timing_tables, bool train) {
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/* Get the old 2x clock source. */
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const u32 prev_2x_clk_src = reg::GetValue(CLKRST + CLK_RST_CONTROLLER_CLK_SOURCE_EMC, CLK_RST_REG_BITS_MASK(CLK_SOURCE_EMC_EMC_2X_CLK_SRC));
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/* Set g_next_pll. */
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g_next_pll = prev_2x_clk_src == PLLMB_UD || prev_2x_clk_src == PLLMB_OUT0;
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/* Reprogram pll. */
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u32 next_clk_src;
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if (PllReprogram(dst_timing_tables->rate_khz, dst_timing_tables->clk_src_emc, src_timing_tables->rate_khz, src_timing_tables->clk_src_emc)) {
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if (prev_2x_clk_src == PLLMB_UD || prev_2x_clk_src == PLLMB_OUT0) {
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g_next_pll = 0;
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} else if (prev_2x_clk_src == PLLM_UD || prev_2x_clk_src == PLLM_OUT0) {
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g_next_pll = !g_next_pll;
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}
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next_clk_src = ProgramPllm(dst_timing_tables->rate_khz, dst_timing_tables->clk_src_emc, g_next_pll);
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} else {
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next_clk_src = dst_timing_tables->clk_src_emc;
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const u32 next_2x_clk_src = reg::GetField(next_clk_src, CLK_RST_REG_BITS_MASK(CLK_SOURCE_EMC_EMC_2X_CLK_SRC));
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if (next_2x_clk_src == PLLM_UD || next_2x_clk_src == PLLMB_UD) {
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if (g_next_pll) {
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reg::SetField(next_clk_src, CLK_RST_REG_BITS_VALUE(CLK_SOURCE_EMC_EMC_2X_CLK_SRC, PLLMB_UD));
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}
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} else if (next_2x_clk_src == PLLM_OUT0 || next_2x_clk_src == PLLMB_OUT0) {
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if (g_next_pll) {
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reg::SetField(next_clk_src, CLK_RST_REG_BITS_VALUE(CLK_SOURCE_EMC_EMC_2X_CLK_SRC, PLLMB_OUT0));
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}
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}
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}
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if (train) {
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TrainFreq(src_timing_tables, dst_timing_tables, next_clk_src);
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if (PllReprogram(dst_timing_tables->rate_khz, dst_timing_tables->clk_src_emc, src_timing_tables->rate_khz, src_timing_tables->clk_src_emc)) {
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g_next_pll = !g_next_pll;
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}
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} else {
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FreqChange(src_timing_tables, dst_timing_tables, next_clk_src);
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}
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}
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}
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void DoMemoryTrainingErista() {
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/* Get timing tables. */
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auto *timing_tables = GetEmcDvfsTimingTables();
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auto *src_timing_tables = timing_tables + 0;
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auto *dst_timing_tables = timing_tables + 1;
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/* Check timing tables. */
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if (src_timing_tables->rate_khz != 204000 || dst_timing_tables->rate_khz != 1600000) {
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ShowFatalError("EmcDvfsTimingTables seem corrupted %" PRIu32 " %" PRIu32 "?\n", src_timing_tables->rate_khz, dst_timing_tables->rate_khz);
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}
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/* Check that we should do training. */
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if (src_timing_tables->clk_src_emc != reg::Read(CLKRST + CLK_RST_CONTROLLER_CLK_SOURCE_EMC)) {
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/* Our clock source isn't what's expected, so presumably training has already been done? */
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/* Either way, the safe bet is to skip it. */
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return;
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}
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/* Train 1600MHz. */
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Dvfs(dst_timing_tables, src_timing_tables, true);
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/* Switch to 1600MHz. */
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Dvfs(dst_timing_tables, src_timing_tables, false);
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/* TODO: Periodic compensation */
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}
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}
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