mirror of
https://github.com/Atmosphere-NX/Atmosphere
synced 2024-09-20 07:08:59 +00:00
501 lines
23 KiB
C++
501 lines
23 KiB
C++
/*
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* Copyright (c) 2018-2020 Atmosphère-NX
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "boot_display.hpp"
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#include "boot_i2c_utils.hpp"
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#include "boot_pmc_wrapper.hpp"
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#include "boot_registers_clkrst.hpp"
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#include "boot_registers_di.hpp"
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#include "boot_registers_gpio.hpp"
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#include "boot_registers_pinmux.hpp"
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#include "boot_registers_pmc.hpp"
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namespace ams::boot {
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/* Display configuration included into anonymous namespace. */
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namespace {
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#include "boot_display_config.inc"
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}
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namespace {
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/* Helpful defines. */
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constexpr size_t DeviceAddressSpaceAlignSize = 0x400000;
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constexpr size_t DeviceAddressSpaceAlignMask = DeviceAddressSpaceAlignSize - 1;
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constexpr uintptr_t FrameBufferPaddr = DisplayConfigFrameBufferAddress;
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constexpr size_t FrameBufferWidth = 768;
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constexpr size_t FrameBufferHeight = 1280;
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constexpr size_t FrameBufferSize = FrameBufferHeight * FrameBufferWidth * sizeof(u32);
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constexpr uintptr_t Disp1Base = 0x54200000ul;
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constexpr uintptr_t DsiBase = 0x54300000ul;
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constexpr uintptr_t ClkRstBase = 0x60006000ul;
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constexpr uintptr_t GpioBase = 0x6000D000ul;
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constexpr uintptr_t ApbMiscBase = 0x70000000ul;
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constexpr uintptr_t MipiCalBase = 0x700E3000ul;
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constexpr size_t Disp1Size = 3 * os::MemoryPageSize;
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constexpr size_t DsiSize = os::MemoryPageSize;
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constexpr size_t ClkRstSize = os::MemoryPageSize;
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constexpr size_t GpioSize = os::MemoryPageSize;
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constexpr size_t ApbMiscSize = os::MemoryPageSize;
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constexpr size_t MipiCalSize = os::MemoryPageSize;
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/* Types. */
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/* Globals. */
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bool g_is_display_intialized = false;
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u32 *g_frame_buffer = nullptr;
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bool g_is_mariko = false;
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u32 g_lcd_vendor = 0;
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Handle g_dc_das_hnd = INVALID_HANDLE;
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u8 g_frame_buffer_storage[DeviceAddressSpaceAlignSize + FrameBufferSize];
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uintptr_t g_disp1_regs = 0;
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uintptr_t g_dsi_regs = 0;
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uintptr_t g_clk_rst_regs = 0;
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uintptr_t g_gpio_regs = 0;
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uintptr_t g_apb_misc_regs = 0;
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uintptr_t g_mipi_cal_regs = 0;
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/* Helper functions. */
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void InitializeRegisterBaseAddresses() {
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g_disp1_regs = dd::GetIoMapping(Disp1Base, Disp1Size);
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g_dsi_regs = dd::GetIoMapping(DsiBase, DsiSize);
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g_clk_rst_regs = dd::GetIoMapping(ClkRstBase, ClkRstSize);
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g_gpio_regs = dd::GetIoMapping(GpioBase, GpioSize);
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g_apb_misc_regs = dd::GetIoMapping(ApbMiscBase, ApbMiscSize);
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g_mipi_cal_regs = dd::GetIoMapping(MipiCalBase, MipiCalSize);
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}
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inline void DoRegisterWrites(uintptr_t base_address, const RegisterWrite *reg_writes, size_t num_writes) {
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for (size_t i = 0; i < num_writes; i++) {
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reg::Write(base_address + reg_writes[i].offset, reg_writes[i].value);
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}
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}
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inline void DoSocDependentRegisterWrites(uintptr_t base_address, const RegisterWrite *reg_writes_erista, size_t num_writes_erista, const RegisterWrite *reg_writes_mariko, size_t num_writes_mariko) {
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if (g_is_mariko) {
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DoRegisterWrites(base_address, reg_writes_mariko, num_writes_mariko);
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} else {
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DoRegisterWrites(base_address, reg_writes_erista, num_writes_erista);
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}
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}
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inline void DoDsiSleepOrRegisterWrites(const DsiSleepOrRegisterWrite *reg_writes, size_t num_writes) {
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for (size_t i = 0; i < num_writes; i++) {
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switch (reg_writes[i].kind) {
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case DsiSleepOrRegisterWriteKind_Write:
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reg::Write(g_dsi_regs + sizeof(u32) * reg_writes[i].offset, reg_writes[i].value);
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break;
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case DsiSleepOrRegisterWriteKind_Sleep:
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svcSleepThread(1'000'000ul * u64(reg_writes[i].offset));
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break;
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AMS_UNREACHABLE_DEFAULT_CASE();
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}
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}
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}
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#define DO_REGISTER_WRITES(base_address, writes) DoRegisterWrites(base_address, writes, util::size(writes))
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#define DO_SOC_DEPENDENT_REGISTER_WRITES(base_address, writes) DoSocDependentRegisterWrites(base_address, writes##Erista, util::size(writes##Erista), writes##Mariko, util::size(writes##Mariko))
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#define DO_DSI_SLEEP_OR_REGISTER_WRITES(writes) DoDsiSleepOrRegisterWrites(writes, util::size(writes))
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void InitializeFrameBuffer() {
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if (g_frame_buffer != nullptr) {
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std::memset(g_frame_buffer, 0x00, FrameBufferSize);
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armDCacheFlush(g_frame_buffer, FrameBufferSize);
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} else {
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const uintptr_t frame_buffer_aligned = ((reinterpret_cast<uintptr_t>(g_frame_buffer_storage) + DeviceAddressSpaceAlignMask) & ~uintptr_t(DeviceAddressSpaceAlignMask));
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g_frame_buffer = reinterpret_cast<u32 *>(frame_buffer_aligned);
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std::memset(g_frame_buffer, 0x00, FrameBufferSize);
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armDCacheFlush(g_frame_buffer, FrameBufferSize);
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/* Create Address Space. */
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R_ABORT_UNLESS(svcCreateDeviceAddressSpace(&g_dc_das_hnd, 0, (1ul << 32)));
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/* Attach it to the DC. */
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R_ABORT_UNLESS(svcAttachDeviceAddressSpace(svc::DeviceName_Dc, g_dc_das_hnd));
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/* Map the framebuffer for the DC as read-only. */
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R_ABORT_UNLESS(svcMapDeviceAddressSpaceAligned(g_dc_das_hnd, dd::GetCurrentProcessHandle(), frame_buffer_aligned, FrameBufferSize, FrameBufferPaddr, 1));
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}
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}
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void FinalizeFrameBuffer() {
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if (g_frame_buffer != nullptr) {
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const uintptr_t frame_buffer_aligned = reinterpret_cast<uintptr_t>(g_frame_buffer);
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/* Unmap the framebuffer from the DC. */
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R_ABORT_UNLESS(svcUnmapDeviceAddressSpace(g_dc_das_hnd, dd::GetCurrentProcessHandle(), frame_buffer_aligned, FrameBufferSize, FrameBufferPaddr));
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/* Detach address space from the DC. */
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R_ABORT_UNLESS(svcDetachDeviceAddressSpace(svc::DeviceName_Dc, g_dc_das_hnd));
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/* Close the address space. */
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R_ABORT_UNLESS(svcCloseHandle(g_dc_das_hnd));
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g_dc_das_hnd = INVALID_HANDLE;
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g_frame_buffer = nullptr;
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}
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}
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void WaitDsiTrigger() {
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os::TimeoutHelper timeout_helper(250'000'000ul);
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while (true) {
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if (timeout_helper.TimedOut()) {
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break;
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}
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if (reg::Read(g_dsi_regs + sizeof(u32) * DSI_TRIGGER) == 0) {
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break;
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}
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}
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svcSleepThread(5'000'000ul);
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}
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void WaitDsiHostControl() {
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os::TimeoutHelper timeout_helper(150'000'000ul);
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while (true) {
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if (timeout_helper.TimedOut()) {
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break;
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}
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if ((reg::Read(g_dsi_regs + sizeof(u32) * DSI_HOST_CONTROL) & DSI_HOST_CONTROL_IMM_BTA) == 0) {
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break;
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}
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}
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}
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}
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void InitializeDisplay() {
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/* Setup globals. */
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InitializeRegisterBaseAddresses();
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g_is_mariko = spl::IsMariko();
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InitializeFrameBuffer();
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/* Turn on DSI/voltage rail. */
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{
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i2c::driver::Session i2c_session;
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i2c::driver::Initialize();
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ON_SCOPE_EXIT { i2c::driver::Finalize(); };
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i2c::driver::OpenSession(&i2c_session, I2cDevice_Max77620Pmic);
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if (g_is_mariko) {
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WriteI2cRegister(i2c_session, 0x18, 0x3A);
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WriteI2cRegister(i2c_session, 0x1F, 0x71);
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}
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WriteI2cRegister(i2c_session, 0x23, 0xD0);
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}
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/* Enable MIPI CAL, DSI, DISP1, HOST1X, UART_FST_MIPI_CAL, DSIA LP clocks. */
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reg::Write(g_clk_rst_regs + CLK_RST_CONTROLLER_RST_DEV_H_CLR, 0x1010000);
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reg::Write(g_clk_rst_regs + CLK_RST_CONTROLLER_CLK_ENB_H_SET, 0x1010000);
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reg::Write(g_clk_rst_regs + CLK_RST_CONTROLLER_RST_DEV_L_CLR, 0x18000000);
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reg::Write(g_clk_rst_regs + CLK_RST_CONTROLLER_CLK_ENB_L_SET, 0x18000000);
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reg::Write(g_clk_rst_regs + CLK_RST_CONTROLLER_CLK_ENB_X_SET, 0x20000);
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reg::Write(g_clk_rst_regs + CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL, 0xA);
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reg::Write(g_clk_rst_regs + CLK_RST_CONTROLLER_CLK_ENB_W_SET, 0x80000);
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reg::Write(g_clk_rst_regs + CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP, 0xA);
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/* DPD idle. */
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WritePmcRegister(PmcBase + APBDEV_PMC_IO_DPD_REQ, 0x40000000);
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WritePmcRegister(PmcBase + APBDEV_PMC_IO_DPD2_REQ, 0x40000000);
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/* Configure LCD pinmux tristate + passthrough. */
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reg::ClearBits(g_apb_misc_regs + 0x3000 + PINMUX_AUX_NFC_EN, PINMUX_TRISTATE);
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reg::ClearBits(g_apb_misc_regs + 0x3000 + PINMUX_AUX_NFC_INT, PINMUX_TRISTATE);
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reg::ClearBits(g_apb_misc_regs + 0x3000 + PINMUX_AUX_LCD_BL_PWM, PINMUX_TRISTATE);
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reg::ClearBits(g_apb_misc_regs + 0x3000 + PINMUX_AUX_LCD_BL_EN, PINMUX_TRISTATE);
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reg::ClearBits(g_apb_misc_regs + 0x3000 + PINMUX_AUX_LCD_RST, PINMUX_TRISTATE);
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/* Configure LCD power, VDD. */
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reg::SetBits(g_gpio_regs + GPIO_PORT3_CNF_0, 0x3);
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reg::SetBits(g_gpio_regs + GPIO_PORT3_OE_0, 0x3);
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reg::SetBits(g_gpio_regs + GPIO_PORT3_OUT_0, 0x1);
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svcSleepThread(10'000'000ul);
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reg::SetBits(g_gpio_regs + GPIO_PORT3_OUT_0, 0x2);
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svcSleepThread(10'000'000ul);
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/* Configure LCD backlight. */
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reg::SetBits(g_gpio_regs + GPIO_PORT6_CNF_1, 0x7);
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reg::SetBits(g_gpio_regs + GPIO_PORT6_OE_1, 0x7);
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reg::SetBits(g_gpio_regs + GPIO_PORT6_OUT_1, 0x2);
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/* Configure display interface and display. */
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reg::Write(g_mipi_cal_regs + 0x060, 0);
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if (g_is_mariko) {
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reg::Write(g_mipi_cal_regs + 0x058, 0);
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reg::Write(g_apb_misc_regs + 0xAC0, 0);
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}
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/* Execute configs. */
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DO_SOC_DEPENDENT_REGISTER_WRITES(g_clk_rst_regs, DisplayConfigPlld01);
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DO_REGISTER_WRITES(g_disp1_regs, DisplayConfigDc01);
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DO_REGISTER_WRITES(g_dsi_regs, DisplayConfigDsi01Init01);
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/* NOTE: Nintendo bug here. */
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/* As of 8.0.0, Nintendo writes this list to CAR instead of DSI */
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/* This results in them zeroing CLK_SOURCE_UARTA... */
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DO_SOC_DEPENDENT_REGISTER_WRITES(g_dsi_regs, DisplayConfigDsi01Init02);
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DO_REGISTER_WRITES(g_dsi_regs, DisplayConfigDsi01Init03);
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DO_SOC_DEPENDENT_REGISTER_WRITES(g_dsi_regs, DisplayConfigDsi01Init04);
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DO_REGISTER_WRITES(g_dsi_regs, DisplayConfigDsi01Init05);
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DO_SOC_DEPENDENT_REGISTER_WRITES(g_dsi_regs, DisplayConfigDsiPhyTiming);
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DO_REGISTER_WRITES(g_dsi_regs, DisplayConfigDsi01Init06);
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DO_SOC_DEPENDENT_REGISTER_WRITES(g_dsi_regs, DisplayConfigDsiPhyTiming);
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DO_REGISTER_WRITES(g_dsi_regs, DisplayConfigDsi01Init07);
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svcSleepThread(10'000'000ul);
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/* Enable backlight reset. */
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reg::SetBits(g_gpio_regs + GPIO_PORT6_OUT_1, 0x4);
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svcSleepThread(60'000'000ul);
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reg::Write(g_dsi_regs + sizeof(u32) * DSI_BTA_TIMING, 0x50204);
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reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x337);
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reg::Write(g_dsi_regs + sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST);
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WaitDsiTrigger();
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reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x406);
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reg::Write(g_dsi_regs + sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST);
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WaitDsiTrigger();
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reg::Write(g_dsi_regs + sizeof(u32) * DSI_HOST_CONTROL, DSI_HOST_CONTROL_TX_TRIG_HOST | DSI_HOST_CONTROL_IMM_BTA | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC);
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WaitDsiHostControl();
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svcSleepThread(5'000'000ul);
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/* Parse LCD vendor. */
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{
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u32 host_response[3];
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for (size_t i = 0; i < util::size(host_response); i++) {
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host_response[i] = reg::Read(g_dsi_regs + sizeof(u32) * DSI_RD_DATA);
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}
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/* The last word from host response is:
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Bits 0-7: FAB
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Bits 8-15: REV
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Bits 16-23: Minor REV
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*/
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if ((host_response[2] & 0xFF) == 0x10) {
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g_lcd_vendor = 0;
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} else {
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g_lcd_vendor = (host_response[2] >> 8) & 0xFF00;
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}
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g_lcd_vendor = (g_lcd_vendor & 0xFFFFFF00) | (host_response[2] & 0xFF);
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}
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/* LCD vendor specific configuration. */
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switch (g_lcd_vendor) {
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case 0xF30: /* AUO first revision screens. */
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reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x1105);
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reg::Write(g_dsi_regs + sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST);
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svcSleepThread(180'000'000ul);
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reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x439);
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reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x9483FFB9);
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reg::Write(g_dsi_regs + sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST);
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svcSleepThread(5'000'000ul);
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reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x739);
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reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x711148B1);
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reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x143209);
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reg::Write(g_dsi_regs + sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST);
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svcSleepThread(5'000'000ul);
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reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x2905);
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reg::Write(g_dsi_regs + sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST);
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break;
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case 0xF20: /* Innolux first revision screens. */
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reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x1105);
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reg::Write(g_dsi_regs + sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST);
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svcSleepThread(180'000'000ul);
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reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x439);
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reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x9483FFB9);
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reg::Write(g_dsi_regs + sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST);
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svcSleepThread(5'000'000ul);
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reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x739);
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reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x751548B1);
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reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x143209);
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reg::Write(g_dsi_regs + sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST);
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svcSleepThread(5'000'000ul);
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reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x2905);
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reg::Write(g_dsi_regs + sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST);
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break;
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case 0x10: /* Japan Display Inc screens. */
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DO_DSI_SLEEP_OR_REGISTER_WRITES(DisplayConfigJdiSpecificInit01);
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break;
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default:
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/* Innolux and AUO second revision screens. */
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if ((g_lcd_vendor | 0x10) == 0x1030) {
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reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x1105);
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reg::Write(g_dsi_regs + sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST);
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svcSleepThread(120'000'000ul);
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reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x2905);
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reg::Write(g_dsi_regs + sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST);
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}
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break;
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}
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svcSleepThread(20'000'000ul);
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DO_SOC_DEPENDENT_REGISTER_WRITES(g_clk_rst_regs, DisplayConfigPlld02);
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DO_REGISTER_WRITES(g_dsi_regs, DisplayConfigDsi01Init08);
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DO_SOC_DEPENDENT_REGISTER_WRITES(g_dsi_regs, DisplayConfigDsiPhyTiming);
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DO_REGISTER_WRITES(g_dsi_regs, DisplayConfigDsi01Init09);
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reg::Write(g_disp1_regs + sizeof(u32) * DC_DISP_DISP_CLOCK_CONTROL, SHIFT_CLK_DIVIDER(4));
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DO_REGISTER_WRITES(g_dsi_regs, DisplayConfigDsi01Init10);
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svcSleepThread(10'000'000ul);
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/* Configure MIPI CAL. */
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DO_REGISTER_WRITES(g_mipi_cal_regs, DisplayConfigMipiCal01);
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DO_SOC_DEPENDENT_REGISTER_WRITES(g_mipi_cal_regs, DisplayConfigMipiCal02);
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DO_SOC_DEPENDENT_REGISTER_WRITES(g_dsi_regs, DisplayConfigDsi01Init11);
|
|
DO_SOC_DEPENDENT_REGISTER_WRITES(g_mipi_cal_regs, DisplayConfigMipiCal03);
|
|
DO_REGISTER_WRITES(g_mipi_cal_regs, DisplayConfigMipiCal04);
|
|
if (g_is_mariko) {
|
|
/* On Mariko the above configurations are executed twice, for some reason. */
|
|
DO_SOC_DEPENDENT_REGISTER_WRITES(g_mipi_cal_regs, DisplayConfigMipiCal02);
|
|
DO_SOC_DEPENDENT_REGISTER_WRITES(g_dsi_regs, DisplayConfigDsi01Init11);
|
|
DO_SOC_DEPENDENT_REGISTER_WRITES(g_mipi_cal_regs, DisplayConfigMipiCal03);
|
|
DO_REGISTER_WRITES(g_mipi_cal_regs, DisplayConfigMipiCal04);
|
|
}
|
|
svcSleepThread(10'000'000ul);
|
|
|
|
/* Write DISP1, FrameBuffer config. */
|
|
DO_REGISTER_WRITES(g_disp1_regs, DisplayConfigDc02);
|
|
DO_REGISTER_WRITES(g_disp1_regs, DisplayConfigFrameBuffer);
|
|
svcSleepThread(35'000'000ul);
|
|
g_is_display_intialized = true;
|
|
}
|
|
|
|
void ShowDisplay(size_t x, size_t y, size_t width, size_t height, const u32 *img) {
|
|
if (!g_is_display_intialized) {
|
|
return;
|
|
}
|
|
|
|
/* Draw the image to the screen. */
|
|
std::memset(g_frame_buffer, 0, FrameBufferSize);
|
|
{
|
|
for (size_t cur_y = 0; cur_y < height; cur_y++) {
|
|
for (size_t cur_x = 0; cur_x < width; cur_x++) {
|
|
g_frame_buffer[(FrameBufferHeight - (x + cur_x)) * FrameBufferWidth + y + cur_y] = img[cur_y * width + cur_x];
|
|
}
|
|
}
|
|
}
|
|
armDCacheFlush(g_frame_buffer, FrameBufferSize);
|
|
|
|
/* Enable backlight. */
|
|
reg::SetBits(g_gpio_regs + GPIO_PORT6_OUT_1, 0x1);
|
|
}
|
|
|
|
void FinalizeDisplay() {
|
|
if (!g_is_display_intialized) {
|
|
return;
|
|
}
|
|
|
|
/* Disable backlight. */
|
|
reg::ClearBits(g_gpio_regs + GPIO_PORT6_OUT_1, 0x1);
|
|
|
|
reg::Write(g_disp1_regs + sizeof(u32) * DSI_VIDEO_MODE_CONTROL, 1);
|
|
reg::Write(g_disp1_regs + sizeof(u32) * DSI_WR_DATA, 0x2805);
|
|
|
|
/* Nintendo waits 5 frames before continuing. */
|
|
{
|
|
const uintptr_t host1x_vaddr = dd::GetIoMapping(0x500030a4, 4);
|
|
const u32 start_val = reg::Read(host1x_vaddr);
|
|
while (reg::Read(host1x_vaddr) < start_val + 5) {
|
|
/* spinlock here. */
|
|
}
|
|
}
|
|
|
|
reg::Write(g_disp1_regs + sizeof(u32) * DC_CMD_STATE_ACCESS, (READ_MUX | WRITE_MUX));
|
|
reg::Write(g_disp1_regs + sizeof(u32) * DSI_VIDEO_MODE_CONTROL, 0);
|
|
|
|
|
|
DO_SOC_DEPENDENT_REGISTER_WRITES(g_clk_rst_regs, DisplayConfigPlld01);
|
|
DO_REGISTER_WRITES(g_dsi_regs, DisplayConfigDsi01Fini01);
|
|
DO_SOC_DEPENDENT_REGISTER_WRITES(g_dsi_regs, DisplayConfigDsiPhyTiming);
|
|
DO_REGISTER_WRITES(g_dsi_regs, DisplayConfigDsi01Fini02);
|
|
|
|
svcSleepThread(10'000'000ul);
|
|
|
|
/* Vendor specific shutdown. */
|
|
switch (g_lcd_vendor) {
|
|
case 0x10: /* Japan Display Inc screens. */
|
|
DO_REGISTER_WRITES(g_dsi_regs, DisplayConfigJdiSpecificFini01);
|
|
break;
|
|
case 0xF30: /* AUO first revision screens. */
|
|
DO_REGISTER_WRITES(g_dsi_regs, DisplayConfigAuoRev1SpecificFini01);
|
|
svcSleepThread(5'000'000ul);
|
|
break;
|
|
case 0x1020: /* Innolux second revision screens. */
|
|
reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x439);
|
|
reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x9483FFB9);
|
|
reg::Write(g_dsi_regs + sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST);
|
|
svcSleepThread(5'000'000ul);
|
|
reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0xB39);
|
|
reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x751548B1);
|
|
reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x71143209);
|
|
reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x115631);
|
|
reg::Write(g_dsi_regs + sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST);
|
|
svcSleepThread(5'000'000ul);
|
|
break;
|
|
case 0x1030: /* AUO second revision screens. */
|
|
reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x439);
|
|
reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x9483FFB9);
|
|
reg::Write(g_dsi_regs + sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST);
|
|
svcSleepThread(5'000'000ul);
|
|
reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0xB39);
|
|
reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x711148B1);
|
|
reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x71143209);
|
|
reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x114D31);
|
|
reg::Write(g_dsi_regs + sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST);
|
|
svcSleepThread(5'000'000ul);
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
svcSleepThread(5'000'000ul);
|
|
|
|
reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x1005);
|
|
reg::Write(g_dsi_regs + sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST);
|
|
svcSleepThread(50'000'000ul);
|
|
|
|
/* Disable backlight RST/Voltage. */
|
|
reg::ClearBits(g_gpio_regs + GPIO_PORT6_OUT_1, 0x4);
|
|
svcSleepThread(10'000'000ul);
|
|
reg::ClearBits(g_gpio_regs + GPIO_PORT3_OUT_0, 0x2);
|
|
svcSleepThread(10'000'000ul);
|
|
reg::ClearBits(g_gpio_regs + GPIO_PORT3_OUT_0, 0x1);
|
|
svcSleepThread(10'000'000ul);
|
|
|
|
/* Cut clock to DSI. */
|
|
reg::Write(g_clk_rst_regs + CLK_RST_CONTROLLER_RST_DEV_H_SET, 0x1010000);
|
|
reg::Write(g_clk_rst_regs + CLK_RST_CONTROLLER_CLK_ENB_H_CLR, 0x1010000);
|
|
reg::Write(g_clk_rst_regs + CLK_RST_CONTROLLER_RST_DEV_L_SET, 0x18000000);
|
|
reg::Write(g_clk_rst_regs + CLK_RST_CONTROLLER_CLK_ENB_L_CLR, 0x18000000);
|
|
reg::Write(g_dsi_regs + sizeof(u32) * DSI_PAD_CONTROL_0, (DSI_PAD_CONTROL_VS1_PULLDN_CLK | DSI_PAD_CONTROL_VS1_PULLDN(0xF) | DSI_PAD_CONTROL_VS1_PDIO_CLK | DSI_PAD_CONTROL_VS1_PDIO(0xF)));
|
|
reg::Write(g_dsi_regs + sizeof(u32) * DSI_POWER_CONTROL, 0);
|
|
|
|
/* Final LCD config for PWM */
|
|
reg::ClearBits(g_gpio_regs + GPIO_PORT6_CNF_1, 0x1);
|
|
reg::SetBits(g_apb_misc_regs + 0x3000 + PINMUX_AUX_LCD_BL_PWM, PINMUX_TRISTATE);
|
|
reg::ReadWrite(g_apb_misc_regs + 0x3000 + PINMUX_AUX_LCD_BL_PWM, 1, 0x3);
|
|
|
|
/* Unmap framebuffer from DC virtual address space. */
|
|
FinalizeFrameBuffer();
|
|
g_is_display_intialized = false;
|
|
}
|
|
|
|
}
|