mirror of
https://github.com/Atmosphere-NX/Atmosphere
synced 2024-11-10 15:16:34 +00:00
f66b41c027
exo2: Implement uncompressor stub and boot code up to Main(). exo2: implement some more init (uart/gic) exo2: implement more of init exo2: improve reg api, add keyslot flag setters exo2: implement se aes decryption/enc exo2: fix bugs in loader stub/mmu mappings exo2: start skeletoning bootconfig/global context types arch: fix makefile flags exo2: implement through master key derivation exo2: implement device master keygen exo2: more init through start of SetupSocSecurity exo2: implement pmc secure scratch management se: implement sticky bit validation libexosphere: fix building for arm32 libexo: fix makefile flags libexo: support building for arm64/arm sc7fw: skeleton binary sc7fw: skeleton a little more sc7fw: implement all non-dram functionality exo2: fix DivideUp error sc7fw: implement more dram code, fix reg library errors sc7fw: complete sc7fw impl. exo2: skeleton the rest of SetupSocSecurity exo2: implement fiq interrupt handler exo2: implement all exception handlers exo2: skeleton the entire smc api, implement the svc invoker exo2: implement rest of SetupSocSecurity exo2: correct slave security errors exo2: fix register definition exo2: minor fixes
113 lines
No EOL
4 KiB
C++
113 lines
No EOL
4 KiB
C++
/*
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* Copyright (c) 2018-2020 Atmosphère-NX
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <exosphere.hpp>
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#include "uart_registers.hpp"
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namespace ams::uart {
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namespace {
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constexpr inline const u16 UartRegisterOffsets[Port_Count] = {
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secmon::MemoryRegionPhysicalDeviceUartA.GetAddress() - secmon::MemoryRegionPhysicalDeviceUart.GetAddress(),
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secmon::MemoryRegionPhysicalDeviceUartB.GetAddress() - secmon::MemoryRegionPhysicalDeviceUart.GetAddress(),
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secmon::MemoryRegionPhysicalDeviceUartC.GetAddress() - secmon::MemoryRegionPhysicalDeviceUart.GetAddress(),
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};
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constinit uintptr_t g_register_address = secmon::MemoryRegionPhysicalDeviceUart.GetAddress();
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volatile UartRegisters *GetRegisters(Port port) {
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return reinterpret_cast<volatile UartRegisters *>(g_register_address + UartRegisterOffsets[port]);
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}
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void WaitSymbols(int baud, u32 num) {
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util::WaitMicroSeconds(util::DivideUp(1'000'000, baud) * num);
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}
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void WaitCycles(int baud, u32 num) {
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util::WaitMicroSeconds(util::DivideUp(1'000'000, 16 * baud) * num);
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}
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ALWAYS_INLINE void WaitFifoNotFull(volatile UartRegisters *uart) {
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while ((uart->lsr & UART_LSR_TX_FIFO_FULL) != 0) { /* ... */ }
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}
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ALWAYS_INLINE void WaitFifoNotEmpty(volatile UartRegisters *uart) {
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while ((uart->lsr & UART_LSR_RX_FIFO_EMPTY) != 0) { /* ... */ }
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}
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void WaitIdle(volatile UartRegisters *uart, u32 vendor_state) {
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if (vendor_state & UART_VENDOR_STATE_TX_IDLE) {
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while ((uart->lsr & UART_LSR_TMTY) == 0) { /* ... */ }
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}
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if (vendor_state & UART_VENDOR_STATE_RX_IDLE) {
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while ((uart->lsr & UART_LSR_RDR) != 0) { /* ... */ }
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}
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}
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}
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void SetRegisterAddress(uintptr_t address) {
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g_register_address = address;
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}
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void Initialize(Port port, int baud_rate, u32 flags) {
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/* Get the registers. */
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auto *uart = GetRegisters(port);
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/* Parse flags. */
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const bool inverted = (flags & Flag_Inverted) != 0;
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/* Calculate the baud rate divisor. */
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constexpr u32 UartClock = 408000000;
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const u32 divisor = (UartClock + (baud_rate * 16) / 2) / (baud_rate * 16);
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/* Disable DLAB and all interrupts. */
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uart->lcr = uart->lcr & ~UART_LCR_DLAB;
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uart->ier = 0;
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uart->mcr = 0;
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/* Setup the uart in FIFO mode. */
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uart->lcr = UART_LCR_DLAB | UART_LCR_WD_LENGTH_8;
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uart->dll = static_cast<u8>(divisor);
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uart->dlh = static_cast<u8>(divisor >> 8);
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uart->lcr = uart->lcr & ~UART_LCR_DLAB;
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reg::Read(std::addressof(uart->spr));
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/* Wait three symbols. */
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WaitSymbols(baud_rate, 3);
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/* Enable FIFO with default settings. */
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uart->fcr = UART_FCR_FCR_EN_FIFO;
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uart->irda_csr = inverted ? UART_IRDA_CSR_INVERT_TXD : 0;
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reg::Read(std::addressof(uart->spr));
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/* Wait three cycles. */
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WaitCycles(baud_rate, 3);
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/* Flush the FIFO. */
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WaitIdle(uart, UART_VENDOR_STATE_TX_IDLE);
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uart->fcr = uart->fcr | UART_FCR_RX_CLR | UART_FCR_TX_CLR;
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WaitCycles(baud_rate, 32);
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/* Wait for idle state. */
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WaitIdle(uart, UART_VENDOR_STATE_TX_IDLE | UART_VENDOR_STATE_RX_IDLE);
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/* Set scratch register to 0. */
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uart->spr = 0;
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}
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} |