mirror of
https://github.com/Atmosphere-NX/Atmosphere
synced 2024-11-15 01:26:34 +00:00
346 lines
12 KiB
C
346 lines
12 KiB
C
/*
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* Copyright (c) 2018-2020 Atmosphère-NX
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <stdbool.h>
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#include <stdint.h>
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#include <string.h>
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#include <vapours/ams_version.h>
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#include "car.h"
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#include "fuse.h"
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#include "pmc.h"
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#include "timers.h"
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/* Initialize the fuse driver */
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void fuse_init(void) {
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/* Make all fuse registers visible, disable the private key and disable programming. */
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clkrst_enable_fuse_regs(true);
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/* fuse_disable_private_key(); */
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fuse_disable_programming();
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}
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/* Disable access to the private key and set the TZ sticky bit. */
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void fuse_disable_private_key(void) {
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volatile tegra_fuse_t *fuse = fuse_get_regs();
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fuse->FUSE_PRIVATEKEYDISABLE = 0x10;
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}
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/* Disable all fuse programming. */
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void fuse_disable_programming(void) {
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volatile tegra_fuse_t *fuse = fuse_get_regs();
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fuse->FUSE_DISABLEREGPROGRAM = 1;
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}
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/* Enable power to the fuse hardware array. */
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void fuse_enable_power(void) {
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volatile tegra_pmc_t *pmc = pmc_get_regs();
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pmc->fuse_control &= ~(0x200); /* Clear PMC_FUSE_CTRL_PS18_LATCH_CLEAR. */
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mdelay(1);
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pmc->fuse_control |= 0x100; /* Set PMC_FUSE_CTRL_PS18_LATCH_SET. */
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mdelay(1);
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}
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/* Disable power to the fuse hardware array. */
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void fuse_disable_power(void) {
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volatile tegra_pmc_t *pmc = pmc_get_regs();
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pmc->fuse_control &= ~(0x100); /* Clear PMC_FUSE_CTRL_PS18_LATCH_SET. */
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mdelay(1);
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pmc->fuse_control |= 0x200; /* Set PMC_FUSE_CTRL_PS18_LATCH_CLEAR. */
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mdelay(1);
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}
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/* Wait for the fuse driver to go idle. */
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static void fuse_wait_idle(void) {
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volatile tegra_fuse_t *fuse = fuse_get_regs();
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uint32_t ctrl_val = 0;
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/* Wait for STATE_IDLE */
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while ((ctrl_val & (0xF0000)) != 0x40000) {
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ctrl_val = fuse->FUSE_FUSECTRL;
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}
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}
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/* Read a fuse from the hardware array. */
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uint32_t fuse_hw_read(uint32_t addr) {
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volatile tegra_fuse_t *fuse = fuse_get_regs();
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/* Wait for idle state. */
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fuse_wait_idle();
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/* Program the target address. */
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fuse->FUSE_FUSEADDR = addr;
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/* Enable read operation in control register. */
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uint32_t ctrl_val = fuse->FUSE_FUSECTRL;
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ctrl_val &= ~0x3;
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ctrl_val |= 0x1; /* Set READ command. */
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fuse->FUSE_FUSECTRL = ctrl_val;
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/* Wait for idle state. */
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fuse_wait_idle();
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return fuse->FUSE_FUSERDATA;
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}
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/* Write a fuse in the hardware array. */
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void fuse_hw_write(uint32_t value, uint32_t addr) {
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volatile tegra_fuse_t *fuse = fuse_get_regs();
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/* Wait for idle state. */
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fuse_wait_idle();
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/* Program the target address and value. */
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fuse->FUSE_FUSEADDR = addr;
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fuse->FUSE_FUSEWDATA = value;
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/* Enable write operation in control register. */
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uint32_t ctrl_val = fuse->FUSE_FUSECTRL;
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ctrl_val &= ~0x3;
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ctrl_val |= 0x2; /* Set WRITE command. */
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fuse->FUSE_FUSECTRL = ctrl_val;
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/* Wait for idle state. */
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fuse_wait_idle();
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}
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/* Sense the fuse hardware array into the fuse cache. */
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void fuse_hw_sense(void) {
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volatile tegra_fuse_t *fuse = fuse_get_regs();
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/* Wait for idle state. */
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fuse_wait_idle();
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/* Enable sense operation in control register */
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uint32_t ctrl_val = fuse->FUSE_FUSECTRL;
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ctrl_val &= ~0x3;
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ctrl_val |= 0x3; /* Set SENSE_CTRL command */
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fuse->FUSE_FUSECTRL = ctrl_val;
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/* Wait for idle state. */
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fuse_wait_idle();
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}
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/* Read the SKU info register. */
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uint32_t fuse_get_sku_info(void) {
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volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs();
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return fuse_chip->FUSE_SKU_INFO;
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}
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/* Read the bootrom patch version. */
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uint32_t fuse_get_bootrom_patch_version(void) {
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volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs();
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return fuse_chip->FUSE_SOC_SPEEDO_1_CALIB;
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}
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/* Read a spare bit register. */
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uint32_t fuse_get_spare_bit(uint32_t index) {
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uint32_t soc_type = fuse_get_soc_type();
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if (soc_type == 0) {
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if (index < 32) {
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volatile tegra_fuse_chip_erista_t *fuse_chip = fuse_chip_erista_get_regs();
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return fuse_chip->FUSE_SPARE_BIT[index];
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}
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} else if (soc_type == 1) {
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if (index < 30) {
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volatile tegra_fuse_chip_mariko_t *fuse_chip = fuse_chip_mariko_get_regs();
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return fuse_chip->FUSE_SPARE_BIT[index];
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}
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}
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return 0;
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}
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/* Read a reserved ODM register. */
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uint32_t fuse_get_reserved_odm(uint32_t index) {
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if (index < 8) {
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volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs();
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return fuse_chip->FUSE_RESERVED_ODM0[index];
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} else {
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uint32_t soc_type = fuse_get_soc_type();
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if (soc_type == 1) {
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volatile tegra_fuse_chip_mariko_t *fuse_chip = fuse_chip_mariko_get_regs();
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if (index < 22) {
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return fuse_chip->FUSE_RESERVED_ODM8[index - 8];
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} else if (index < 25) {
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return fuse_chip->FUSE_RESERVED_ODM22[index - 22];
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} else if (index < 26) {
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return fuse_chip->FUSE_RESERVED_ODM25;
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} else if (index < 29) {
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return fuse_chip->FUSE_RESERVED_ODM26[index - 26];
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} else if (index < 30) {
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return fuse_chip->FUSE_RESERVED_ODM29;
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}
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}
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}
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return 0;
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}
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/* Get the DramId. */
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uint32_t fuse_get_dram_id(void) {
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return ((fuse_get_reserved_odm(4) >> 3) & 0x1F);
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}
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/* Derive the DeviceId. */
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uint64_t fuse_get_device_id(void) {
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volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs();
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uint64_t device_id = 0;
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uint64_t y_coord = fuse_chip->FUSE_OPT_Y_COORDINATE & 0x1FF;
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uint64_t x_coord = fuse_chip->FUSE_OPT_X_COORDINATE & 0x1FF;
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uint64_t wafer_id = fuse_chip->FUSE_OPT_WAFER_ID & 0x3F;
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uint32_t lot_code = fuse_chip->FUSE_OPT_LOT_CODE_0;
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uint64_t fab_code = fuse_chip->FUSE_OPT_FAB_CODE & 0x3F;
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uint64_t derived_lot_code = 0;
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for (unsigned int i = 0; i < 5; i++) {
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derived_lot_code = (derived_lot_code * 0x24) + ((lot_code >> (24 - 6*i)) & 0x3F);
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}
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derived_lot_code &= 0x03FFFFFF;
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device_id |= y_coord << 0;
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device_id |= x_coord << 9;
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device_id |= wafer_id << 18;
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device_id |= derived_lot_code << 24;
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device_id |= fab_code << 50;
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return device_id;
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}
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/* Derive the HardwareType with firmware specific checks. */
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uint32_t fuse_get_hardware_type_with_firmware_check(uint32_t target_firmware) {
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uint32_t fuse_reserved_odm4 = fuse_get_reserved_odm(4);
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uint32_t hardware_type = (((fuse_reserved_odm4 >> 7) & 2) | ((fuse_reserved_odm4 >> 2) & 1));
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if (target_firmware < ATMOSPHERE_TARGET_FIRMWARE_4_0_0) {
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volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs();
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uint32_t fuse_spare_bit9 = (fuse_chip->FUSE_SPARE_BIT[9] & 1);
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switch (hardware_type) {
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case 0x00: return (fuse_spare_bit9 == 0) ? 0 : 3;
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case 0x01: return 0; /* HardwareType_Icosa */
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case 0x02: return 1; /* HardwareType_Copper */
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default: return 3; /* HardwareType_Undefined */
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}
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} else {
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hardware_type |= ((fuse_reserved_odm4 >> 14) & 0x3C);
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if (target_firmware < ATMOSPHERE_TARGET_FIRMWARE_7_0_0) {
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switch (hardware_type) {
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case 0x01: return 0; /* HardwareType_Icosa */
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case 0x02: return 1; /* HardwareType_Copper */
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case 0x04: return 3; /* HardwareType_Iowa */
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default: return 4; /* HardwareType_Undefined */
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}
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} else {
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if (target_firmware < ATMOSPHERE_TARGET_FIRMWARE_10_0_0) {
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switch (hardware_type) {
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case 0x01: return 0; /* HardwareType_Icosa */
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case 0x02: return 4; /* HardwareType_Calcio */
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case 0x04: return 3; /* HardwareType_Iowa */
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case 0x08: return 2; /* HardwareType_Hoag */
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default: return 0xF; /* HardwareType_Undefined */
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}
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} else {
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switch (hardware_type) {
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case 0x01: return 0; /* HardwareType_Icosa */
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case 0x02: return 4; /* HardwareType_Calcio */
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case 0x04: return 3; /* HardwareType_Iowa */
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case 0x08: return 2; /* HardwareType_Hoag */
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case 0x10: return 5; /* HardwareType_Five */
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default: return 0xF; /* HardwareType_Undefined */
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}
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}
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}
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}
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}
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/* Derive the HardwareType. */
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uint32_t fuse_get_hardware_type(void) {
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return fuse_get_hardware_type_with_firmware_check(ATMOSPHERE_TARGET_FIRMWARE_CURRENT);
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}
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/* Derive the HardwareState. */
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uint32_t fuse_get_hardware_state(void) {
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uint32_t fuse_reserved_odm4 = fuse_get_reserved_odm(4);
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uint32_t hardware_state = (((fuse_reserved_odm4 >> 7) & 4) | (fuse_reserved_odm4 & 3));
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switch (hardware_state) {
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case 0x03: return 0; /* HardwareState_Development */
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case 0x04: return 1; /* HardwareState_Production */
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default: return 2; /* HardwareState_Undefined */
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}
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}
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/* Derive the 16-byte HardwareInfo and copy to output buffer. */
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void fuse_get_hardware_info(void *dst) {
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volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs();
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uint32_t hw_info[0x4];
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uint32_t ops_reserved = fuse_chip->FUSE_OPT_OPS_RESERVED & 0x3F;
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uint32_t y_coord = fuse_chip->FUSE_OPT_Y_COORDINATE & 0x1FF;
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uint32_t x_coord = fuse_chip->FUSE_OPT_X_COORDINATE & 0x1FF;
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uint32_t wafer_id = fuse_chip->FUSE_OPT_WAFER_ID & 0x3F;
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uint32_t lot_code_0 = fuse_chip->FUSE_OPT_LOT_CODE_0;
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uint32_t lot_code_1 = fuse_chip->FUSE_OPT_LOT_CODE_1 & 0x0FFFFFFF;
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uint32_t fab_code = fuse_chip->FUSE_OPT_FAB_CODE & 0x3F;
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uint32_t vendor_code = fuse_chip->FUSE_OPT_VENDOR_CODE & 0xF;
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/* Hardware Info = OPS_RESERVED || Y_COORD || X_COORD || WAFER_ID || LOT_CODE || FAB_CODE || VENDOR_ID */
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hw_info[0] = (uint32_t)((lot_code_1 << 30) | (wafer_id << 24) | (x_coord << 15) | (y_coord << 6) | (ops_reserved));
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hw_info[1] = (uint32_t)((lot_code_0 << 26) | (lot_code_1 >> 2));
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hw_info[2] = (uint32_t)((fab_code << 26) | (lot_code_0 >> 6));
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hw_info[3] = (uint32_t)(vendor_code);
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memcpy(dst, hw_info, 0x10);
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}
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/* Check if have a new ODM fuse format. */
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bool fuse_is_new_format(void) {
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return ((fuse_get_reserved_odm(4) & 0x800) && (fuse_get_reserved_odm(0) == 0x8E61ECAE) && (fuse_get_reserved_odm(1) == 0xF2BA3BB2));
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}
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/* Get the DeviceUniqueKeyGeneration. */
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uint32_t fuse_get_device_unique_key_generation(void) {
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if (fuse_is_new_format()) {
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return (fuse_get_reserved_odm(2) & 0x1F);
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} else {
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return 0;
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}
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}
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/* Get the SocType from the HardwareType. */
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uint32_t fuse_get_soc_type(void) {
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switch (fuse_get_hardware_type()) {
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case 0:
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case 1:
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return 0; /* SocType_Erista */
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case 3:
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case 2:
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case 4:
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case 5:
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return 1; /* SocType_Mariko */
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default:
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return 0xF; /* SocType_Undefined */
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}
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}
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/* Get the Regulator type. */
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uint32_t fuse_get_regulator(void) {
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if (fuse_get_soc_type() == 1) {
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return ((fuse_get_reserved_odm(28) & 1) + 1); /* Regulator_Mariko_Max77812_A or Regulator_Mariko_Max77812_B */
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} else {
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return 0; /* Regulator_Erista_Max77621 */
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}
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}
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