mirror of
https://github.com/Atmosphere-NX/Atmosphere
synced 2025-01-22 22:56:11 +00:00
114cdc5aa4
- set/way cache ops create losses of coherency, do not broadcast and are only meant to be used on boot, period. Cache ops by VA are **the only way** to do data cache maintenance. Fix a bug where the L2 cache was evicted by each core. It shouldn't have. - Cleaning dcache to PoU and invalidating icache to PoU, by VA is sufficient for self-modifying code - Since we operate within a single cluster and don't do DMA, we almost always operate within the inner shareability domain (commit untested on real hw)
65 lines
2.1 KiB
C
65 lines
2.1 KiB
C
/*
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* Copyright (c) 2019 Atmosphère-NX
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <string.h>
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#include "core_ctx.h"
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#include "platform/memory_map_mmu_cfg.h"
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#include "sysreg.h"
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#include "utils.h"
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extern u8 __bss_start__[], __end__[], __temp_bss_start__[], __temp_bss_end__[];
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extern const u32 __vectors_start__[];
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static void initSysregs(void)
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{
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// Set VBAR
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SET_SYSREG(vbar_el2, (uintptr_t)__vectors_start__);
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// Set system to sane defaults, aarch64 for el1, mmu&caches initially disabled for EL1, etc.
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SET_SYSREG(hcr_el2, 0x80000000);
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SET_SYSREG(dacr32_el2, 0xFFFFFFFF); // unused
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SET_SYSREG(sctlr_el1, 0x00C50838);
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SET_SYSREG(mdcr_el2, 0x00000000);
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SET_SYSREG(mdscr_el1, 0x00000000);
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// Timer stuff
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SET_SYSREG(cntvoff_el2, 0x00000000);
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SET_SYSREG(cnthctl_el2, 0x00000003); // Don't trap anything for now; event streams disabled
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SET_SYSREG(cntkctl_el1, 0x00000003); // Don't trap anything for now; event streams disabled
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SET_SYSREG(cntp_ctl_el0, 0x00000000);
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SET_SYSREG(cntv_ctl_el0, 0x00000000);
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__dsb();
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__isb();
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}
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void initSystem(u32 coreId, bool isBootCore, u64 argument)
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{
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coreCtxInit(coreId, isBootCore, argument);
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initSysregs();
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if (isBootCore) {
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if (!currentCoreCtx->warmboot) {
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memset(__bss_start__, 0, __end__ - __bss_start__);
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}
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memset(__temp_bss_start__, 0, __temp_bss_end__ - __temp_bss_start__);
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}
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configureMemoryMapEnableMmu();
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configureMemoryMapEnableStage2();
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}
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