mirror of
https://github.com/Atmosphere-NX/Atmosphere
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143 lines
4.3 KiB
C++
143 lines
4.3 KiB
C++
/*
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* Copyright (c) 2018-2020 Atmosphère-NX
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#pragma once
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#include <vapours.hpp>
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#include <mesosphere/arch/arm64/kern_cpu_system_registers.hpp>
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namespace ams::kern::arm64::cpu {
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#if defined(ATMOSPHERE_CPU_ARM_CORTEX_A57) || defined(ATMOSPHERE_CPU_ARM_CORTEX_A53)
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constexpr inline size_t InstructionCacheLineSize = 0x40;
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constexpr inline size_t DataCacheLineSize = 0x40;
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#else
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#error "Unknown CPU for cache line sizes"
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#endif
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#if defined(ATMOSPHERE_BOARD_NINTENDO_SWITCH)
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static constexpr size_t NumCores = 4;
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#else
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#error "Unknown Board for cpu::NumCores"
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#endif
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/* Helpers for managing memory state. */
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ALWAYS_INLINE void DataSynchronizationBarrier() {
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__asm__ __volatile__("dsb sy" ::: "memory");
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}
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ALWAYS_INLINE void DataSynchronizationBarrierInnerShareable() {
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__asm__ __volatile__("dsb ish" ::: "memory");
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}
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ALWAYS_INLINE void DataMemoryBarrier() {
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__asm__ __volatile__("dmb sy" ::: "memory");
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}
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ALWAYS_INLINE void InstructionMemoryBarrier() {
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__asm__ __volatile__("isb" ::: "memory");
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}
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ALWAYS_INLINE void EnsureInstructionConsistency() {
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DataSynchronizationBarrier();
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InstructionMemoryBarrier();
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}
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ALWAYS_INLINE void InvalidateEntireInstructionCache() {
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__asm__ __volatile__("ic iallu" ::: "memory");
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EnsureInstructionConsistency();
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}
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/* Helper for address access. */
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ALWAYS_INLINE bool GetPhysicalAddressWritable(KPhysicalAddress *out, KVirtualAddress addr, bool privileged = false) {
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const uintptr_t va = GetInteger(addr);
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if (privileged) {
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__asm__ __volatile__("at s1e1w, %[va]" :: [va]"r"(va) : "memory");
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} else {
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__asm__ __volatile__("at s1e0w, %[va]" :: [va]"r"(va) : "memory");
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}
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InstructionMemoryBarrier();
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u64 par = GetParEl1();
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if (par & 0x1) {
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return false;
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}
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if (out) {
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*out = KPhysicalAddress((par & 0xFFFFFFFFF000ull) | (va & 0xFFFull));
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}
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return true;
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}
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ALWAYS_INLINE bool GetPhysicalAddressReadable(KPhysicalAddress *out, KVirtualAddress addr, bool privileged = false) {
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const uintptr_t va = GetInteger(addr);
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if (privileged) {
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__asm__ __volatile__("at s1e1r, %[va]" :: [va]"r"(va) : "memory");
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} else {
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__asm__ __volatile__("at s1e0r, %[va]" :: [va]"r"(va) : "memory");
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}
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InstructionMemoryBarrier();
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u64 par = GetParEl1();
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if (par & 0x1) {
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return false;
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}
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if (out) {
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*out = KPhysicalAddress((par & 0xFFFFFFFFF000ull) | (va & 0xFFFull));
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}
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return true;
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}
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/* Synchronization helpers. */
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NOINLINE void SynchronizeAllCores();
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/* Cache management helpers. */
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void ClearPageToZeroImpl(void *);
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void FlushEntireDataCacheShared();
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void FlushEntireDataCacheLocal();
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ALWAYS_INLINE void ClearPageToZero(void *page) {
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MESOSPHERE_ASSERT(util::IsAligned(reinterpret_cast<uintptr_t>(page), PageSize));
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MESOSPHERE_ASSERT(page != nullptr);
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ClearPageToZeroImpl(page);
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}
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ALWAYS_INLINE void InvalidateEntireTlb() {
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__asm__ __volatile__("tlbi vmalle1is" ::: "memory");
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EnsureInstructionConsistency();
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}
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ALWAYS_INLINE uintptr_t GetCoreLocalRegionAddress() {
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register uintptr_t x18 asm("x18");
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__asm__ __volatile__("" : [x18]"=r"(x18));
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return x18;
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}
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ALWAYS_INLINE void SetCoreLocalRegionAddress(uintptr_t value) {
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register uintptr_t x18 asm("x18") = value;
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__asm__ __volatile__("":: [x18]"r"(x18));
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SetTpidrEl1(value);
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}
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ALWAYS_INLINE void SwitchThreadLocalRegion(uintptr_t tlr) {
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cpu::SetTpidrRoEl0(tlr);
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}
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}
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