mirror of
https://github.com/Atmosphere-NX/Atmosphere
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515 lines
16 KiB
ArmAsm
515 lines
16 KiB
ArmAsm
/*
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* Copyright (c) 2018-2020 Atmosphère-NX
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/* For some reason GAS doesn't know about it, even with .cpu cortex-a57 */
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#define cpuactlr_el1 s3_1_c15_c2_0
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#define cpuectlr_el1 s3_1_c15_c2_1
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#define LOAD_IMMEDIATE_32(reg, val) \
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mov reg, #(((val) >> 0x00) & 0xFFFF); \
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movk reg, #(((val) >> 0x10) & 0xFFFF), lsl#16
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#define LOAD_IMMEDIATE_64(reg, val) \
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mov reg, #(((val) >> 0x00) & 0xFFFF); \
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movk reg, #(((val) >> 0x10) & 0xFFFF), lsl#16; \
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movk reg, #(((val) >> 0x20) & 0xFFFF), lsl#32; \
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movk reg, #(((val) >> 0x30) & 0xFFFF), lsl#48
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#define LOAD_FROM_LABEL(reg, label) \
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adr reg, label; \
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ldr reg, [reg]
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.section .crt0.text.start, "ax", %progbits
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.global _start
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_start:
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b _ZN3ams4kern4init10StartCore0Emm
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__metadata_begin:
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.ascii "MSS0" /* Magic */
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__metadata_ini_offset:
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.quad 0 /* INI1 base address. */
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__metadata_kernelldr_offset:
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.quad 0 /* Kernel Loader base address. */
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__metadata_target_firmware:
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.word 0xCCCCCCCC /* Target firmware. */
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__metadata_kernel_layout:
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.word _start - _start /* rx_offset */
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.word __rodata_start - _start /* rx_end_offset */
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.word __rodata_start - _start /* ro_offset */
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.word __data_start - _start /* ro_end_offset */
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.word __data_start - _start /* rw_offset */
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.word __bss_start__ - _start /* rw_end_offset */
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.word __bss_start__ - _start /* bss_offset */
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.word __bss_end__ - _start /* bss_end_offset */
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.word __end__ - _start /* ini_load_offset */
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.word _DYNAMIC - _start /* dynamic_offset */
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.word __init_array_start - _start /* init_array_offset */
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.word __init_array_end - _start /* init_array_end_offset */
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.if (. - __metadata_begin) != 0x48
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.error "Incorrect Mesosphere Metadata"
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.endif
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#ifdef ATMOSPHERE_BOARD_NINTENDO_NX
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.global _ZN3ams4kern17GetTargetFirmwareEv
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.type _ZN3ams4kern17GetTargetFirmwareEv, %function
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_ZN3ams4kern17GetTargetFirmwareEv:
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adr x0, __metadata_target_firmware
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ldr w0, [x0]
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ret
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#endif
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/* ams::kern::init::StartCore0(uintptr_t, uintptr_t) */
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.section .crt0.text._ZN3ams4kern4init10StartCore0Emm, "ax", %progbits
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.global _ZN3ams4kern4init10StartCore0Emm
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.type _ZN3ams4kern4init10StartCore0Emm, %function
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_ZN3ams4kern4init10StartCore0Emm:
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/* Mask all interrupts. */
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msr daifset, #0xF
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/* Save arguments for later use. */
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mov x19, x0
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mov x20, x1
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/* Check our current EL. We want to be executing out of EL1. */
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/* If we're in EL2, we'll need to deprivilege ourselves. */
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mrs x1, currentel
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cmp x1, #0x4
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b.eq core0_el1
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cmp x1, #0x8
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b.eq core0_el2
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core0_el3:
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b core0_el3
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core0_el2:
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bl _ZN3ams4kern4init16JumpFromEL2ToEL1Ev
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core0_el1:
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bl _ZN3ams4kern4init19DisableMmuAndCachesEv
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#ifdef ATMOSPHERE_BOARD_NINTENDO_NX
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/* Get the target firmware from exosphere. */
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LOAD_IMMEDIATE_32(w0, 0xC3000004)
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mov w1, #65000
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smc #1
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cmp x0, #0
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0:
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b.ne 0b
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/* Store the target firmware. */
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adr x0, __metadata_target_firmware
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str w1, [x0]
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#endif
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/* We want to invoke kernel loader. */
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adr x0, _start
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adr x1, __metadata_kernel_layout
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LOAD_FROM_LABEL(x2, __metadata_ini_offset)
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add x2, x0, x2
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LOAD_FROM_LABEL(x3, __metadata_kernelldr_offset)
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add x3, x0, x3
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/* Invoke kernel loader. */
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blr x3
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/* At this point kernelldr has been invoked, and we are relocated at a random virtual address. */
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/* Next thing to do is to set up our memory management and slabheaps -- all the other core initialization. */
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/* Call ams::kern::init::InitializeCore(uintptr_t, uintptr_t) */
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mov x1, x0 /* Kernelldr returns a KInitialPageAllocator state for the kernel to re-use. */
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mov x0, xzr /* Official kernel always passes zero, when this is non-zero the address is mapped. */
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bl _ZN3ams4kern4init14InitializeCoreEmm
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/* Get the init arguments for core 0. */
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mov x0, xzr
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bl _ZN3ams4kern4init23GetInitArgumentsAddressEi
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bl _ZN3ams4kern4init16InvokeEntrypointEPKNS1_14KInitArgumentsE
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/* ams::kern::init::StartOtherCore(const ams::kern::init::KInitArguments *) */
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.section .crt0.text._ZN3ams4kern4init14StartOtherCoreEPKNS1_14KInitArgumentsE, "ax", %progbits
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.global _ZN3ams4kern4init14StartOtherCoreEPKNS1_14KInitArgumentsE
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.type _ZN3ams4kern4init14StartOtherCoreEPKNS1_14KInitArgumentsE, %function
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_ZN3ams4kern4init14StartOtherCoreEPKNS1_14KInitArgumentsE:
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/* Preserve the KInitArguments pointer in a register. */
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mov x20, x0
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/* Check our current EL. We want to be executing out of EL1. */
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/* If we're in EL2, we'll need to deprivilege ourselves. */
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mrs x1, currentel
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cmp x1, #0x4
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b.eq othercore_el1
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cmp x1, #0x8
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b.eq othercore_el2
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othercore_el3:
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b othercore_el3
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othercore_el2:
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bl _ZN3ams4kern4init16JumpFromEL2ToEL1Ev
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othercore_el1:
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bl _ZN3ams4kern4init19DisableMmuAndCachesEv
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/* Setup system registers using values from our KInitArguments. */
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ldr x1, [x20, #0x00]
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msr ttbr0_el1, x1
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ldr x1, [x20, #0x08]
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msr ttbr1_el1, x1
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ldr x1, [x20, #0x10]
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msr tcr_el1, x1
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ldr x1, [x20, #0x18]
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msr mair_el1, x1
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/* Perform cpu-specific setup. */
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mrs x1, midr_el1
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ubfx x2, x1, #0x18, #0x8 /* Extract implementer bits. */
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cmp x2, #0x41 /* Implementer::ArmLimited */
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b.ne othercore_cpu_specific_setup_end
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ubfx x2, x1, #0x4, #0xC /* Extract primary part number. */
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cmp x2, #0xD07 /* PrimaryPartNumber::CortexA57 */
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b.eq othercore_cpu_specific_setup_cortex_a57
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cmp x2, #0xD03 /* PrimaryPartNumber::CortexA53 */
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b.eq othercore_cpu_specific_setup_cortex_a53
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b othercore_cpu_specific_setup_end
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othercore_cpu_specific_setup_cortex_a57:
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othercore_cpu_specific_setup_cortex_a53:
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ldr x1, [x20, #0x20]
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msr cpuactlr_el1, x1
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ldr x1, [x20, #0x28]
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msr cpuectlr_el1, x1
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othercore_cpu_specific_setup_end:
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/* Ensure instruction consistency. */
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dsb sy
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isb
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/* Set sctlr_el1 and ensure instruction consistency. */
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ldr x1, [x20, #0x30]
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msr sctlr_el1, x1
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dsb sy
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isb
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/* Jump to the virtual address equivalent to ams::kern::init::InvokeEntrypoint */
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ldr x1, [x20, #0x50]
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adr x2, _ZN3ams4kern4init14StartOtherCoreEPKNS1_14KInitArgumentsE
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sub x1, x1, x2
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adr x2, _ZN3ams4kern4init16InvokeEntrypointEPKNS1_14KInitArgumentsE
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add x1, x1, x2
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mov x0, x20
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br x1
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/* ams::kern::init::InvokeEntrypoint(const ams::kern::init::KInitArguments *) */
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.section .crt0.text._ZN3ams4kern4init16InvokeEntrypointEPKNS1_14KInitArgumentsE, "ax", %progbits
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.global _ZN3ams4kern4init16InvokeEntrypointEPKNS1_14KInitArgumentsE
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.type _ZN3ams4kern4init16InvokeEntrypointEPKNS1_14KInitArgumentsE, %function
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_ZN3ams4kern4init16InvokeEntrypointEPKNS1_14KInitArgumentsE:
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/* Preserve the KInitArguments pointer in a register. */
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mov x20, x0
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/* Clear CPACR_EL1. This will prevent classes of traps (SVE, etc). */
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msr cpacr_el1, xzr
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isb
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/* Setup the stack pointer. */
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ldr x1, [x20, #0x38]
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mov sp, x1
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/* Ensure that system debug registers are setup. */
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bl _ZN3ams4kern4init24InitializeDebugRegistersEv
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/* Ensure that the exception vectors are setup. */
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bl _ZN3ams4kern4init26InitializeExceptionVectorsEv
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/* Setup the exception stack in tpidr_el1. */
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ldr x1, [x20, #0x58]
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msr tpidr_el1, x1
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/* Jump to the entrypoint. */
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ldr x1, [x20, #0x40]
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ldr x0, [x20, #0x48]
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br x1
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/* ams::kern::init::JumpFromEL2ToEL1() */
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.section .crt0.text._ZN3ams4kern4init16JumpFromEL2ToEL1Ev, "ax", %progbits
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.global _ZN3ams4kern4init16JumpFromEL2ToEL1Ev
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.type _ZN3ams4kern4init16JumpFromEL2ToEL1Ev, %function
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_ZN3ams4kern4init16JumpFromEL2ToEL1Ev:
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/* We're going to want to ERET to our caller. */
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msr elr_el2, x30
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/* Flush the entire data cache and invalidate the entire TLB. */
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bl _ZN3ams4kern4arch5arm643cpu32FlushEntireDataCacheWithoutStackEv
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/* Setup system registers for deprivileging. */
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/* Check if we're on cortex A57 or A53. If we are, set ACTLR_EL2. */
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mrs x1, midr_el1
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/* Is the manufacturer ID 'A' (ARM)? */
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ubfx x2, x1, #0x18, #8
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cmp x2, #0x41
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b.ne 2f
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/* Is the board ID Cortex-A57? */
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ubfx x2, x1, #4, #0xC
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mov x3, #0xD07
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cmp x2, x3
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b.eq 1f
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/* Is the board ID Cortex-A53? */
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mov x3, #0xD03
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cmp x2, x3
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b.ne 2f
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1:
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/* ACTLR_EL2: */
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/* - CPUACTLR access control = 1 */
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/* - CPUECTLR access control = 1 */
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/* - L2CTLR access control = 1 */
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/* - L2ECTLR access control = 1 */
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/* - L2ACTLR access control = 1 */
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mov x0, #0x73
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msr actlr_el2, x0
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2:
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/* HCR_EL2: */
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/* - RW = 1 (el1 is aarch64) */
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mov x0, #0x80000000
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msr hcr_el2, x0
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/* SCTLR_EL1: */
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/* - EOS = 1 */
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/* - EIS = 1 */
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/* - SPAN = 1 */
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LOAD_IMMEDIATE_32(x0, 0x00C00800)
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msr sctlr_el1, x0
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/* DACR32_EL2: */
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/* - Manager access for all D<n> */
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mov x0, #0xFFFFFFFF
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msr dacr32_el2, x0
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/* Set VPIDR_EL2 = MIDR_EL1 */
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mrs x0, midr_el1
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msr vpidr_el2, x0
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/* SET VMPIDR_EL2 = MPIDR_EL1 */
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mrs x0, mpidr_el1
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msr vmpidr_el2, x0
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/* SPSR_EL2: */
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/* - EL1h */
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/* - IRQ masked */
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/* - FIQ masked */
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mov x0, #0xC5
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msr spsr_el2, x0
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eret
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/* ams::kern::init::DisableMmuAndCaches() */
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.section .crt0.text._ZN3ams4kern4init19DisableMmuAndCachesEv, "ax", %progbits
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.global _ZN3ams4kern4init19DisableMmuAndCachesEv
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.type _ZN3ams4kern4init19DisableMmuAndCachesEv, %function
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_ZN3ams4kern4init19DisableMmuAndCachesEv:
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/* The stack isn't set up, so we'll need to trash a register. */
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mov x22, x30
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/* Flush the entire data cache and invalidate the entire TLB. */
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bl _ZN3ams4kern4arch5arm643cpu32FlushEntireDataCacheWithoutStackEv
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/* Invalidate the instruction cache, and ensure instruction consistency. */
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ic ialluis
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dsb sy
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isb
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/* Set SCTLR_EL1 to disable the caches and mmu. */
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/* SCTLR_EL1: */
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/* - M = 0 */
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/* - C = 0 */
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/* - I = 0 */
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mrs x0, sctlr_el1
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LOAD_IMMEDIATE_64(x1, ~0x1005)
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and x0, x0, x1
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msr sctlr_el1, x0
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mov x30, x22
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ret
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/* ams::kern::arch::arm64::cpu::FlushEntireDataCacheWithoutStack() */
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.section .crt0.text._ZN3ams4kern4arch5arm643cpu32FlushEntireDataCacheWithoutStackEv, "ax", %progbits
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.global _ZN3ams4kern4arch5arm643cpu32FlushEntireDataCacheWithoutStackEv
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.type _ZN3ams4kern4arch5arm643cpu32FlushEntireDataCacheWithoutStackEv, %function
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_ZN3ams4kern4arch5arm643cpu32FlushEntireDataCacheWithoutStackEv:
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/* The stack isn't set up, so we'll need to trash a register. */
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mov x23, x30
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/* Ensure that the cache is coherent. */
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bl _ZN3ams4kern4arch5arm643cpu37FlushEntireDataCacheLocalWithoutStackEv
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dsb sy
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bl _ZN3ams4kern4arch5arm643cpu38FlushEntireDataCacheSharedWithoutStackEv
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dsb sy
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bl _ZN3ams4kern4arch5arm643cpu37FlushEntireDataCacheLocalWithoutStackEv
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dsb sy
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/* Invalidate the entire TLB, and ensure instruction consistency. */
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tlbi vmalle1is
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dsb sy
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isb
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mov x30, x23
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ret
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/* ams::kern::arch::arm64::cpu::FlushEntireDataCacheLocalWithoutStack() */
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.section .crt0.text._ZN3ams4kern4arch5arm643cpu37FlushEntireDataCacheLocalWithoutStackEv, "ax", %progbits
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.global _ZN3ams4kern4arch5arm643cpu37FlushEntireDataCacheLocalWithoutStackEv
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.type _ZN3ams4kern4arch5arm643cpu37FlushEntireDataCacheLocalWithoutStackEv, %function
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_ZN3ams4kern4arch5arm643cpu37FlushEntireDataCacheLocalWithoutStackEv:
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/* The stack isn't set up, so we'll need to trash a register. */
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mov x24, x30
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/* CacheLineIdAccessor clidr_el1; */
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mrs x10, clidr_el1
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/* const int levels_of_unification = clidr_el1.GetLevelsOfUnification(); */
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ubfx x10, x10, #0x15, 3
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/* int level = levels_of_unification - 1 */
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sub w9, w10, #1
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/* while (level >= 0) { */
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begin_flush_cache_local_loop:
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cmn w9, #1
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b.eq done_flush_cache_local_loop
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/* FlushEntireDataCacheImplWithoutStack(level); */
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mov w0, w9
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bl _ZN3ams4kern4arch5arm643cpu36FlushEntireDataCacheImplWithoutStackEv
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/* level--; */
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sub w9, w9, #1
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/* } */
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b begin_flush_cache_local_loop
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done_flush_cache_local_loop:
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mov x30, x24
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ret
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/* ams::kern::arch::arm64::cpu::FlushEntireDataCacheSharedWithoutStack() */
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.section .crt0.text._ZN3ams4kern4arch5arm643cpu38FlushEntireDataCacheSharedWithoutStackEv, "ax", %progbits
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.global _ZN3ams4kern4arch5arm643cpu38FlushEntireDataCacheSharedWithoutStackEv
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.type _ZN3ams4kern4arch5arm643cpu38FlushEntireDataCacheSharedWithoutStackEv, %function
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_ZN3ams4kern4arch5arm643cpu38FlushEntireDataCacheSharedWithoutStackEv:
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/* The stack isn't set up, so we'll need to trash a register. */
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mov x24, x30
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/* CacheLineIdAccessor clidr_el1; */
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mrs x10, clidr_el1
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/* const int levels_of_coherency = clidr_el1.GetLevelsOfCoherency(); */
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ubfx x9, x10, #0x18, 3
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/* const int levels_of_unification = clidr_el1.GetLevelsOfUnification(); */
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ubfx x10, x10, #0x15, 3
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/* int level = levels_of_coherency */
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/* while (level >= levels_of_unification) { */
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begin_flush_cache_shared_loop:
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cmp w10, w9
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b.gt done_flush_cache_shared_loop
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/* FlushEntireDataCacheImplWithoutStack(level); */
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mov w0, w9
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bl _ZN3ams4kern4arch5arm643cpu36FlushEntireDataCacheImplWithoutStackEv
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/* level--; */
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sub w9, w9, #1
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/* } */
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b begin_flush_cache_shared_loop
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done_flush_cache_shared_loop:
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mov x30, x24
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ret
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/* ams::kern::arch::arm64::cpu::FlushEntireDataCacheImplWithoutStack() */
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.section .crt0.text._ZN3ams4kern4arch5arm643cpu36FlushEntireDataCacheImplWithoutStackEv, "ax", %progbits
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.global _ZN3ams4kern4arch5arm643cpu36FlushEntireDataCacheImplWithoutStackEv
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.type _ZN3ams4kern4arch5arm643cpu36FlushEntireDataCacheImplWithoutStackEv, %function
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_ZN3ams4kern4arch5arm643cpu36FlushEntireDataCacheImplWithoutStackEv:
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/* const u64 level_sel_value = static_cast<u64>(level << 1); */
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lsl w6, w0, #1
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sxtw x6, w6
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/* cpu::SetCsselrEl1(level_sel_value); */
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msr csselr_el1, x6
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/* cpu::InstructionMemoryBarrier(); */
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isb
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/* CacheSizeIdAccessor ccsidr_el1; */
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mrs x3, ccsidr_el1
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/* const int num_ways = ccsidr_el1.GetAssociativity(); */
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ubfx x7, x3, #3, #0xA
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mov w8, w7
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/* const int line_size = ccsidr_el1.GetLineSize(); */
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and x4, x3, #7
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/* const u64 way_shift = static_cast<u64>(__builtin_clz(num_ways)); */
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clz w7, w7
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/* const u64 set_shift = static_cast<u64>(line_size + 4); */
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add w4, w4, #4
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/* const int num_sets = ccsidr_el1.GetNumberOfSets(); */
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ubfx w3, w3, #0xD, #0xF
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/* int way = 0; */
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mov x5, #0
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/* while (way <= num_ways) { */
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begin_flush_cache_impl_way_loop:
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cmp w8, w5
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b.lt done_flush_cache_impl_way_loop
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/* int set = 0; */
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mov x0, #0
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/* while (set <= num_sets) { */
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begin_flush_cache_impl_set_loop:
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cmp w3, w0
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b.lt done_flush_cache_impl_set_loop
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/* const u64 cisw_value = (static_cast<u64>(way) << way_shift) | (static_cast<u64>(set) << set_shift) | level_sel_value; */
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lsl x2, x5, x7
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lsl x1, x0, x4
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orr x1, x1, x2
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orr x1, x1, x6
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/* __asm__ __volatile__("dc cisw, %0" :: "r"(cisw_value) : "memory"); */
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dc cisw, x1
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/* set++; */
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add x0, x0, #1
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/* } */
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b begin_flush_cache_impl_set_loop
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done_flush_cache_impl_set_loop:
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/* way++; */
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add x5, x5, 1
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/* } */
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b begin_flush_cache_impl_way_loop
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done_flush_cache_impl_way_loop:
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ret
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