mirror of
https://github.com/Atmosphere-NX/Atmosphere
synced 2024-09-21 07:38:59 +00:00
206c10f333
Use 204 MHz as host clock in SDR104 mode instead of 136 MHz. Due to this, also change the frequency init divider so the initialization frequency is below 400 kHz. This makes the clocks for SDMMC1 in all modes to match the TRM table. Make it clear in the code that HS200/HS400 modes in fact use PLLP_OUT0 and not PLLC4_OUT2_LJ like the comment suggest. In fact selecting the PLLC4_OUT2_LJ as clock source results in freeze after switching to HS200/HS400 mode. This is most likely related to the PLLC4 not being enabled, but it should be checked later. Set the HS200/HS400 divider to 3, as this is what the code really did set prior to this change - so this commit does not change that. Configure Legacy 12 MHz clock to run at 12 MHz using the SW default configuration (as per TRM) for the SDMMC legacy timer. Introduce initial version of sdmmc_host_clock_delay() in order to use it in places where the wait is host clock dependent. The way it is implemented now does not change the sleep that was used instead.
299 lines
12 KiB
C
299 lines
12 KiB
C
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#ifndef __FUSEE_CLOCK_H__
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#define __FUSEE_CLOCK_H__
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#include "utils.h"
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/**
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* Struct definition yanked from u-boot.
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*/
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/* PLL registers - there are several PLLs in the clock controller */
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struct clk_pll {
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uint32_t pll_base; /* the control register */
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/* pll_out[0] is output A control, pll_out[1] is output B control */
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uint32_t pll_out[2];
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uint32_t pll_misc; /* other misc things */
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};
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/* PLL registers - there are several PLLs in the clock controller */
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struct clk_pll_simple {
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uint32_t pll_base; /* the control register */
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uint32_t pll_misc; /* other misc things */
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};
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struct clk_pllm {
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uint32_t pllm_base; /* the control register */
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uint32_t pllm_out; /* output control */
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uint32_t pllm_misc1; /* misc1 */
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uint32_t pllm_misc2; /* misc2 */
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};
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/*
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* Most PLLs use the clk_pll structure, but some have a simpler two-member
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* structure for which we use clk_pll_simple. The reason for this non-
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* othogonal setup is not stated.
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*/
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enum {
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TEGRA_CLK_PLLS = 6, /* Number of normal PLLs */
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TEGRA_CLK_SIMPLE_PLLS = 3, /* Number of simple PLLs */
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TEGRA_CLK_SOURCES = 64, /* Number of ppl clock sources L/H/U */
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TEGRA_CLK_SOURCES_VW = 32, /* Number of ppl clock sources V/W */
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TEGRA_CLK_SOURCES_X = 32, /* Number of ppl clock sources X */
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TEGRA_CLK_SOURCES_Y = 18, /* Number of ppl clock sources Y */
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};
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/*
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* Masks for TEGRA_CLK_SOURCE elements.
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*/
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enum {
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CLK_SOURCE_MASK = (0b111 << 29),
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CLK_SOURCE_SDMMC1_PLLP_OUT0 = (0b000 << 29), /* Fixed 408 MHz */
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CLK_SOURCE_SDMMC4_PLLP_OUT0 = (0b000 << 29), /* Fixed 408 MHz */
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CLK_SOURCE_SDMMC4_PLLC4_OUT2_LJ = (0b001 << 29), /* 199.68 MHz */
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CLK_SOURCE_SDMMC_LEGACY_PLLP_OUT0 = (0b100 << 29), /* Fixed 408 MHz */
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CLK_DIVIDER_MASK = (0xff << 0),
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CLK_DIVIDER_UNITY = (0x00 << 0),
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};
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/**
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* Reset bits for relevant registers.
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*/
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enum {
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CAR_CONTROL_SDMMC1 = (1 << 14),
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CAR_CONTROL_SDMMC4 = (1 << 15),
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CAR_CONTROL_SDMMC_LEGACY = (1 << 1),
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};
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enum {
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CLK_SOURCE_SDMMC1 = 20,
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CLK_SOURCE_SDMMC4 = 25, /* 0x54 into the the main source block */
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CLK_SOURCE_SDMMC_LEGACY = 0, /* first in block Y */
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};
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/* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */
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struct tegra_car {
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uint32_t rst_src; /* _RST_SOURCE_0,0x00 */
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uint32_t rst_dev_l;
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uint32_t rst_dev_h;
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uint32_t rst_dev_u;
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uint32_t clk_out_dev_l;
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uint32_t clk_out_dev_h;
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uint32_t clk_out_dev_u;
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uint32_t reserved0; /* reserved_0, 0x1C */
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uint32_t cclk_brst_pol; /* _CCLK_BURST_POLICY_0, 0x20 */
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uint32_t super_cclk_div; /* _SUPER_CCLK_DIVIDER_0,0x24 */
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uint32_t sclk_brst_pol; /* _SCLK_BURST_POLICY_0, 0x28 */
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uint32_t super_sclk_div; /* _SUPER_SCLK_DIVIDER_0,0x2C */
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uint32_t clk_sys_rate; /* _CLK_SYSTEM_RATE_0, 0x30 */
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uint32_t prog_dly_clk; /* _PROG_DLY_CLK_0, 0x34 */
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uint32_t aud_sync_clk_rate; /* _AUDIO_SYNC_CLK_RATE_0,0x38 */
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uint32_t reserved1; /* reserved_1, 0x3C */
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uint32_t cop_clk_skip_plcy; /* _COP_CLK_SKIP_POLICY_0,0x40 */
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uint32_t clk_mask_arm; /* _CLK_MASK_ARM_0, 0x44 */
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uint32_t misc_clk_enb; /* _MISC_CLK_ENB_0, 0x48 */
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uint32_t clk_cpu_cmplx; /* _CLK_CPU_CMPLX_0, 0x4C */
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uint32_t osc_ctrl; /* _OSC_CTRL_0, 0x50 */
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uint32_t pll_lfsr; /* _PLL_LFSR_0, 0x54 */
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uint32_t osc_freq_det; /* _OSC_FREQ_DET_0, 0x58 */
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uint32_t osc_freq_det_stat; /* _OSC_FREQ_DET_STATUS_0,0x5C */
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uint32_t reserved2[8]; /* reserved_2[8], 0x60-7C */
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struct clk_pll pll[TEGRA_CLK_PLLS]; /* PLLs from 0x80 to 0xdc */
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/* PLLs from 0xe0 to 0xf4 */
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struct clk_pll_simple pll_simple[TEGRA_CLK_SIMPLE_PLLS];
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uint32_t reserved10; /* _reserved_10, 0xF8 */
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uint32_t reserved11; /* _reserved_11, 0xFC */
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uint32_t clk_src[TEGRA_CLK_SOURCES]; /*_I2S1_0... 0x100-1fc */
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uint32_t reserved20[32]; /* _reserved_20, 0x200-27c */
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uint32_t clk_out_enb_x; /* _CLK_OUT_ENB_X_0, 0x280 */
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uint32_t clk_enb_x_set; /* _CLK_ENB_X_SET_0, 0x284 */
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uint32_t clk_enb_x_clr; /* _CLK_ENB_X_CLR_0, 0x288 */
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uint32_t rst_devices_x; /* _RST_DEVICES_X_0, 0x28c */
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uint32_t rst_dev_x_set; /* _RST_DEV_X_SET_0, 0x290 */
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uint32_t rst_dev_x_clr; /* _RST_DEV_X_CLR_0, 0x294 */
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uint32_t clk_out_enb_y; /* _CLK_OUT_ENB_Y_0, 0x298 */
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uint32_t clk_enb_y_set; /* _CLK_ENB_Y_SET_0, 0x29c */
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uint32_t clk_enb_y_clr; /* _CLK_ENB_Y_CLR_0, 0x2a0 */
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uint32_t rst_devices_y; /* _RST_DEVICES_Y_0, 0x2a4 */
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uint32_t rst_dev_y_set; /* _RST_DEV_Y_SET_0, 0x2a8 */
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uint32_t rst_dev_y_clr; /* _RST_DEV_Y_CLR_0, 0x2ac */
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uint32_t reserved21[17]; /* _reserved_21, 0x2b0-2f0 */
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uint32_t dfll_base; /* _DFLL_BASE_0, 0x2f4 */
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uint32_t reserved22[2]; /* _reserved_22, 0x2f8-2fc */
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/* _RST_DEV_L/H/U_SET_0 0x300 ~ 0x314 */
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uint32_t rst_dev_l_set;
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uint32_t rst_dev_l_clr;
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uint32_t rst_dev_h_set;
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uint32_t rst_dev_h_clr;
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uint32_t rst_dev_u_set;
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uint32_t rst_dev_u_clr;
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uint32_t reserved30[2]; /* _reserved_30, 0x318, 0x31c */
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/* _CLK_ENB_L/H/U_CLR_0 0x320 ~ 0x334 */
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uint32_t clk_enb_l_set;
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uint32_t clk_enb_l_clr;
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uint32_t clk_enb_h_set;
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uint32_t clk_enb_h_clr;
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uint32_t clk_enb_u_set;
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uint32_t clk_enb_u_clr;
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uint32_t reserved31[2]; /* _reserved_31, 0x338, 0x33c */
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uint32_t cpu_cmplx_set; /* _RST_CPU_CMPLX_SET_0, 0x340 */
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uint32_t cpu_cmplx_clr; /* _RST_CPU_CMPLX_CLR_0, 0x344 */
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/* Additional (T30) registers */
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uint32_t clk_cpu_cmplx_set; /* _CLK_CPU_CMPLX_SET_0, 0x348 */
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uint32_t clk_cpu_cmplx_clr; /* _CLK_CPU_CMPLX_SET_0, 0x34c */
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uint32_t reserved32[2]; /* _reserved_32, 0x350,0x354 */
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uint32_t rst_dev_v; /* _RST_DEVICES_V/W_0 */
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uint32_t rst_dev_w; /* _RST_DEVICES_V/W_0 */
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uint32_t clk_out_enb_v; /* _CLK_OUT_ENB_V/W_0 */
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uint32_t clk_out_enb_w; /* _CLK_OUT_ENB_V/W_0 */
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uint32_t cclkg_brst_pol; /* _CCLKG_BURST_POLICY_0, 0x368 */
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uint32_t super_cclkg_div; /* _SUPER_CCLKG_DIVIDER_0, 0x36C */
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uint32_t cclklp_brst_pol; /* _CCLKLP_BURST_POLICY_0, 0x370 */
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uint32_t super_cclkp_div; /* _SUPER_CCLKLP_DIVIDER_0, 0x374 */
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uint32_t clk_cpug_cmplx; /* _CLK_CPUG_CMPLX_0, 0x378 */
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uint32_t clk_cpulp_cmplx; /* _CLK_CPULP_CMPLX_0, 0x37C */
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uint32_t cpu_softrst_ctrl; /* _CPU_SOFTRST_CTRL_0, 0x380 */
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uint32_t cpu_softrst_ctrl1; /* _CPU_SOFTRST_CTRL1_0, 0x384 */
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uint32_t cpu_softrst_ctrl2; /* _CPU_SOFTRST_CTRL2_0, 0x388 */
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uint32_t reserved33[9]; /* _reserved_33, 0x38c-3ac */
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uint32_t clk_src_v; /* 0x3B0-0x42C */
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uint32_t clk_src_w; /* 0x3B0-0x42C */
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/* _RST_DEV_V/W_SET_0 0x430 ~ 0x43c */
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uint32_t rst_dev_v_set;
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uint32_t rst_dev_v_clr;
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uint32_t rst_dev_w_set;
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uint32_t rst_dev_w_clr;
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/* _CLK_ENB_V/W_CLR_0 0x440 ~ 0x44c */
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uint32_t rst_clk_v_set;
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uint32_t rst_clk_v_clr;
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uint32_t rst_clk_w_set;
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uint32_t rst_clk_w_clr;
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/* Additional (T114+) registers */
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uint32_t rst_cpug_cmplx_set; /* _RST_CPUG_CMPLX_SET_0, 0x450 */
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uint32_t rst_cpug_cmplx_clr; /* _RST_CPUG_CMPLX_CLR_0, 0x454 */
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uint32_t rst_cpulp_cmplx_set; /* _RST_CPULP_CMPLX_SET_0, 0x458 */
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uint32_t rst_cpulp_cmplx_clr; /* _RST_CPULP_CMPLX_CLR_0, 0x45C */
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uint32_t clk_cpug_cmplx_set; /* _CLK_CPUG_CMPLX_SET_0, 0x460 */
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uint32_t clk_cpug_cmplx_clr; /* _CLK_CPUG_CMPLX_CLR_0, 0x464 */
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uint32_t clk_cpulp_cmplx_set; /* _CLK_CPULP_CMPLX_SET_0, 0x468 */
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uint32_t clk_cpulp_cmplx_clr; /* _CLK_CPULP_CMPLX_CLR_0, 0x46C */
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uint32_t cpu_cmplx_status; /* _CPU_CMPLX_STATUS_0, 0x470 */
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uint32_t reserved40[1]; /* _reserved_40, 0x474 */
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uint32_t intstatus; /* __INTSTATUS_0, 0x478 */
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uint32_t intmask; /* __INTMASK_0, 0x47C */
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uint32_t utmip_pll_cfg0; /* _UTMIP_PLL_CFG0_0, 0x480 */
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uint32_t utmip_pll_cfg1; /* _UTMIP_PLL_CFG1_0, 0x484 */
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uint32_t utmip_pll_cfg2; /* _UTMIP_PLL_CFG2_0, 0x488 */
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uint32_t plle_aux; /* _PLLE_AUX_0, 0x48C */
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uint32_t sata_pll_cfg0; /* _SATA_PLL_CFG0_0, 0x490 */
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uint32_t sata_pll_cfg1; /* _SATA_PLL_CFG1_0, 0x494 */
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uint32_t pcie_pll_cfg0; /* _PCIE_PLL_CFG0_0, 0x498 */
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uint32_t prog_audio_dly_clk; /* _PROG_AUDIO_DLY_CLK_0, 0x49C */
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uint32_t audio_sync_clk_i2s0; /* _AUDIO_SYNC_CLK_I2S0_0, 0x4A0 */
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uint32_t audio_sync_clk_i2s1; /* _AUDIO_SYNC_CLK_I2S1_0, 0x4A4 */
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uint32_t audio_sync_clk_i2s2; /* _AUDIO_SYNC_CLK_I2S2_0, 0x4A8 */
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uint32_t audio_sync_clk_i2s3; /* _AUDIO_SYNC_CLK_I2S3_0, 0x4AC */
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uint32_t audio_sync_clk_i2s4; /* _AUDIO_SYNC_CLK_I2S4_0, 0x4B0 */
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uint32_t audio_sync_clk_spdif; /* _AUDIO_SYNC_CLK_SPDIF_0, 0x4B4 */
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uint32_t plld2_base; /* _PLLD2_BASE_0, 0x4B8 */
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uint32_t plld2_misc; /* _PLLD2_MISC_0, 0x4BC */
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uint32_t utmip_pll_cfg3; /* _UTMIP_PLL_CFG3_0, 0x4C0 */
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uint32_t pllrefe_base; /* _PLLREFE_BASE_0, 0x4C4 */
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uint32_t pllrefe_misc; /* _PLLREFE_MISC_0, 0x4C8 */
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uint32_t crs_reserved_50[7]; /* _reserved_50, 0x4CC-0x4E4 */
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uint32_t pllc2_base; /* _PLLC2_BASE_0, 0x4E8 */
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uint32_t pllc2_misc0; /* _PLLC2_MISC_0_0, 0x4EC */
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uint32_t pllc2_misc1; /* _PLLC2_MISC_1_0, 0x4F0 */
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uint32_t pllc2_misc2; /* _PLLC2_MISC_2_0, 0x4F4 */
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uint32_t pllc2_misc3; /* _PLLC2_MISC_3_0, 0x4F8 */
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uint32_t pllc3_base; /* _PLLC3_BASE_0, 0x4FC */
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uint32_t pllc3_misc0; /* _PLLC3_MISC_0_0, 0x500 */
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uint32_t pllc3_misc1; /* _PLLC3_MISC_1_0, 0x504 */
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uint32_t pllc3_misc2; /* _PLLC3_MISC_2_0, 0x508 */
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uint32_t pllc3_misc3; /* _PLLC3_MISC_3_0, 0x50C */
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uint32_t pllx_misc1; /* _PLLX_MISC_1_0, 0x510 */
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uint32_t pllx_misc2; /* _PLLX_MISC_2_0, 0x514 */
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uint32_t pllx_misc3; /* _PLLX_MISC_3_0, 0x518 */
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uint32_t xusbio_pll_cfg0; /* _XUSBIO_PLL_CFG0_0, 0x51C */
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uint32_t xusbio_pll_cfg1; /* _XUSBIO_PLL_CFG0_1, 0x520 */
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uint32_t plle_aux1; /* _PLLE_AUX1_0, 0x524 */
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uint32_t pllp_reshift; /* _PLLP_RESHIFT_0, 0x528 */
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uint32_t utmipll_hw_pwrdn_cfg0; /* _UTMIPLL_HW_PWRDN_CFG0_0, 0x52C */
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uint32_t pllu_hw_pwrdn_cfg0; /* _PLLU_HW_PWRDN_CFG0_0, 0x530 */
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uint32_t xusb_pll_cfg0; /* _XUSB_PLL_CFG0_0, 0x534 */
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uint32_t reserved51[1]; /* _reserved_51, 0x538 */
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uint32_t clk_cpu_misc; /* _CLK_CPU_MISC_0, 0x53C */
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uint32_t clk_cpug_misc; /* _CLK_CPUG_MISC_0, 0x540 */
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uint32_t clk_cpulp_misc; /* _CLK_CPULP_MISC_0, 0x544 */
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uint32_t pllx_hw_ctrl_cfg; /* _PLLX_HW_CTRL_CFG_0, 0x548 */
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uint32_t pllx_sw_ramp_cfg; /* _PLLX_SW_RAMP_CFG_0, 0x54C */
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uint32_t pllx_hw_ctrl_status; /* _PLLX_HW_CTRL_STATUS_0, 0x550 */
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uint32_t reserved52[1]; /* _reserved_52, 0x554 */
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uint32_t super_gr3d_clk_div; /* _SUPER_GR3D_CLK_DIVIDER_0, 0x558 */
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uint32_t spare_reg0; /* _SPARE_REG0_0, 0x55C */
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uint32_t _rsv32[4]; /* 0x560-0x56c */
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uint32_t plld2_ss_cfg; /* _PLLD2_SS_CFG 0x570 */
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uint32_t _rsv32_1[7]; /* 0x574-58c */
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struct clk_pll_simple plldp; /* _PLLDP_BASE, 0x590 _PLLDP_MISC */
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uint32_t plldp_ss_cfg; /* _PLLDP_SS_CFG, 0x598 */
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/* Tegra124+ - skip to 0x600 here for new CLK_SOURCE_ regs */
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uint32_t _rsrv32_2[25]; /* _0x59C - 0x5FC */
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uint32_t clk_src_x[TEGRA_CLK_SOURCES_X]; /* XUSB, etc, 0x600-0x67C */
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/* Tegra210 - skip to 0x694 here for new CLK_SOURCE_ regs */
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uint32_t reserved61[5]; /* _reserved_61, 0x680 - 0x690 */
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/*
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* NOTE: PLLA1 regs are in the middle of this Y region. Break this in
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* two later if PLLA1 is needed, but for now this is cleaner.
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*/
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uint32_t clk_src_y[TEGRA_CLK_SOURCES_Y]; /* SPARE1, etc, 0x694-0x6D8 */
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};
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/**
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* Utility function that grabs the Tegra CAR registers.
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*/
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static inline struct tegra_car *car_get_regs(void)
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{
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return (struct tegra_car *)0x60006000UL;
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}
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#endif
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