mirror of
https://github.com/Atmosphere-NX/Atmosphere
synced 2025-01-11 23:34:50 +00:00
688 lines
30 KiB
C++
688 lines
30 KiB
C++
/*
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* Copyright (c) 2018-2020 Atmosphère-NX
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#if defined(ATMOSPHERE_IS_STRATOSPHERE)
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#include <stratosphere.hpp>
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#elif defined(ATMOSPHERE_IS_MESOSPHERE)
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#include <mesosphere.hpp>
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#elif defined(ATMOSPHERE_IS_EXOSPHERE)
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#include <exosphere.hpp>
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#else
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#include <vapours.hpp>
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#endif
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#include "sdmmc_sdmmc_controller.board.nintendo_nx.hpp"
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#include "sdmmc_io_impl.board.nintendo_nx.hpp"
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namespace ams::sdmmc::impl {
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Result SetSdCardVoltageEnabled(bool en) {
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/* TODO */
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AMS_UNUSED(en);
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AMS_ABORT();
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}
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Result SetSdCardVoltageValue(u32 micro_volts) {
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/* TODO */
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AMS_UNUSED(micro_volts);
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AMS_ABORT();
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}
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namespace gpio_impl {
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namespace {
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constexpr inline dd::PhysicalAddress GpioRegistersPhysicalAddress = 0x6000d000;
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constexpr inline size_t GpioRegistersSize = 4_KB;
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enum GpioPadPort {
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GpioPadPort_A = 0,
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GpioPadPort_B = 1,
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GpioPadPort_C = 2,
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GpioPadPort_D = 3,
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GpioPadPort_E = 4,
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GpioPadPort_F = 5,
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GpioPadPort_G = 6,
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GpioPadPort_H = 7,
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GpioPadPort_I = 8,
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GpioPadPort_J = 9,
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GpioPadPort_K = 10,
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GpioPadPort_L = 11,
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GpioPadPort_M = 12,
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GpioPadPort_N = 13,
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GpioPadPort_O = 14,
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GpioPadPort_P = 15,
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GpioPadPort_Q = 16,
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GpioPadPort_R = 17,
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GpioPadPort_S = 18,
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GpioPadPort_T = 19,
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GpioPadPort_U = 20,
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GpioPadPort_V = 21,
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GpioPadPort_W = 22,
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GpioPadPort_X = 23,
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GpioPadPort_Y = 24,
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GpioPadPort_Z = 25,
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GpioPadPort_AA = 26,
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GpioPadPort_BB = 27,
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GpioPadPort_CC = 28,
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GpioPadPort_DD = 29,
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GpioPadPort_EE = 30,
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GpioPadPort_FF = 31,
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};
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consteval unsigned int GetInternalGpioPadNumber(GpioPadPort port, unsigned int which) {
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AMS_ASSUME(which < 8);
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return (static_cast<unsigned int>(port) * 8) + which;
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}
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enum InternalGpioPadNumber {
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InternalGpioPadNumber_E4 = GetInternalGpioPadNumber(GpioPadPort_E, 4),
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InternalGpioPadNumber_M0 = GetInternalGpioPadNumber(GpioPadPort_M, 0),
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};
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constexpr int ConvertInternalGpioPadNumberToController(InternalGpioPadNumber number) {
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return (number >> 5);
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}
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constexpr int ConvertInternalGpioPadNumberToPort(InternalGpioPadNumber number) {
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return (number >> 3);
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}
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constexpr int ConvertInternalGpioPadNumberToBitIndex(InternalGpioPadNumber number) {
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return (number & 7);
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}
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constexpr int ConvertPortNumberToOffset(int port_number) {
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return (port_number & 3);
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}
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struct PadNameToInternalPadNumberEntry {
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GpioPadName pad_name;
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InternalGpioPadNumber internal_number;
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};
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constexpr inline const PadNameToInternalPadNumberEntry PadNameToInternalPadNumberTable[] = {
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{ GpioPadName_PowSdEn, InternalGpioPadNumber_E4 },
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};
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constexpr InternalGpioPadNumber ConvertPadNameToInternalPadNumber(GpioPadName pad) {
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const PadNameToInternalPadNumberEntry *target = nullptr;
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for (const auto &entry : PadNameToInternalPadNumberTable) {
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if (entry.pad_name == pad) {
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target = std::addressof(entry);
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break;
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}
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}
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AMS_ABORT_UNLESS(target != nullptr);
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return target->internal_number;
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}
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enum GpioRegisterType {
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GpioRegisterType_GPIO_CNF = 0,
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GpioRegisterType_GPIO_OE = 1,
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GpioRegisterType_GPIO_OUT = 2,
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GpioRegisterType_GPIO_IN = 3,
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GpioRegisterType_GPIO_INT_STA = 4,
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GpioRegisterType_GPIO_INT_ENB = 5,
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GpioRegisterType_GPIO_INT_LVL = 6,
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GpioRegisterType_GPIO_INT_CLR = 7,
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GpioRegisterType_GPIO_DB_CTRL = 8,
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GpioRegisterType_GPIO_DB_CNT = 9,
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};
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constexpr inline uintptr_t MaskedWriteAddressOffset = 0x80;
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constexpr inline int MaskedWriteBitOffset = 8;
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constexpr uintptr_t GetGpioRegisterAddress(uintptr_t gpio_address, GpioRegisterType reg_type, InternalGpioPadNumber pad_number) {
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const auto controller = ConvertInternalGpioPadNumberToController(pad_number);
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const auto port = ConvertInternalGpioPadNumberToPort(pad_number);
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const auto offset = ConvertPortNumberToOffset(port);
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switch (reg_type) {
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default:
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return gpio_address + (0x100 * controller) + (0x10 * reg_type) + (0x4 * offset);
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case GpioRegisterType_GPIO_DB_CTRL:
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return gpio_address + (0x100 * controller) + (0x10 * GpioRegisterType_GPIO_IN) + (0x4 * offset);
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case GpioRegisterType_GPIO_DB_CNT:
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return gpio_address + (0x100 * controller) + MaskedWriteAddressOffset + (0x10 * GpioRegisterType_GPIO_INT_CLR) + (0x4 * offset);
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}
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}
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void SetMaskedBit(uintptr_t pad_address, int index, int value) {
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const uintptr_t mask_address = pad_address + MaskedWriteAddressOffset;
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reg::Write(mask_address, (1u << (MaskedWriteBitOffset + index)) | (static_cast<unsigned int>(value) << index));
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}
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void SetMaskedBits(uintptr_t pad_address, unsigned int mask, unsigned int value) {
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const uintptr_t mask_address = pad_address + MaskedWriteAddressOffset;
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reg::Write(mask_address, (mask << MaskedWriteBitOffset) | (value));
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}
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}
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void OpenSession(GpioPadName pad) {
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/* Convert the pad to an internal number. */
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const auto pad_number = ConvertPadNameToInternalPadNumber(pad);
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/* Get the gpio registers address. */
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const uintptr_t gpio_address = dd::QueryIoMapping(GpioRegistersPhysicalAddress, GpioRegistersSize);
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/* Configure the pad as GPIO by setting the appropriate bit in CNF. */
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const uintptr_t pad_address = GetGpioRegisterAddress(gpio_address, GpioRegisterType_GPIO_CNF, pad_number);
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const uintptr_t pad_index = ConvertInternalGpioPadNumberToBitIndex(pad_number);
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SetMaskedBit(pad_address, pad_index, 1);
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/* Read the pad address to make sure our configuration takes. */
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reg::Read(pad_address);
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}
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void CloseSession(GpioPadName pad) {
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/* Nothing needs to be done here, as the only thing official code does is unbind the interrupt event. */
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AMS_UNUSED(pad);
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}
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void SetDirection(GpioPadName pad, Direction direction) {
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/* Convert the pad to an internal number. */
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const auto pad_number = ConvertPadNameToInternalPadNumber(pad);
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/* Get the gpio registers address. */
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const uintptr_t gpio_address = dd::QueryIoMapping(GpioRegistersPhysicalAddress, GpioRegistersSize);
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/* Configure the pad direction modifying the appropriate bit in OE. */
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const uintptr_t pad_address = GetGpioRegisterAddress(gpio_address, GpioRegisterType_GPIO_OE, pad_number);
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const uintptr_t pad_index = ConvertInternalGpioPadNumberToBitIndex(pad_number);
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SetMaskedBit(pad_address, pad_index, direction);
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/* Read the pad address to make sure our configuration takes. */
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reg::Read(pad_address);
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}
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void SetValue(GpioPadName pad, GpioValue value) {
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/* Convert the pad to an internal number. */
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const auto pad_number = ConvertPadNameToInternalPadNumber(pad);
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/* Get the gpio registers address. */
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const uintptr_t gpio_address = dd::QueryIoMapping(GpioRegistersPhysicalAddress, GpioRegistersSize);
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/* Configure the pad value modifying the appropriate bit in OUT. */
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const uintptr_t pad_address = GetGpioRegisterAddress(gpio_address, GpioRegisterType_GPIO_OUT, pad_number);
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const uintptr_t pad_index = ConvertInternalGpioPadNumberToBitIndex(pad_number);
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SetMaskedBit(pad_address, pad_index, value);
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/* Read the pad address to make sure our configuration takes. */
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reg::Read(pad_address);
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}
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}
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namespace pinmux_impl {
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namespace {
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constexpr auto Sdmmc1ClkCmdDat03PadNumber = gpio_impl::InternalGpioPadNumber_M0;
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constexpr unsigned int Sdmmc1ClkCmdDat03PadMask = 0x3F;
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constexpr unsigned int Sdmmc1ClkCmdDat03PadCnfGpio = 0x3F;
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constexpr unsigned int Sdmmc1ClkCmdDat03PadCnfSfio = 0x00;
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constexpr unsigned int Sdmmc1ClkCmdDat03PadOutHigh = 0x3F;
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constexpr unsigned int Sdmmc1ClkCmdDat03PadOutLow = 0x00;
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constexpr unsigned int Sdmmc1ClkCmdDat03PadOeOutput = 0x3F;
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constexpr unsigned int Sdmmc1ClkCmdDat03PadOeInput = 0x00;
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struct PinmuxDefinition {
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u32 reg_offset;
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u32 mask_val;
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u32 pm_val;
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};
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/* NOTE: We only use the SDMMC1 pins, which are conveniently the first few... */
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constexpr const PinmuxDefinition PinmuxDefinitionMap[] = {
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{0x00003000, 0x72FF, 0x01}, /* Sdmmc1Clk */
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{0x00003004, 0x72FF, 0x02}, /* Sdmmc1Cmd */
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{0x00003008, 0x72FF, 0x02}, /* Sdmmc1Dat3 */
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{0x0000300C, 0x72FF, 0x02}, /* Sdmmc1Dat2 */
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{0x00003010, 0x72FF, 0x02}, /* Sdmmc1Dat1 */
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{0x00003014, 0x72FF, 0x01}, /* Sdmmc1Dat0 */
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};
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enum PinmuxPadIndex {
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PinmuxPadIndex_Sdmmc1Clk = 0,
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PinmuxPadIndex_Sdmmc1Cmd = 1,
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PinmuxPadIndex_Sdmmc1Dat3 = 2,
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PinmuxPadIndex_Sdmmc1Dat2 = 3,
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PinmuxPadIndex_Sdmmc1Dat1 = 4,
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PinmuxPadIndex_Sdmmc1Dat0 = 5,
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PinmuxPadIndex_Count,
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};
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static_assert(util::size(PinmuxDefinitionMap) == PinmuxPadIndex_Count);
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consteval const PinmuxDefinition GetDefinition(PinmuxPadIndex pad_index) {
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AMS_ABORT_UNLESS(pad_index < PinmuxPadIndex_Count);
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return PinmuxDefinitionMap[pad_index];
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}
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template<PinmuxPadIndex PadIndex, u32 PinmuxConfigVal, u32 PinmuxConfigMaskVal>
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ALWAYS_INLINE u32 UpdatePinmuxPad(uintptr_t pinmux_base_vaddr) {
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constexpr const PinmuxDefinition Definition = GetDefinition(PadIndex);
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/* Fetch this PINMUX's register offset */
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constexpr u32 PinmuxRegOffset = Definition.reg_offset;
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/* Fetch this PINMUX's mask value */
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constexpr u32 PinmuxMaskVal = Definition.mask_val;
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/* Get current register ptr. */
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const uintptr_t pinmux_reg = pinmux_base_vaddr + PinmuxRegOffset;
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/* Read from the PINMUX register */
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u32 pinmux_val = reg::Read(pinmux_reg);
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/* This PINMUX register is locked */
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AMS_ABORT_UNLESS((pinmux_val & 0x80) == 0);
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constexpr u32 PmVal = (PinmuxConfigVal & 0x07);
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/* Adjust PM */
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if constexpr (PinmuxConfigMaskVal & 0x07) {
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/* Apply additional changes first */
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if constexpr (PmVal == 0x05) {
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/* This pin supports PUPD change */
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if constexpr (PinmuxMaskVal & 0x0C) {
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/* Change PUPD */
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if ((pinmux_val & 0x0C) != 0x04) {
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pinmux_val &= 0xFFFFFFF3;
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pinmux_val |= 0x04;
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}
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}
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/* This pin supports Tristate change */
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if constexpr (PinmuxMaskVal & 0x10) {
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/* Change Tristate */
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if (!(pinmux_val & 0x10)) {
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pinmux_val |= 0x10;
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}
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}
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/* This pin supports EInput change */
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if constexpr (PinmuxMaskVal & 0x40) {
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/* Change EInput */
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if (pinmux_val & 0x40) {
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pinmux_val &= 0xFFFFFFBF;
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}
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}
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}
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/* Translate PM value if necessary */
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constexpr u32 TranslatedPmVal = (PmVal == 0x04 || PmVal == 0x05 || PmVal >= 0x06) ? Definition.pm_val : PmVal;
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/* This pin supports PM change */
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if constexpr (PinmuxMaskVal & 0x03) {
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/* Change PM */
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if ((pinmux_val & 0x03) != (TranslatedPmVal & 0x03)) {
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pinmux_val &= 0xFFFFFFFC;
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pinmux_val |= (TranslatedPmVal & 0x03);
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}
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}
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}
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constexpr u32 PupdConfigVal = (PinmuxConfigVal & 0x18);
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/* Adjust PUPD */
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if constexpr (PinmuxConfigMaskVal & 0x18) {
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if constexpr (PupdConfigVal < 0x11) {
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/* This pin supports PUPD change */
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if constexpr (PinmuxMaskVal & 0x0C) {
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/* Change PUPD */
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if (((pinmux_val >> 0x02) & 0x03) != (PupdConfigVal >> 0x03)) {
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pinmux_val &= 0xFFFFFFF3;
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pinmux_val |= (PupdConfigVal >> 0x01);
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}
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}
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}
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}
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constexpr u32 EodConfigVal = (PinmuxConfigVal & 0x60);
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/* Adjust EOd field */
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if constexpr (PinmuxConfigMaskVal & 0x60) {
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if constexpr (EodConfigVal == 0x20) {
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/* This pin supports Tristate change */
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if constexpr (PinmuxMaskVal & 0x10) {
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/* Change Tristate */
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if (!(pinmux_val & 0x10)) {
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pinmux_val |= 0x10;
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}
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}
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/* This pin supports EInput change */
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if constexpr (PinmuxMaskVal & 0x40) {
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/* Change EInput */
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if (!(pinmux_val & 0x40)) {
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pinmux_val |= 0x40;
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}
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}
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/* This pin supports EOd change */
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if constexpr (PinmuxMaskVal & 0x800) {
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/* Change EOd */
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if (pinmux_val & 0x800) {
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pinmux_val &= 0xFFFFF7FF;
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}
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}
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} else if constexpr (EodConfigVal == 0x40) {
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/* This pin supports Tristate change */
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if constexpr (PinmuxMaskVal & 0x10) {
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/* Change Tristate */
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if (pinmux_val & 0x10) {
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pinmux_val &= 0xFFFFFFEF;
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}
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}
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/* This pin supports EInput change */
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if constexpr (PinmuxMaskVal & 0x40) {
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/* Change EInput */
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if (!(pinmux_val & 0x40)) {
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pinmux_val |= 0x40;
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}
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}
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/* This pin supports EOd change */
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if constexpr (PinmuxMaskVal & 0x800) {
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/* Change EOd */
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if (pinmux_val & 0x800) {
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pinmux_val &= 0xFFFFF7FF;
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}
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}
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} else if constexpr (EodConfigVal == 0x60) {
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/* This pin supports Tristate change */
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if constexpr (PinmuxMaskVal & 0x10) {
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/* Change Tristate */
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if (pinmux_val & 0x10) {
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pinmux_val &= 0xFFFFFFEF;
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}
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}
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/* This pin supports EInput change */
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if constexpr (PinmuxMaskVal & 0x40) {
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/* Change EInput */
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if (!(pinmux_val & 0x40)) {
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pinmux_val |= 0x40;
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}
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}
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/* This pin supports EOd change */
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if constexpr (PinmuxMaskVal & 0x800) {
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/* Change EOd */
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if (!(pinmux_val & 0x800)) {
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pinmux_val |= 0x800;
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}
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}
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} else {
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/* This pin supports Tristate change */
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if constexpr (PinmuxMaskVal & 0x10) {
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/* Change Tristate */
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if (pinmux_val & 0x10) {
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pinmux_val &= 0xFFFFFFEF;
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}
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}
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/* This pin supports EInput change */
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if constexpr (PinmuxMaskVal & 0x40) {
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/* Change EInput */
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if (pinmux_val & 0x40) {
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pinmux_val &= 0xFFFFFFBF;
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}
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}
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/* This pin supports EOd change */
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if constexpr (PinmuxMaskVal & 0x800) {
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/* Change EOd */
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if (pinmux_val & 0x800) {
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pinmux_val &= 0xFFFFF7FF;
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}
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}
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}
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}
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constexpr u32 LockConfigVal = (PinmuxConfigVal & 0x80);
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/* Adjust Lock */
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if constexpr (PinmuxConfigMaskVal & 0x80) {
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/* This pin supports Lock change */
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if constexpr (PinmuxMaskVal & 0x80) {
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/* Change Lock */
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if ((pinmux_val ^ PinmuxConfigVal) & 0x80) {
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pinmux_val &= 0xFFFFFF7F;
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pinmux_val |= LockConfigVal;
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}
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}
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}
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constexpr u32 IoResetConfigVal = (((PinmuxConfigVal >> 0x08) & 0x1) << 0x10);
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/* Adjust IoReset */
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if constexpr (PinmuxConfigMaskVal & 0x100) {
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/* This pin supports IoReset change */
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if constexpr (PinmuxMaskVal & 0x10000) {
|
|
/* Change IoReset */
|
|
if (((pinmux_val >> 0x10) ^ (PinmuxConfigVal >> 0x08)) & 0x01) {
|
|
pinmux_val &= 0xFFFEFFFF;
|
|
pinmux_val |= IoResetConfigVal;
|
|
}
|
|
}
|
|
}
|
|
|
|
constexpr u32 ParkConfigVal = (((PinmuxConfigVal >> 0x0A) & 0x1) << 0x5);
|
|
|
|
/* Adjust Park */
|
|
if constexpr (PinmuxConfigMaskVal & 0x400) {
|
|
/* This pin supports Park change */
|
|
if constexpr (PinmuxMaskVal & 0x20) {
|
|
/* Change Park */
|
|
if (((pinmux_val >> 0x05) ^ (PinmuxConfigVal >> 0x0A)) & 0x01) {
|
|
pinmux_val &= 0xFFFFFFDF;
|
|
pinmux_val |= ParkConfigVal;
|
|
}
|
|
}
|
|
}
|
|
|
|
constexpr u32 ElpdrConfigVal = (((PinmuxConfigVal >> 0x0B) & 0x1) << 0x08);
|
|
|
|
/* Adjust ELpdr */
|
|
if constexpr (PinmuxConfigMaskVal & 0x800) {
|
|
/* This pin supports ELpdr change */
|
|
if constexpr (PinmuxMaskVal & 0x100) {
|
|
/* Change ELpdr */
|
|
if (((pinmux_val >> 0x08) ^ (PinmuxConfigVal >> 0x0B)) & 0x01) {
|
|
pinmux_val &= 0xFFFFFEFF;
|
|
pinmux_val |= ElpdrConfigVal;
|
|
}
|
|
}
|
|
}
|
|
|
|
constexpr u32 EhsmConfigVal = (((PinmuxConfigVal >> 0x0C) & 0x1) << 0x09);
|
|
|
|
/* Adjust EHsm */
|
|
if constexpr (PinmuxConfigMaskVal & 0x1000) {
|
|
/* This pin supports EHsm change */
|
|
if constexpr (PinmuxMaskVal & 0x200) {
|
|
/* Change EHsm */
|
|
if (((pinmux_val >> 0x09) ^ (PinmuxConfigVal >> 0x0C)) & 0x01) {
|
|
pinmux_val &= 0xFFFFFDFF;
|
|
pinmux_val |= EhsmConfigVal;
|
|
}
|
|
}
|
|
}
|
|
|
|
constexpr u32 EIoHvConfigVal = (((PinmuxConfigVal >> 0x09) & 0x1) << 0x0A);
|
|
|
|
/* Adjust EIoHv */
|
|
if constexpr (PinmuxConfigMaskVal & 0x200) {
|
|
/* This pin supports EIoHv change */
|
|
if constexpr (PinmuxMaskVal & 0x400) {
|
|
/* Change EIoHv */
|
|
if (((pinmux_val >> 0x0A) ^ (PinmuxConfigVal >> 0x09)) & 0x01) {
|
|
pinmux_val &= 0xFFFFFBFF;
|
|
pinmux_val |= EIoHvConfigVal;
|
|
}
|
|
}
|
|
}
|
|
|
|
constexpr u32 EschmtConfigVal = (((PinmuxConfigVal >> 0x0D) & 0x1) << 0x0C);
|
|
|
|
/* Adjust ESchmt */
|
|
if constexpr (PinmuxConfigMaskVal & 0x2000) {
|
|
/* This pin supports ESchmt change */
|
|
if constexpr (PinmuxMaskVal & 0x1000) {
|
|
/* Change ESchmt */
|
|
if (((pinmux_val >> 0x0C) ^ (PinmuxConfigVal >> 0x0D)) & 0x01) {
|
|
pinmux_val &= 0xFFFFEFFF;
|
|
pinmux_val |= EschmtConfigVal;
|
|
}
|
|
}
|
|
}
|
|
|
|
constexpr u32 PreempConfigVal = (((PinmuxConfigVal >> 0x10) & 0x1) << 0xF);
|
|
|
|
/* Adjust Preemp */
|
|
if constexpr (PinmuxConfigMaskVal & 0x10000) {
|
|
/* This pin supports Preemp change */
|
|
if constexpr (PinmuxMaskVal & 0x8000) {
|
|
/* Change Preemp */
|
|
if (((pinmux_val >> 0x0F) ^ (PinmuxConfigVal >> 0x10)) & 0x01) {
|
|
pinmux_val &= 0xFFFF7FFF;
|
|
pinmux_val |= PreempConfigVal;
|
|
}
|
|
}
|
|
}
|
|
|
|
constexpr u32 DrvTypeConfigVal = (((PinmuxConfigVal >> 0x0E) & 0x3) << 0xD);
|
|
|
|
/* Adjust DrvType */
|
|
if constexpr (PinmuxConfigMaskVal & 0xC000) {
|
|
/* This pin supports DrvType change */
|
|
if constexpr (PinmuxMaskVal & 0x6000) {
|
|
/* Change DrvType */
|
|
if (((pinmux_val >> 0x0D) ^ (PinmuxConfigVal >> 0x0E)) & 0x03) {
|
|
pinmux_val &= 0xFFFF9FFF;
|
|
pinmux_val |= DrvTypeConfigVal;
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Write to the appropriate PINMUX register */
|
|
reg::Write(pinmux_reg, pinmux_val);
|
|
|
|
/* Do a dummy read from the PINMUX register */
|
|
pinmux_val = reg::Read(pinmux_reg);
|
|
|
|
return pinmux_val;
|
|
}
|
|
|
|
}
|
|
|
|
void SetPinAssignment(PinAssignment assignment) {
|
|
/* Get the apb registers address. */
|
|
const uintptr_t apb_address = dd::QueryIoMapping(ApbMiscRegistersPhysicalAddress, ApbMiscRegistersSize);
|
|
AMS_UNUSED(apb_address);
|
|
|
|
/* Set the pin assignment. */
|
|
switch (assignment) {
|
|
case PinAssignment_Sdmmc1OutputHigh:
|
|
{
|
|
/* Clear Sdmmc1Clk pulldown. */
|
|
UpdatePinmuxPad<PinmuxPadIndex_Sdmmc1Clk, 0, 0x18>(apb_address);
|
|
|
|
/* Get the gpio registers address. */
|
|
const uintptr_t gpio_address = dd::QueryIoMapping(gpio_impl::GpioRegistersPhysicalAddress, gpio_impl::GpioRegistersSize);
|
|
|
|
/* Configure GPIO M0-5 (SDMMC1 CLK + CMD + DAT0/1/2/3) as gpio. */
|
|
const uintptr_t cnf_address = gpio_impl::GetGpioRegisterAddress(gpio_address, gpio_impl::GpioRegisterType_GPIO_CNF, Sdmmc1ClkCmdDat03PadNumber);
|
|
gpio_impl::SetMaskedBits(cnf_address, Sdmmc1ClkCmdDat03PadMask, Sdmmc1ClkCmdDat03PadCnfGpio);
|
|
|
|
/* Configure GPIO M0-5 (SDMMC1 CLK + CMD + DAT0/1/2/3) as high. */
|
|
const uintptr_t out_address = gpio_impl::GetGpioRegisterAddress(gpio_address, gpio_impl::GpioRegisterType_GPIO_OUT, Sdmmc1ClkCmdDat03PadNumber);
|
|
gpio_impl::SetMaskedBits(out_address, Sdmmc1ClkCmdDat03PadMask, Sdmmc1ClkCmdDat03PadOutHigh);
|
|
|
|
/* Configure GPIO M0-5 (SDMMC1 CLK + CMD + DAT0/1/2/3) as output. */
|
|
const uintptr_t oe_address = gpio_impl::GetGpioRegisterAddress(gpio_address, gpio_impl::GpioRegisterType_GPIO_OE, Sdmmc1ClkCmdDat03PadNumber);
|
|
gpio_impl::SetMaskedBits(oe_address, Sdmmc1ClkCmdDat03PadMask, Sdmmc1ClkCmdDat03PadOeOutput);
|
|
|
|
/* Read to be sure that our configuration takes. */
|
|
reg::Read(oe_address);
|
|
}
|
|
break;
|
|
case PinAssignment_Sdmmc1ResetState:
|
|
{
|
|
/* Get the gpio registers address. */
|
|
const uintptr_t gpio_address = dd::QueryIoMapping(gpio_impl::GpioRegistersPhysicalAddress, gpio_impl::GpioRegistersSize);
|
|
|
|
/* Configure GPIO M0-5 (SDMMC1 CLK + CMD + DAT0/1/2/3) as sfio. */
|
|
const uintptr_t cnf_address = gpio_impl::GetGpioRegisterAddress(gpio_address, gpio_impl::GpioRegisterType_GPIO_CNF, Sdmmc1ClkCmdDat03PadNumber);
|
|
gpio_impl::SetMaskedBits(cnf_address, Sdmmc1ClkCmdDat03PadMask, Sdmmc1ClkCmdDat03PadCnfSfio);
|
|
|
|
/* Configure GPIO M0-5 (SDMMC1 CLK + CMD + DAT0/1/2/3) as low. */
|
|
const uintptr_t out_address = gpio_impl::GetGpioRegisterAddress(gpio_address, gpio_impl::GpioRegisterType_GPIO_OUT, Sdmmc1ClkCmdDat03PadNumber);
|
|
gpio_impl::SetMaskedBits(out_address, Sdmmc1ClkCmdDat03PadMask, Sdmmc1ClkCmdDat03PadOutLow);
|
|
|
|
/* Configure GPIO M0-5 (SDMMC1 CLK + CMD + DAT0/1/2/3) as input. */
|
|
const uintptr_t oe_address = gpio_impl::GetGpioRegisterAddress(gpio_address, gpio_impl::GpioRegisterType_GPIO_OE, Sdmmc1ClkCmdDat03PadNumber);
|
|
gpio_impl::SetMaskedBits(oe_address, Sdmmc1ClkCmdDat03PadMask, Sdmmc1ClkCmdDat03PadOeInput);
|
|
|
|
/* Read to be sure that our configuration takes. */
|
|
reg::Read(oe_address);
|
|
|
|
/* Set Sdmmc1Clk pulldown. */
|
|
UpdatePinmuxPad<PinmuxPadIndex_Sdmmc1Clk, 0x8, 0x18>(apb_address);
|
|
}
|
|
break;
|
|
case PinAssignment_Sdmmc1SchmtEnable:
|
|
{
|
|
/* Set Schmitt enable for all pins in the group. */
|
|
UpdatePinmuxPad<PinmuxPadIndex_Sdmmc1Clk, 0x2000, 0x2000>(apb_address);
|
|
UpdatePinmuxPad<PinmuxPadIndex_Sdmmc1Cmd, 0x2000, 0x2000>(apb_address);
|
|
UpdatePinmuxPad<PinmuxPadIndex_Sdmmc1Dat3, 0x2000, 0x2000>(apb_address);
|
|
UpdatePinmuxPad<PinmuxPadIndex_Sdmmc1Dat2, 0x2000, 0x2000>(apb_address);
|
|
UpdatePinmuxPad<PinmuxPadIndex_Sdmmc1Dat1, 0x2000, 0x2000>(apb_address);
|
|
UpdatePinmuxPad<PinmuxPadIndex_Sdmmc1Dat0, 0x2000, 0x2000>(apb_address);
|
|
}
|
|
break;
|
|
case PinAssignment_Sdmmc1SchmtDisable:
|
|
{
|
|
/* Set Schmitt disable for all pins in the group. */
|
|
UpdatePinmuxPad<PinmuxPadIndex_Sdmmc1Clk, 0x0000, 0x2000>(apb_address);
|
|
UpdatePinmuxPad<PinmuxPadIndex_Sdmmc1Cmd, 0x0000, 0x2000>(apb_address);
|
|
UpdatePinmuxPad<PinmuxPadIndex_Sdmmc1Dat3, 0x0000, 0x2000>(apb_address);
|
|
UpdatePinmuxPad<PinmuxPadIndex_Sdmmc1Dat2, 0x0000, 0x2000>(apb_address);
|
|
UpdatePinmuxPad<PinmuxPadIndex_Sdmmc1Dat1, 0x0000, 0x2000>(apb_address);
|
|
UpdatePinmuxPad<PinmuxPadIndex_Sdmmc1Dat0, 0x0000, 0x2000>(apb_address);
|
|
}
|
|
break;
|
|
AMS_UNREACHABLE_DEFAULT_CASE();
|
|
}
|
|
}
|
|
|
|
}
|
|
|
|
}
|