mirror of
https://github.com/Atmosphere-NX/Atmosphere
synced 2024-09-19 22:59:00 +00:00
3a1ccdd919
* ams: update to build with gcc10/c++20 * remove mno-outline-atomics * ams: take care of most TODO C++20s * fusee/sept: update for gcc10 * whoosh, your code now uses pre-compiled headers * make: dependency fixes
194 lines
6.6 KiB
C
194 lines
6.6 KiB
C
/*
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* Copyright (c) 2018-2020 Atmosphère-NX
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef EXOSPHERE_MMU_H
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#define EXOSPHERE_MMU_H
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#include <stdbool.h>
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#include <stdint.h>
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#include <stddef.h>
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#include "utils.h"
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#ifndef MMU_GRANULE_TYPE
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#define MMU_GRANULE_TYPE 0 /* 0: 4KB, 1: 64KB, 2: 16KB. The Switch always uses a 4KB granule size. */
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#endif
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#if MMU_GRANULE_TYPE == 0
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#define MMU_Lx_SHIFT(x) (12 + 9 * (3 - (x)))
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#define MMU_Lx_MASK(x) MASKL(9)
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#elif MMU_GRANULE_TYPE == 1
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/* 64 KB, no L0 here */
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#define MMU_Lx_SHIFT(x) (16 + 13 * (3 - (x)))
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#define MMU_Lx_MASK(x) ((x) == 1 ? MASKL(5) : MASKL(13))
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#elif MMU_GRANULE_TYPE == 2
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#define MMU_Lx_SHIFT(x) (14 + 11 * (3 - (x)))
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#define MMU_Lx_MASK(x) ((x) == 0 ? 1 : MASKL(11))
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#endif
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/*
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* The following defines are adapted from uboot:
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*
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* (C) Copyright 2013
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* David Feng <fenghua@phytium.com.cn>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/* Memory attributes, see set_memory_registers_enable_mmu */
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#define MMU_MT_NORMAL 0ull
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#define MMU_MT_DEVICE_NGNRE 1ull
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#define MMU_MT_DEVICE_NGNRNE 2ull /* not used, also the same as Attr4-7 */
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/*
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* Hardware page table definitions.
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*
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*/
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#define MMU_PTE_TYPE_MASK 3ull
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#define MMU_PTE_TYPE_FAULT 0ull
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#define MMU_PTE_TYPE_TABLE 3ull
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#define MMU_PTE_TYPE_BLOCK 1ull
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/* L3 only */
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#define MMU_PTE_TYPE_PAGE 3ull
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#define MMU_PTE_TABLE_PXN BITL(59)
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#define MMU_PTE_TABLE_XN BITL(60)
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#define MMU_PTE_TABLE_AP BITL(61)
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#define MMU_PTE_TABLE_NS BITL(63)
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/*
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* Block
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*/
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#define MMU_PTE_BLOCK_MEMTYPE(x) ((uint64_t)((x) << 2))
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#define MMU_PTE_BLOCK_NS BITL(5)
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#define MMU_PTE_BLOCK_NON_SHAREABLE (0ull << 8)
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#define MMU_PTE_BLOCK_OUTER_SHAREABLE (2ull << 8)
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#define MMU_PTE_BLOCK_INNER_SHAREBLE (3ull << 8)
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#define MMU_PTE_BLOCK_AF BITL(10)
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#define MMU_PTE_BLOCK_NG BITL(11)
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#define MMU_PTE_BLOCK_PXN BITL(53)
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#define MMU_PTE_BLOCK_UXN BITL(54)
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#define MMU_PTE_BLOCK_XN MMU_PTE_BLOCK_UXN
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/*
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* AP[2:1]
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*/
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#define MMU_AP_PRIV_RW (0ull << 6)
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#define MMU_AP_RW (1ull << 6)
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#define MMU_AP_PRIV_RO (2ull << 6)
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#define MMU_AP_RO (3ull << 6)
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/*
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* S2AP[2:1] (for stage2 translations; secmon doesn't use it)
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*/
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#define MMU_S2AP_NONE (0ull << 6)
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#define MMU_S2AP_RO (1ull << 6)
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#define MMU_S2AP_WO (2ull << 6)
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#define MMU_S2AP_RW (3ull << 6)
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/*
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* AttrIndx[2:0]
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*/
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#define MMU_PMD_ATTRINDX(t) ((uint64_t)((t) << 2))
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#define MMU_PMD_ATTRINDX_MASK (7ull << 2)
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/*
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* TCR flags.
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*/
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#define TCR_T0SZ(x) ((64 - (x)) << 0)
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#define TCR_IRGN_NC (0 << 8)
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#define TCR_IRGN_WBWA (1 << 8)
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#define TCR_IRGN_WT (2 << 8)
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#define TCR_IRGN_WBNWA (3 << 8)
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#define TCR_IRGN_MASK (3 << 8)
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#define TCR_ORGN_NC (0 << 10)
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#define TCR_ORGN_WBWA (1 << 10)
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#define TCR_ORGN_WT (2 << 10)
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#define TCR_ORGN_WBNWA (3 << 10)
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#define TCR_ORGN_MASK (3 << 10)
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#define TCR_NOT_SHARED (0 << 12)
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#define TCR_SHARED_OUTER (2 << 12)
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#define TCR_SHARED_INNER (3 << 12)
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#define TCR_TG0_4K (0 << 14)
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#define TCR_TG0_64K (1 << 14)
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#define TCR_TG0_16K (2 << 14)
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#define TCR_PS(x) ((x) << 16)
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#define TCR_EPD1_DISABLE BIT(23)
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#define TCR_EL1_RSVD BIT(31)
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#define TCR_EL2_RSVD (BIT(31) | BIT(23))
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#define TCR_EL3_RSVD (BIT(31) | BIT(23))
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static inline void mmu_init_table(volatile uintptr_t *tbl, size_t num_entries) {
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for(size_t i = 0; i < num_entries / 8; i++) {
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tbl[i] = MMU_PTE_TYPE_FAULT;
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}
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}
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/*
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All the functions below assume base_addr is valid.
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They do not invalidate the TLB, which must be done separately.
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*/
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static inline unsigned int mmu_compute_index(unsigned int level, uintptr_t base_addr) {
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return (base_addr >> MMU_Lx_SHIFT(level)) & MMU_Lx_MASK(level);
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}
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static inline void mmu_map_table(unsigned int level, uintptr_t *tbl, uintptr_t base_addr, uintptr_t *next_lvl_tbl_pa, uint64_t attrs) {
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tbl[mmu_compute_index(level, base_addr)] = (uintptr_t)next_lvl_tbl_pa | attrs | MMU_PTE_TYPE_TABLE;
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}
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static inline void mmu_map_block(unsigned int level, uintptr_t *tbl, uintptr_t base_addr, uintptr_t phys_addr, uint64_t attrs) {
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tbl[mmu_compute_index(level, base_addr)] = phys_addr | attrs | MMU_PTE_BLOCK_AF | MMU_PTE_TYPE_BLOCK;
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}
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static inline void mmu_map_page(uintptr_t *tbl, uintptr_t base_addr, uintptr_t phys_addr, uint64_t attrs) {
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tbl[mmu_compute_index(3, base_addr)] = phys_addr | attrs | MMU_PTE_BLOCK_AF | MMU_PTE_TYPE_PAGE;
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}
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static inline void mmu_unmap(unsigned int level, uintptr_t *tbl, uintptr_t base_addr) {
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tbl[mmu_compute_index(level, base_addr)] = MMU_PTE_TYPE_FAULT;
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}
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static inline void mmu_unmap_page(uintptr_t *tbl, uintptr_t base_addr) {
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tbl[mmu_compute_index(3, base_addr)] = MMU_PTE_TYPE_FAULT;
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}
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static inline void mmu_map_block_range(unsigned int level, uintptr_t *tbl, uintptr_t base_addr, uintptr_t phys_addr, size_t size, uint64_t attrs) {
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size = ((size + (BITL(MMU_Lx_SHIFT(level)) - 1)) >> MMU_Lx_SHIFT(level)) << MMU_Lx_SHIFT(level);
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for(size_t offset = 0; offset < size; offset += BITL(MMU_Lx_SHIFT(level))) {
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mmu_map_block(level, tbl, base_addr + offset, phys_addr + offset, attrs);
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}
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}
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static inline void mmu_map_page_range(uintptr_t *tbl, uintptr_t base_addr, uintptr_t phys_addr, size_t size, uint64_t attrs) {
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size = ((size + (BITL(MMU_Lx_SHIFT(3)) - 1)) >> MMU_Lx_SHIFT(3)) << MMU_Lx_SHIFT(3);
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for(size_t offset = 0; offset < size; offset += BITL(MMU_Lx_SHIFT(3))) {
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mmu_map_page(tbl, base_addr + offset, phys_addr + offset, attrs);
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}
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}
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static inline void mmu_unmap_range(unsigned int level, uintptr_t *tbl, uintptr_t base_addr, size_t size) {
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size = ((size + (BITL(MMU_Lx_SHIFT(level)) - 1)) >> MMU_Lx_SHIFT(level)) << MMU_Lx_SHIFT(level);
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for(size_t offset = 0; offset < size; offset += BITL(MMU_Lx_SHIFT(level))) {
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mmu_unmap(level, tbl, base_addr + offset);
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}
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}
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#endif
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