mirror of
https://github.com/Atmosphere-NX/Atmosphere
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104 lines
6.4 KiB
C++
104 lines
6.4 KiB
C++
/*
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* Copyright (c) 2018-2020 Atmosphère-NX
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#pragma once
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#include <vapours.hpp>
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/* Clock source enums. */
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#define CLK_RST_REG_BITS_MASK(NAME) REG_NAMED_BITS_MASK (CLK_RST_CONTROLLER, NAME)
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#define CLK_RST_REG_BITS_VALUE(NAME, VALUE) REG_NAMED_BITS_VALUE (CLK_RST_CONTROLLER, NAME, VALUE)
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#define CLK_RST_REG_BITS_ENUM(NAME, ENUM) REG_NAMED_BITS_ENUM (CLK_RST_CONTROLLER, NAME, ENUM)
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#define CLK_RST_REG_BITS_ENUM_SEL(NAME, __COND__, TRUE_ENUM, FALSE_ENUM) REG_NAMED_BITS_ENUM_SEL(CLK_RST_CONTROLLER, NAME, __COND__, TRUE_ENUM, FALSE_ENUM)
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#define DEFINE_CLK_RST_REG(NAME, __OFFSET__, __WIDTH__) REG_DEFINE_NAMED_REG (CLK_RST_CONTROLLER, NAME, __OFFSET__, __WIDTH__)
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#define DEFINE_CLK_RST_REG_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE) REG_DEFINE_NAMED_BIT_ENUM (CLK_RST_CONTROLLER, NAME, __OFFSET__, ZERO, ONE)
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#define DEFINE_CLK_RST_REG_TWO_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE) REG_DEFINE_NAMED_TWO_BIT_ENUM (CLK_RST_CONTROLLER, NAME, __OFFSET__, ZERO, ONE, TWO, THREE)
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#define DEFINE_CLK_RST_REG_THREE_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN) REG_DEFINE_NAMED_THREE_BIT_ENUM(CLK_RST_CONTROLLER, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN)
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#define DEFINE_CLK_RST_REG_FOUR_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN) REG_DEFINE_NAMED_FOUR_BIT_ENUM (CLK_RST_CONTROLLER, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN)
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#define CLK_RST_CONTROLLER_RST_SOURCE (0x000)
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#define CLK_RST_CONTROLLER_MISC_CLK_ENB (0x048)
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#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD (0x3A4)
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DEFINE_CLK_RST_REG(MISC_CLK_ENB_CFG_ALL_VISIBLE, 28, 1);
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/* RST_DEVICES */
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#define CLK_RST_CONTROLLER_RST_DEVICES_L (0x004)
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#define CLK_RST_CONTROLLER_RST_DEVICES_H (0x008)
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#define CLK_RST_CONTROLLER_RST_DEVICES_U (0x00C)
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#define CLK_RST_CONTROLLER_RST_DEVICES_X (0x28C)
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#define CLK_RST_CONTROLLER_RST_DEVICES_Y (0x2A4)
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#define CLK_RST_CONTROLLER_RST_DEVICES_V (0x358)
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#define CLK_RST_CONTROLLER_RST_DEVICES_W (0x35C)
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/* CLK_OUT_ENB */
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#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L (0x010)
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#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H (0x014)
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#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U (0x018)
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#define CLK_RST_CONTROLLER_CLK_OUT_ENB_X (0x280)
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#define CLK_RST_CONTROLLER_CLK_OUT_ENB_Y (0x298)
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#define CLK_RST_CONTROLLER_CLK_OUT_ENB_V (0x360)
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#define CLK_RST_CONTROLLER_CLK_OUT_ENB_W (0x364)
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/* CLK_SOURCE */
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#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1 (0x124)
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#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5 (0x128)
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#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA (0x178)
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#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB (0x17C)
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#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC (0x1A0)
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#define CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON (0x3E8)
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/* RST_DEV_*_CLR */
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#define CLK_RST_CONTROLLER_RST_DEV_L_CLR (0x304)
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/* CLK_ENB_*_INDEX */
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#define CLK_RST_CONTROLLER_CLK_ENB_I2C1_INDEX (0x0C)
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#define CLK_RST_CONTROLLER_CLK_ENB_I2C5_INDEX (0x0F)
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#define CLK_RST_CONTROLLER_CLK_ENB_UARTA_INDEX (0x06)
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#define CLK_RST_CONTROLLER_CLK_ENB_UARTB_INDEX (0x07)
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#define CLK_RST_CONTROLLER_CLK_ENB_UARTC_INDEX (0x17)
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#define CLK_RST_CONTROLLER_CLK_ENB_ACTMON_INDEX (0x17)
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/* RST_CPUG_CMPLX_* */
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#define CLK_RST_CONTROLLER_RST_CPUG_CMPLX_SET (0x450)
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#define CLK_RST_CONTROLLER_RST_CPUG_CMPLX_CLR (0x454)
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DEFINE_CLK_RST_REG_BIT_ENUM(LVL2_CLK_GATE_OVRD_ARC_CLK_OVR_ON, 19, OFF, ON);
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DEFINE_CLK_RST_REG_BIT_ENUM(LVL2_CLK_GATE_OVRD_TSEC_CLK_OVR_ON, 20, OFF, ON);
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DEFINE_CLK_RST_REG_BIT_ENUM(LVL2_CLK_GATE_OVRD_TSECB_CLK_OVR_ON, 21, OFF, ON);
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DEFINE_CLK_RST_REG_BIT_ENUM(LVL2_CLK_GATE_OVRD_ISPB_CLK_OVR_ON, 22, OFF, ON);
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DEFINE_CLK_RST_REG_BIT_ENUM(LVL2_CLK_GATE_OVRD_TZRAM_CLK_OVR_ON, 23, OFF, ON);
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DEFINE_CLK_RST_REG_BIT_ENUM(LVL2_CLK_GATE_OVRD_QSPI_CLK_OVR_ON, 24, OFF, ON);
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DEFINE_CLK_RST_REG_BIT_ENUM(LVL2_CLK_GATE_OVRD_A9AVP_CLK_OVR_ON, 26, OFF, ON);
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DEFINE_CLK_RST_REG_BIT_ENUM(LVL2_CLK_GATE_OVRD_MPCORE_MSELECT_CLK_OVR_ON, 27, OFF, ON);
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DEFINE_CLK_RST_REG_BIT_ENUM(LVL2_CLK_GATE_OVRD_SDMMC1_LEGACY_TMCLK_OVR_ON, 28, OFF, ON);
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DEFINE_CLK_RST_REG_BIT_ENUM(LVL2_CLK_GATE_OVRD_SDMMC2_LEGACY_TMCLK_OVR_ON, 29, OFF, ON);
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DEFINE_CLK_RST_REG_BIT_ENUM(LVL2_CLK_GATE_OVRD_SDMMC3_LEGACY_TMCLK_OVR_ON, 30, OFF, ON);
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DEFINE_CLK_RST_REG_BIT_ENUM(LVL2_CLK_GATE_OVRD_SDMMC4_LEGACY_TMCLK_OVR_ON, 31, OFF, ON);
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DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_I2C1_I2C1_CLK_SRC, 29, PLLP_OUT0, PLLC2_OUT0, PLLC_OUT0, PLLC4_OUT0, RESERVED4, PLLC4_OUT1, CLK_M, PLLC4_OUT2);
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DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_I2C5_I2C5_CLK_SRC, 29, PLLP_OUT0, PLLC2_OUT0, PLLC_OUT0, PLLC4_OUT0, RESERVED4, PLLC4_OUT1, CLK_M, PLLC4_OUT2);
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DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_UARTA_UARTA_CLK_SRC, 29, PLLP_OUT0, PLLC2_OUT0, PLLC_OUT0, PLLC4_OUT0, RESERVED4, PLLC4_OUT1, CLK_M, PLLC4_OUT2);
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DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_UARTB_UARTB_CLK_SRC, 29, PLLP_OUT0, PLLC2_OUT0, PLLC_OUT0, PLLC4_OUT0, RESERVED4, PLLC4_OUT1, CLK_M, PLLC4_OUT2);
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DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_UARTC_UARTC_CLK_SRC, 29, PLLP_OUT0, PLLC2_OUT0, PLLC_OUT0, PLLC4_OUT0, RESERVED4, PLLC4_OUT1, CLK_M, PLLC4_OUT2);
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DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_ACTMON_ACTMON_CLK_SRC, 29, PLLP_OUT0, PLLC2_OUT0, PLLC_OUT0, PLLC4_OUT0, CLK_S, PLLC4_OUT1, CLK_M, PLLC4_OUT2);
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DEFINE_CLK_RST_REG_BIT_ENUM(RST_DEV_L_CLR_CLR_COP_RST, 1, DISABLE, ENABLE);
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