mirror of
https://github.com/Atmosphere-NX/Atmosphere
synced 2024-12-24 21:51:15 +00:00
349 lines
9.9 KiB
C
349 lines
9.9 KiB
C
/*
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* Copyright (c) 2019 Atmosphère-NX
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "sysreg_traps.h"
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#include "synchronization.h"
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#include "sysreg.h"
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// For a32 mcr/mrc => a64 mrs
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static u32 convertMcrMrcIss(u32 *outCondition, bool *outCondValid, u32 *outShift, u32 a32Iss, u32 coproc, u32 el)
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{
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// NOTE: MCRR / MRRC do NOT map for the most part and need to be handled separately
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//u32 direction = a32Iss & 1;
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u32 opc2 = (a32Iss >> 17) & 7;
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u32 opc1 = (a32Iss >> 14) & 7;
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u32 CRn = (a32Iss >> 10) & 15;
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//u32 Rt = (a32Iss >> 5) & 31;
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u32 CRm = (a32Iss >> 1) & 15;
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*outCondValid = (a32Iss & BIT(24)) != 0;
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*outCondition = (a32Iss >> 20) & 15;
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*outShift = 0;
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u32 op0 = (16 - coproc) & 3;
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u32 op1;
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// Do NOT translate cp15, 0, c7-8 (Cache, and resp. TLB maintenance coproc regs) as they don't map to Aarch64
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if (coproc == 15 && (CRn == 7 || CRn == 8)) {
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return -2;
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}
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// A few special cases
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// We're probably missing some of them
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// opc1 Crn Crm opc2
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if (coproc == 15) {
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/* don't care // ACTLR2
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if (opc1 == 0 && CRn == 1 && CRm == 0 && opc2 == 3) {
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*outShift = 32;
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opc2 = 1;
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}*/
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// TTBCR2
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if (opc1 == 0 && CRn == 2 && CRm == 0 && opc2 == 3) {
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*outShift = 32;
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opc2 = 2;
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}
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/* don't care // ERX*2
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if (opc1 == 0 && CRn == 5 && CRm == 4 && opc2 >= 4) {
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*outShift = 32;
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opc2 &= ~4;
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}*/
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// DFSR -> ESR_EL1
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if (opc1 == 0 && CRn == 5 && CRm == 0 && opc2 == 0) {
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CRm = 2;
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}
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// IFAR -> high FAR_EL1
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if (opc1 == 0 && CRn == 6 && CRm == 0 && opc2 == 2) {
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opc2 = 0;
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*outShift = 32;
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}
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// MAIR1
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if (opc1 == 0 && CRn == 10 && CRm == 2 && opc2 == 1) {
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*outShift = 32;
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opc2 = 0;
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}
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// AMAIR1
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if (opc1 ==0 && CRn == 10 && CRm == 3 && opc2 == 1) {
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*outShift = 32;
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opc2 = 0;
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}
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}
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// The difficult part
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switch (opc1) {
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case SYSREG_OP1_AARCH32_AUTO: {
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switch (el) {
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case 0:
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op1 = SYSREG_OP1_EL0;
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break;
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case 1:
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op1 = SYSREG_OP1_AARCH64_EL1;
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break;
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case 2:
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op1 = SYSREG_OP1_EL2;
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break;
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case 3:
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op1 = SYSREG_OP1_EL3;
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break;
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default:
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return -1;
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}
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break;
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}
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case SYSREG_OP1_EL0:
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case SYSREG_OP1_EL2:
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case SYSREG_OP1_EL3:
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case SYSREG_OP1_CACHE:
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case SYSREG_OP1_CACHESZSEL:
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op1 = opc1;
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break;
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// We shouldn't even trap those to begin with.
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case SYSREG_OP1_AARCH32_JZL:
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default:
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return -1;
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}
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// Everything but op0 is at its correct place & only op1 needs to be replaced
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return (a32Iss & ~(MASK2(24, 20) | MASK2(16, 14) | MASK2(19, 17))) | (op0 << 20) | (opc2 << 17) | (op1 << 14);
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}
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static bool evaluateMcrMrcCondition(u64 spsr, u32 condition, bool condValid)
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{
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if (!condValid) {
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// Only T32 instructions can do that
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u32 it = spsrGetT32ItFlags(spsr);
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return it == 0 || spsrEvaluateConditionCode(spsr, it >> 4);
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} else {
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return spsrEvaluateConditionCode(spsr, condition);
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}
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}
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static void doSystemRegisterRwImpl(u64 *val, u32 iss)
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{
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u32 op0 = (iss >> 20) & 3;
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u32 op2 = (iss >> 17) & 7;
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u32 op1 = (iss >> 14) & 7;
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u32 CRn = (iss >> 10) & 15;
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//u32 Rt = (iss >> 5) & 31;
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u32 CRm = (iss >> 1) & 15;
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u32 dir = iss & 1;
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u32 codebuf[] = {
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0, // TBD
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0xD65F03C0, // ret
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};
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codebuf[0] = dir ? MAKE_MRS_FROM_FIELDS(op0, op1, CRn, CRm, op2, 0) : MAKE_MSR_FROM_FIELDS(op0, op1, CRn, CRm, op2, 0);
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__dsb_sy();
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__isb();
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*val = ((u64 (*)(u64))codebuf)(*val);
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}
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void doSystemRegisterRead(ExceptionStackFrame *frame, u32 iss, u32 reg1, u32 reg2)
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{
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// reg1 != reg2: mrrc/mcrr
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u64 val = 0;
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iss &= ~((0x1F << 5) | 1);
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doSystemRegisterRwImpl(&val, iss | 1);
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if (reg1 == reg2) {
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frame->x[reg1] = val;
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} else {
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if (reg1 != -1) {
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frame->x[reg1] = val & 0xFFFFFFFF;
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}
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if (reg2 != -1) {
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frame->x[reg2] = val >> 32;
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}
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}
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skipFaultingInstruction(frame, 4);
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}
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void doSystemRegisterWrite(ExceptionStackFrame *frame, u32 iss, u32 reg1, u32 reg2)
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{
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// reg1 != reg2: mrrc/mcrr
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u64 val = 0;
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iss &= ~((0x1F << 5) | 1);
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if (reg1 == -1 || reg2 == -1) {
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doSystemRegisterRwImpl(&val, iss | 1);
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if (reg1 == -1) {
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val = (frame->x[reg2] << 32) | (val & 0xFFFFFFFF);
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} else {
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val = ((val >> 32) << 32) | (frame->x[reg1] & 0xFFFFFFFF);
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}
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}
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else {
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if (reg1 != reg2) {
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val |= (frame->x[reg2] << 32) | (frame->x[reg1] & 0xFFFFFFFF);
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} else {
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val = frame->x[reg1];
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}
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}
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doSystemRegisterRwImpl(&val, iss);
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skipFaultingInstruction(frame, 4);
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}
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void handleMsrMrsTrap(ExceptionStackFrame *frame, ExceptionSyndromeRegister esr)
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{
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u32 iss = esr.iss;
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u32 reg = (iss >> 5) & 31;
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bool isRead = (iss & 1) != 0;
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if (isRead) {
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doSystemRegisterRead(frame, iss, reg, reg);
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} else {
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doSystemRegisterWrite(frame, iss, reg, reg);
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}
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}
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void handleMcrMrcTrap(ExceptionStackFrame *frame, ExceptionSyndromeRegister esr)
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{
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u32 condition;
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bool condValid;
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u32 coproc = esr.ec == Exception_CP14RTTrap ? 14 : 15;
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u32 shift = 0;
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// EL0 if User Mode else EL1
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u32 iss = convertMcrMrcIss(&condition, &condValid, &shift, esr.iss, coproc, (frame->spsr_el2 & 0xF) == 0 ? 0 : 1);
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if (esr.iss & BIT(31)) {
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// Error, we shouldn't have trapped those in first place anyway.
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skipFaultingInstruction(frame, 4);
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return;
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} else if (!evaluateMcrMrcCondition(frame->spsr_el2, condition, condValid)) {
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skipFaultingInstruction(frame, 4);
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return;
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}
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u32 reg = (iss >> 5) & 31;
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bool isRead = (iss & 1) != 0;
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u32 reg1 = shift == 32 ? -1 : reg;
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u32 reg2 = shift == 32 ? reg : -1;
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if (isRead) {
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doSystemRegisterRead(frame, iss, reg1, reg2);
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} else {
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doSystemRegisterRead(frame, iss, reg1, reg2);
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}
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}
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void handleMcrrMrrcTrap(ExceptionStackFrame *frame, ExceptionSyndromeRegister esr)
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{
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u32 iss = esr.iss;
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u32 coproc = esr.ec == Exception_CP14RRTTrap ? 14 : 15;
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bool cv = (iss & BIT(24)) != 0;
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u32 cond = (iss >> 20) & 0xF;
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u32 opc1 = (iss >> 16) & 0xF;
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u32 reg2 = (iss >> 10) & 0x1F;
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u32 reg1 = (iss >> 5) & 0x1F;
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u32 crm = (iss >> 1) & 0xF;
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u32 dir = iss & 1;
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if (!evaluateMcrMrcCondition(frame->spsr_el2, cond, cv)) {
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skipFaultingInstruction(frame, 4);
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return;
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}
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u32 sysregIss = -1;
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// No automatic conversion, handle what we potentiall trap
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if (coproc == 14) {
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if (crm == 1 && opc1 == 0) {
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sysregIss = ENCODE_SYSREG_ISS(MDRAR_EL1);
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} else if (crm == 2 && opc1 == 0) {
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// DBGSAR, deprecated in Armv8 and no reg mapping,
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// we won't handle it
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}
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} else {
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switch (crm) {
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case 2: {
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switch (opc1) {
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case 0:
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sysregIss = ENCODE_SYSREG_ISS(TTBR0_EL1);
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break;
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case 1:
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sysregIss = ENCODE_SYSREG_ISS(TTBR1_EL1);
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break;
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default:
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// other regs are el2 ttbr regs, not trapped here
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break;
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}
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break;
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}
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case 7:
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sysregIss = opc1 == 0 ? ENCODE_SYSREG_ISS(PAR_EL1) : -1;
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break;
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case 14: {
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switch (opc1) {
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case 0:
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sysregIss = ENCODE_SYSREG_ISS(CNTPCT_EL0);
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break;
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case 1:
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sysregIss = ENCODE_SYSREG_ISS(CNTVCT_EL0);
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break;
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case 2:
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sysregIss = ENCODE_SYSREG_ISS(CNTP_CVAL_EL0);
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break;
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case 3:
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sysregIss = ENCODE_SYSREG_ISS(CNTV_CVAL_EL0);
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break;
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case 4:
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sysregIss = ENCODE_SYSREG_ISS(CNTVOFF_EL2);
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break;
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case 6:
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sysregIss = ENCODE_SYSREG_ISS(CNTHP_CVAL_EL2);
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break;
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}
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}
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}
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}
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if (esr.iss & BIT(31)) {
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// Error, we shouldn't have trapped those in first place anyway.
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skipFaultingInstruction(frame, 4);
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return;
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}
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if (dir == 1) {
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doSystemRegisterRead(frame, sysregIss, reg1, reg2);
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} else {
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doSystemRegisterWrite(frame, sysregIss, reg1, reg2);
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}
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}
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void handleLdcStcTrap(ExceptionStackFrame *frame, ExceptionSyndromeRegister esr)
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{
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// Only used for DBGDTRRXint
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// Do not execute the read/writes
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skipFaultingInstruction(frame, esr.il == 0 ? 2 : 4);
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}
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