mirror of
https://github.com/Atmosphere-NX/Atmosphere
synced 2024-09-20 07:08:59 +00:00
180 lines
8 KiB
C
180 lines
8 KiB
C
#include <string.h>
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#include "utils.h"
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#include "mmu.h"
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#include "memory_map.h"
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#include "arm.h"
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#include "package2.h"
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#include "timers.h"
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#undef MAILBOX_NX_BOOTLOADER_BASE
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#undef TIMERS_BASE
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#define MAILBOX_NX_BOOTLOADER_BASE (MMIO_GET_DEVICE_PA(MMIO_DEVID_NXBOOTLOADER_MAILBOX))
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#define TIMERS_BASE (MMIO_GET_DEVICE_PA(MMIO_DEVID_TMRs_WDTs))
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extern const uint8_t __start_cold[];
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static void identity_map_all_mappings(uintptr_t *mmu_l1_tbl, uintptr_t *mmu_l3_tbl) {
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static const uintptr_t addrs[] = { TUPLE_FOLD_LEFT_0(EVAL(IDENTIY_MAPPING_ID_MAX), _MMAPID, COMMA) };
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static const size_t sizes[] = { TUPLE_FOLD_LEFT_1(EVAL(IDENTIY_MAPPING_ID_MAX), _MMAPID, COMMA) };
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static const uint64_t attribs[] = { TUPLE_FOLD_LEFT_2(EVAL(IDENTIY_MAPPING_ID_MAX), _MMAPID, COMMA) };
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static const uint64_t is_block[] = { TUPLE_FOLD_LEFT_3(EVAL(IDENTIY_MAPPING_ID_MAX), _MMAPID, COMMA) };
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for(size_t i = 0; i < IDENTIY_MAPPING_ID_MAX; i++) {
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identity_map_mapping(mmu_l1_tbl, mmu_l3_tbl, addrs[i], sizes[i], attribs[i], is_block[i]);
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}
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}
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static void mmio_map_all_devices(uintptr_t *mmu_l3_tbl) {
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static const uintptr_t pas[] = { TUPLE_FOLD_LEFT_0(EVAL(MMIO_DEVID_MAX), _MMAPDEV, COMMA) };
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static const size_t sizes[] = { TUPLE_FOLD_LEFT_1(EVAL(MMIO_DEVID_MAX), _MMAPDEV, COMMA) };
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static const bool is_secure[] = { TUPLE_FOLD_LEFT_2(EVAL(MMIO_DEVID_MAX), _MMAPDEV, COMMA) };
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for(size_t i = 0, offset = 0; i < MMIO_DEVID_MAX; i++) {
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mmio_map_device(mmu_l3_tbl, MMIO_BASE + offset, pas[i], sizes[i], is_secure[i]);
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offset += sizes[i];
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offset += 0x1000;
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}
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}
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static void lp0_entry_map_all_ram_segments(uintptr_t *mmu_l3_tbl) {
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static const uintptr_t pas[] = { TUPLE_FOLD_LEFT_0(EVAL(LP0_ENTRY_RAM_SEGMENT_ID_MAX), _MMAPLP0ES, COMMA) };
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static const size_t sizes[] = { TUPLE_FOLD_LEFT_1(EVAL(LP0_ENTRY_RAM_SEGMENT_ID_MAX), _MMAPLP0ES, COMMA) };
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static const uint64_t attribs[] = { TUPLE_FOLD_LEFT_2(EVAL(LP0_ENTRY_RAM_SEGMENT_ID_MAX), _MMAPLP0ES, COMMA) };
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for(size_t i = 0, offset = 0; i < LP0_ENTRY_RAM_SEGMENT_ID_MAX; i++) {
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lp0_entry_map_ram_segment(mmu_l3_tbl, LP0_ENTRY_RAM_SEGMENT_BASE + offset, pas[i], sizes[i], attribs[i]);
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offset += 0x10000;
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}
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}
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static void warmboot_map_all_ram_segments(uintptr_t *mmu_l3_tbl) {
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static const uintptr_t pas[] = { TUPLE_FOLD_LEFT_0(EVAL(WARMBOOT_RAM_SEGMENT_ID_MAX), _MMAPWBS, COMMA) };
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static const size_t sizes[] = { TUPLE_FOLD_LEFT_1(EVAL(WARMBOOT_RAM_SEGMENT_ID_MAX), _MMAPWBS, COMMA) };
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static const uint64_t attribs[] = { TUPLE_FOLD_LEFT_2(EVAL(WARMBOOT_RAM_SEGMENT_ID_MAX), _MMAPWBS, COMMA) };
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for(size_t i = 0, offset = 0; i < WARMBOOT_RAM_SEGMENT_ID_MAX; i++) {
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warmboot_map_ram_segment(mmu_l3_tbl, WARMBOOT_RAM_SEGMENT_BASE + offset, pas[i], sizes[i], attribs[i]);
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offset += sizes[i];
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}
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}
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static void tzram_map_all_segments(uintptr_t *mmu_l3_tbl) {
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static const uintptr_t offs[] = { TUPLE_FOLD_LEFT_0(EVAL(TZRAM_SEGMENT_ID_MAX), _MMAPTZS, COMMA) };
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static const size_t sizes[] = { TUPLE_FOLD_LEFT_1(EVAL(TZRAM_SEGMENT_ID_MAX), _MMAPTZS, COMMA) };
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static const size_t increments[] = { TUPLE_FOLD_LEFT_2(EVAL(TZRAM_SEGMENT_ID_MAX), _MMAPTZS, COMMA) };
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static const bool is_executable[] = { TUPLE_FOLD_LEFT_3(EVAL(TZRAM_SEGMENT_ID_MAX), _MMAPTZS, COMMA) };
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for(size_t i = 0, offset = 0; i < TZRAM_SEGMENT_ID_MAX; i++) {
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tzram_map_segment(mmu_l3_tbl, TZRAM_SEGMENT_BASE + offset, 0x7C010000ull + offs[i], sizes[i], is_executable[i]);
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offset += increments[i];
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}
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}
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static void configure_ttbls(void) {
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uintptr_t *mmu_l1_tbl = (uintptr_t *)(TZRAM_GET_SEGMENT_PA(TZRAM_SEGEMENT_ID_SECMON_EVT) + 0x800 - 64);
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uintptr_t *mmu_l2_tbl = (uintptr_t *)TZRAM_GET_SEGMENT_PA(TZRAM_SEGMENT_ID_L2_TRANSLATION_TABLE);
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uintptr_t *mmu_l3_tbl = (uintptr_t *)TZRAM_GET_SEGMENT_PA(TZRAM_SEGMENT_ID_L3_TRANSLATION_TABLE);
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mmu_init_table(mmu_l1_tbl, 64); /* 33-bit address space */
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mmu_init_table(mmu_l2_tbl, 4096);
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/*
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Nintendo uses the same L3 table for everything, but they make sure
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nothing clashes.
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*/
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mmu_init_table(mmu_l3_tbl, 4096);
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mmu_map_table(1, mmu_l1_tbl, 0x40000000, mmu_l2_tbl, 0);
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mmu_map_table(1, mmu_l1_tbl, 0x1C0000000, mmu_l2_tbl, 0);
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mmu_map_table(2, mmu_l2_tbl, 0x40000000, mmu_l3_tbl, 0);
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mmu_map_table(2, mmu_l2_tbl, 0x7C000000, mmu_l3_tbl, 0);
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mmu_map_table(2, mmu_l2_tbl, 0x1F0000000ull, mmu_l3_tbl, 0);
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identity_map_all_mappings(mmu_l1_tbl, mmu_l3_tbl);
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mmio_map_all_devices(mmu_l3_tbl);
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lp0_entry_map_all_ram_segments(mmu_l3_tbl);
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warmboot_map_all_ram_segments(mmu_l3_tbl);
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tzram_map_all_segments(mmu_l3_tbl);
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}
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static void translate_func_list(coldboot_crt0_reloc_list_t *reloc_list, boot_func_list_t *func_list, bool in_tzram) {
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coldboot_crt0_reloc_t *warmboot_crt0_reloc = &reloc_list->relocs[0];
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coldboot_crt0_reloc_t *main_reloc = &reloc_list->relocs[reloc_list->nb_relocs_pre_mmu_init];
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uintptr_t main_pa;
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if (in_tzram) {
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/* The main segment immediately follows the warmboot crt0 in TZRAM, in the same page. */
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main_pa = (uintptr_t)warmboot_crt0_reloc->vma | ((uintptr_t)main_reloc->vma & 0xFFF);
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} else {
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main_pa = reloc_list->reloc_base + main_reloc->reloc_offset;
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}
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for(size_t i = 0; i < func_list->nb_funcs; i++) {
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if(func_list->addrs[i] >= 0x1F0000000ull) {
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func_list->addrs[i] = main_pa + func_list->addrs[i] - (uintptr_t)main_reloc->vma;
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}
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}
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}
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static void do_relocation(const coldboot_crt0_reloc_list_t *reloc_list, size_t index) {
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uint64_t *p_vma = (uint64_t *)reloc_list->relocs[index].vma;
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const uint64_t *p_lma = (const uint64_t *)(reloc_list->reloc_base + reloc_list->relocs[index].reloc_offset);
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size_t size = reloc_list->relocs[index].end_vma - reloc_list->relocs[index].vma;
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for(size_t i = 0; i < size / 8; i++) {
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p_vma[i] = reloc_list->relocs[index].reloc_offset != 0 ? p_lma[i] : 0;
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}
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}
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uintptr_t get_coldboot_crt0_stack_address(void) {
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return TZRAM_GET_SEGMENT_PA(TZRAM_SEGMENT_ID_CORE3_STACK) + 0x800;
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}
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void coldboot_init(coldboot_crt0_reloc_list_t *reloc_list, boot_func_list_t *func_list, boot_func_list_t *func_list_warmboot) {
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MAILBOX_NX_SECMON_BOOT_TIME = TIMERUS_CNTR_1US_0;
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boot_func_list_t func_copy = *func_list;
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/* Custom approach */
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reloc_list->reloc_base = (uintptr_t)__start_cold;
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translate_func_list(reloc_list, func_list, false);
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/*
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From https://events.static.linuxfound.org/sites/events/files/slides/slides_17.pdf :
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Caches may write back dirty lines at any time:
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- To make space for new allocations
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- Even if MMU is off
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- Even if Cacheable accesses are disabled (caches are never 'off')
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It should be fine to clear that here and not before.
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*/
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func_list->funcs.flush_dcache_all();
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func_list->funcs.invalidate_icache_all();
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/* TODO: Set NX BOOTLOADER clock time field */
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/* This at least copies .warm_crt0 to its VMA. */
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for(size_t i = 0; i < reloc_list->nb_relocs_pre_mmu_init; i++) {
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do_relocation(reloc_list, i);
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}
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/* At this point, we can (and will) access functions located in .warm_crt0 */
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/* Initialize DMA controllers, and write to AHB_GIZMO_TZRAM. */
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/* TZRAM accesses should work normally after this point. */
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func_list->funcs.init_dma_controllers();
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configure_ttbls();
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func_list->funcs.set_memory_registers_enable_mmu();
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/* Copy or clear the remaining sections */
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for(size_t i = 0; i < reloc_list->nb_relocs_post_mmu_init; i++) {
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do_relocation(reloc_list, reloc_list->nb_relocs_pre_mmu_init + i);
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}
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func_list->funcs.flush_dcache_all();
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func_list->funcs.invalidate_icache_all();
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/* At this point we can access all the mapped segments (all other functions, data...) normally */
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*func_list_warmboot = func_copy;
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translate_func_list(reloc_list, func_list_warmboot, true);
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}
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