mirror of
https://github.com/Atmosphere-NX/Atmosphere
synced 2024-05-19 01:30:46 +00:00
521 lines
20 KiB
C++
521 lines
20 KiB
C++
/*
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* Copyright (c) Atmosphère-NX
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <exosphere.hpp>
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#include "fuse_registers.hpp"
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namespace ams::fuse {
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namespace {
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static constexpr SocType SocType_CommonInternal = static_cast<SocType>(-1);
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static_assert(SocType_CommonInternal != SocType_Erista);
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static_assert(SocType_CommonInternal != SocType_Mariko);
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constinit SocType g_soc_type = SocType_CommonInternal;
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struct BypassEntry {
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u32 offset;
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u32 value;
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};
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struct OdmWord2 {
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using DeviceUniqueKeyGeneration = util::BitPack32::Field<0, 5, int>;
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using Reserved = util::BitPack32::Field<5, 27, int>;
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};
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struct OdmWord4 {
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using HardwareState1 = util::BitPack32::Field<0, 2, int>;
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using HardwareType1 = util::BitPack32::Field<HardwareState1::Next, 1, int>;
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using DramId1 = util::BitPack32::Field<HardwareType1::Next, 5, int>;
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using HardwareType2 = util::BitPack32::Field<DramId1::Next, 1, int>;
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using HardwareState2 = util::BitPack32::Field<HardwareType2::Next, 1, int>;
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using RetailInteractiveDisplayState = util::BitPack32::Field<HardwareState2::Next, 1, int>;
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using FormatVersion = util::BitPack32::Field<RetailInteractiveDisplayState::Next, 1, int>;
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using DramId2 = util::BitPack32::Field<FormatVersion::Next, 3, int>;
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using Reserved = util::BitPack32::Field<DramId2::Next, 1, int>;
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using HardwareType3 = util::BitPack32::Field<Reserved::Next, 4, int>;
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};
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struct OdmWord28 {
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using Regulator = util::BitPack32::Field<0, 1, int>;
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using Reserved = util::BitPack32::Field<1, 31, int>;
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};
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constexpr ALWAYS_INLINE int GetHardwareStateValue(const util::BitPack32 odm_word4) {
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constexpr auto HardwareState1Shift = 0;
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constexpr auto HardwareState2Shift = OdmWord4::HardwareState1::Count + HardwareState1Shift;
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return (odm_word4.Get<OdmWord4::HardwareState1>() << HardwareState1Shift) |
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(odm_word4.Get<OdmWord4::HardwareState2>() << HardwareState2Shift);
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}
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constexpr ALWAYS_INLINE int GetHardwareTypeValue(const util::BitPack32 odm_word4) {
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constexpr auto HardwareType1Shift = 0;
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constexpr auto HardwareType2Shift = OdmWord4::HardwareType1::Count + HardwareType1Shift;
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constexpr auto HardwareType3Shift = OdmWord4::HardwareType2::Count + HardwareType2Shift;
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return (odm_word4.Get<OdmWord4::HardwareType1>() << HardwareType1Shift) |
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(odm_word4.Get<OdmWord4::HardwareType2>() << HardwareType2Shift) |
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(odm_word4.Get<OdmWord4::HardwareType3>() << HardwareType3Shift);
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}
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constexpr ALWAYS_INLINE int GetDramIdValue(const util::BitPack32 odm_word4) {
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constexpr auto DramId1Shift = 0;
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constexpr auto DramId2Shift = OdmWord4::DramId1::Count + DramId1Shift;
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return (odm_word4.Get<OdmWord4::DramId1>() << DramId1Shift) |
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(odm_word4.Get<OdmWord4::DramId2>() << DramId2Shift);
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}
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constinit uintptr_t g_register_address = secmon::MemoryRegionPhysicalDeviceFuses.GetAddress();
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constinit bool g_checked_for_rcm_bug_patch = false;
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constinit bool g_has_rcm_bug_patch = false;
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ALWAYS_INLINE volatile FuseRegisterRegion *GetRegisterRegion() {
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return reinterpret_cast<volatile FuseRegisterRegion *>(g_register_address);
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}
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ALWAYS_INLINE volatile FuseRegisters &GetRegisters() {
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return GetRegisterRegion()->fuse;
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}
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ALWAYS_INLINE volatile FuseChipRegistersCommon &GetChipRegistersCommon() {
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return GetRegisterRegion()->chip_common;
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}
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ALWAYS_INLINE volatile FuseChipRegistersErista &GetChipRegistersErista() {
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return GetRegisterRegion()->chip_erista;
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}
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ALWAYS_INLINE volatile FuseChipRegistersMariko &GetChipRegistersMariko() {
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return GetRegisterRegion()->chip_mariko;
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}
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bool IsIdle() {
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return reg::HasValue(GetRegisters().FUSE_FUSECTRL, FUSE_REG_BITS_ENUM(FUSECTRL_STATE, IDLE));
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}
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void WaitForIdle() {
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while (!IsIdle()) { /* ... */ }
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}
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u32 GetOdmWordImpl(int index, fuse::SocType soc_type) {
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if (index < 8) {
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volatile auto &chip = GetChipRegistersCommon();
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return chip.FUSE_RESERVED_ODM_0[index - 0];
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} else if (soc_type == SocType_Mariko) {
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volatile auto &chip = GetChipRegistersMariko();
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if (index < 22) {
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return chip.FUSE_RESERVED_ODM_8[index - 8];
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} else if (index < 25) {
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return chip.FUSE_RESERVED_ODM_22[index - 22];
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} else if (index < 26) {
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return chip.FUSE_RESERVED_ODM_25[index - 25];
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} else if (index < 29) {
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return chip.FUSE_RESERVED_ODM_26[index - 26];
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} else if (index < 30) {
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return chip.FUSE_RESERVED_ODM_29[index - 29];
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}
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}
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AMS_ABORT("Invalid ODM fuse read");
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}
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u32 GetCommonOdmWord(int index) {
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return GetOdmWordImpl(index, SocType_CommonInternal);
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}
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bool IsNewFuseFormat() {
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/* On mariko, this should always be true. */
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if (GetSocType() != SocType_Erista) {
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return true;
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}
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/* Require that the format version be non-zero in odm4. */
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if (util::BitPack32{GetCommonOdmWord(4)}.Get<OdmWord4::FormatVersion>() == 0) {
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return false;
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}
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/* Check that odm word 0/1 are fused with the magic values. */
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constexpr u32 NewFuseFormatMagic0 = 0x8E61ECAE;
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constexpr u32 NewFuseFormatMagic1 = 0xF2BA3BB2;
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const u32 w0 = GetCommonOdmWord(0);
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const u32 w1 = GetCommonOdmWord(1);
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return w0 == NewFuseFormatMagic0 && w1 == NewFuseFormatMagic1;
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}
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constexpr u32 CompressLotCode(u32 lot0) {
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constexpr int Radix = 36;
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constexpr int Count = 5;
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constexpr int Width = 6;
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constexpr u32 Mask = (1u << Width) - 1;
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u32 compressed = 0;
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for (int i = Count - 1; i >= 0; --i) {
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compressed *= Radix;
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compressed += (lot0 >> (i * Width)) & Mask;
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}
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return compressed;
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}
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constexpr const TargetFirmware FuseVersionIncrementFirmwares[] = {
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TargetFirmware_18_0_0,
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TargetFirmware_17_0_0,
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TargetFirmware_16_0_0,
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TargetFirmware_15_0_0,
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TargetFirmware_13_2_1,
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TargetFirmware_12_0_2,
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TargetFirmware_11_0_0,
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TargetFirmware_10_0_0,
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TargetFirmware_9_1_0,
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TargetFirmware_9_0_0,
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TargetFirmware_8_1_0,
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TargetFirmware_7_0_0,
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TargetFirmware_6_2_0,
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TargetFirmware_6_0_0,
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TargetFirmware_5_0_0,
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TargetFirmware_4_0_0,
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TargetFirmware_3_0_2,
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TargetFirmware_3_0_0,
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TargetFirmware_2_0_0,
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TargetFirmware_1_0_0,
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};
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constexpr inline int NumFuseIncrements = util::size(FuseVersionIncrementFirmwares);
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constexpr const BypassEntry FuseBypassEntries[] = {
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/* Don't configure any fuse bypass entries. */
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};
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constexpr inline int NumFuseBypassEntries = util::size(FuseBypassEntries);
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/* Verify that the fuse version increment list is sorted. */
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static_assert([] {
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for (size_t i = 0; i < util::size(FuseVersionIncrementFirmwares) - 1; ++i) {
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if (FuseVersionIncrementFirmwares[i] <= FuseVersionIncrementFirmwares[i + 1]) {
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return false;
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}
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}
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return true;
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}());
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constexpr int GetExpectedFuseVersionImpl(TargetFirmware target_fw) {
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for (int i = 0; i < NumFuseIncrements; ++i) {
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if (target_fw >= FuseVersionIncrementFirmwares[i]) {
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return NumFuseIncrements - i;
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}
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}
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return 0;
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}
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static_assert(GetExpectedFuseVersionImpl(TargetFirmware_11_0_0) == 14);
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static_assert(GetExpectedFuseVersionImpl(TargetFirmware_1_0_0) == 1);
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static_assert(GetExpectedFuseVersionImpl(static_cast<TargetFirmware>(0)) == 0);
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}
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void SetRegisterAddress(uintptr_t address) {
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g_register_address = address;
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}
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void SetWriteSecureOnly() {
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reg::Write(GetRegisters().FUSE_PRIVATEKEYDISABLE, FUSE_REG_BITS_ENUM(PRIVATEKEYDISABLE_TZ_STICKY_BIT_VAL, KEY_INVISIBLE));
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}
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void Lockout() {
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reg::Write(GetRegisters().FUSE_DISABLEREGPROGRAM, FUSE_REG_BITS_ENUM(DISABLEREGPROGRAM_VAL, ENABLE));
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}
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u32 ReadWord(int address) {
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/* Require that the fuse array be idle. */
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AMS_ABORT_UNLESS(IsIdle());
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/* Get the registers. */
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volatile auto &FUSE = GetRegisters();
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/* Write the address to read. */
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reg::Write(FUSE.FUSE_FUSEADDR, address);
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/* Set control to read. */
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reg::ReadWrite(FUSE.FUSE_FUSECTRL, FUSE_REG_BITS_ENUM(FUSECTRL_CMD, READ));
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/* Wait 1 us. */
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util::WaitMicroSeconds(1);
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/* Wait for the array to be idle. */
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WaitForIdle();
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return reg::Read(FUSE.FUSE_FUSERDATA);
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}
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u32 GetOdmWord(int index) {
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return GetOdmWordImpl(index, GetSocType());
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}
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void GetEcid(br::BootEcid *out) {
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/* Get the registers. */
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volatile auto &chip = GetChipRegistersCommon();
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/* Read the ecid components. */
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const u32 vendor = reg::Read(chip.FUSE_OPT_VENDOR_CODE) & ((1u << 4) - 1);
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const u32 fab = reg::Read(chip.FUSE_OPT_FAB_CODE) & ((1u << 6) - 1);
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const u32 lot0 = reg::Read(chip.FUSE_OPT_LOT_CODE_0) /* all 32 bits */ ;
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const u32 lot1 = reg::Read(chip.FUSE_OPT_LOT_CODE_1) & ((1u << 28) - 1);
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const u32 wafer = reg::Read(chip.FUSE_OPT_WAFER_ID) & ((1u << 6) - 1);
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const u32 x_coord = reg::Read(chip.FUSE_OPT_X_COORDINATE) & ((1u << 9) - 1);
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const u32 y_coord = reg::Read(chip.FUSE_OPT_Y_COORDINATE) & ((1u << 9) - 1);
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const u32 reserved = reg::Read(chip.FUSE_OPT_OPS_RESERVED) & ((1u << 6) - 1);
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/* Clear the output. */
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util::ClearMemory(out, sizeof(*out));
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/* Copy the component bits. */
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out->ecid[0] = static_cast<u32>((lot1 << 30) | (wafer << 24) | (x_coord << 15) | (y_coord << 6) | (reserved));
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out->ecid[1] = static_cast<u32>((lot0 << 26) | (lot1 >> 2));
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out->ecid[2] = static_cast<u32>((fab << 26) | (lot0 >> 6));
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out->ecid[3] = static_cast<u32>(vendor);
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}
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u64 GetDeviceId() {
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/* Get the registers. */
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volatile auto &chip = GetChipRegistersCommon();
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/* Read the device id components. */
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/* NOTE: Device ID is "basically" just an alternate encoding of Ecid. */
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/* It elides lot1 (and compresses lot0), but this is fine because */
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/* lot1 is fixed-value for all fused devices. */
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const u64 fab = reg::Read(chip.FUSE_OPT_FAB_CODE) & ((1u << 6) - 1);
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const u32 lot0 = reg::Read(chip.FUSE_OPT_LOT_CODE_0) /* all 32 bits */ ;
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const u64 wafer = reg::Read(chip.FUSE_OPT_WAFER_ID) & ((1u << 6) - 1);
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const u64 x_coord = reg::Read(chip.FUSE_OPT_X_COORDINATE) & ((1u << 9) - 1);
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const u64 y_coord = reg::Read(chip.FUSE_OPT_Y_COORDINATE) & ((1u << 9) - 1);
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/* Compress lot0 down from 32-bits to 26. */
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const u64 clot0 = CompressLotCode(lot0) & ((1u << 26) - 1);
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return (y_coord << 0) |
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(x_coord << 9) |
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(wafer << 18) |
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(clot0 << 24) |
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(fab << 50);
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}
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DramId GetDramId() {
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/* Get the value. */
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return static_cast<DramId>(GetDramIdValue(util::BitPack32{GetCommonOdmWord(4)}));
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}
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HardwareType GetHardwareType() {
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/* Read the odm word. */
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const util::BitPack32 odm_word4 = { GetCommonOdmWord(4) };
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/* Get the value. */
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const auto value = GetHardwareTypeValue(odm_word4);
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switch (value) {
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case 0x01: return HardwareType_Icosa;
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case 0x02: return (true /* TODO: GetSocType() == SocType_Mariko */) ? HardwareType_Calcio : HardwareType_Copper;
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case 0x04: return HardwareType_Iowa;
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case 0x08: return HardwareType_Hoag;
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case 0x10: return HardwareType_Aula;
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default: return HardwareType_Undefined;
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}
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}
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HardwareState GetHardwareState() {
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/* Read the odm word. */
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const util::BitPack32 odm_word4 = { GetCommonOdmWord(4) };
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/* Get the value. */
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const auto value = GetHardwareStateValue(odm_word4);
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switch (value) {
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case 3: return HardwareState_Development;
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case 4: return HardwareState_Production;
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default: return HardwareState_Undefined;
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}
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}
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PatchVersion GetPatchVersion() {
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const auto patch_version = reg::Read(GetChipRegistersCommon().FUSE_SOC_SPEEDO_1_CALIB);
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return static_cast<PatchVersion>(static_cast<int>(GetSocType() << 12) | patch_version);
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}
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RetailInteractiveDisplayState GetRetailInteractiveDisplayState() {
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return static_cast<RetailInteractiveDisplayState>(util::BitPack32{GetCommonOdmWord(4)}.Get<OdmWord4::RetailInteractiveDisplayState>());
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}
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pmic::Regulator GetRegulator() {
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if (GetSocType() == SocType_Mariko) {
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/* Read the odm word. */
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const util::BitPack32 odm_word28 = { GetOdmWordImpl(28, SocType_Mariko) };
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return static_cast<pmic::Regulator>(odm_word28.Get<OdmWord28::Regulator>() + 1);
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} else /* if (GetSocType() == SocType_Erista) */ {
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return pmic::Regulator_Erista_Max77621;
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}
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}
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int GetDeviceUniqueKeyGeneration() {
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if (IsNewFuseFormat()) {
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return util::BitPack32{GetCommonOdmWord(2)}.Get<OdmWord2::DeviceUniqueKeyGeneration>();
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} else {
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return 0;
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}
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}
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SocType GetSocType() {
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if (AMS_LIKELY(g_soc_type != SocType_CommonInternal)) {
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return g_soc_type;
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} else {
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switch (GetHardwareType()) {
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case HardwareType_Icosa:
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case HardwareType_Copper:
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g_soc_type = SocType_Erista;
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break;
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case HardwareType_Iowa:
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case HardwareType_Hoag:
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case HardwareType_Calcio:
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case HardwareType_Aula:
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g_soc_type = SocType_Mariko;
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break;
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default:
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g_soc_type = SocType_Undefined;
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break;
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}
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return g_soc_type;
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}
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}
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int GetExpectedFuseVersion(TargetFirmware target_fw) {
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return GetExpectedFuseVersionImpl(target_fw);
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}
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int GetFuseVersion() {
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return util::PopCount(GetCommonOdmWord(7));
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}
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bool HasRcmVulnerabilityPatch() {
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/* Only check for RCM bug patch once, and cache our result. */
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if (!g_checked_for_rcm_bug_patch) {
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do {
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/* Mariko units are necessarily patched. */
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if (fuse::GetSocType() != SocType_Erista) {
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g_has_rcm_bug_patch = true;
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break;
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}
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/* Some patched units use XUSB in RCM. */
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if (reg::Read(GetChipRegistersCommon().FUSE_RESERVED_SW) & 0x80) {
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g_has_rcm_bug_patch = true;
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break;
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}
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/* Other units have a proper ipatch instead. */
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u32 word_count = reg::Read(GetChipRegistersCommon().FUSE_FIRST_BOOTROM_PATCH_SIZE) & 0x7F;
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u32 word_addr = 191;
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while (word_count && !g_has_rcm_bug_patch) {
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u32 word0 = ReadWord(word_addr);
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u32 ipatch_count = (word0 >> 16) & 0xF;
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for (u32 i = 0; i < ipatch_count && !g_has_rcm_bug_patch; ++i) {
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u32 word = ReadWord(word_addr - (i + 1));
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u32 addr = (word >> 16) * 2;
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if (addr == 0x769a) {
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g_has_rcm_bug_patch = true;
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break;
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}
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}
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word_addr -= word_count;
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word_count = word0 >> 25;
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}
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} while (0);
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g_checked_for_rcm_bug_patch = true;
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}
|
|
|
|
return g_has_rcm_bug_patch;
|
|
}
|
|
|
|
bool IsOdmProductionMode() {
|
|
return reg::HasValue(GetChipRegistersCommon().FUSE_SECURITY_MODE, FUSE_REG_BITS_ENUM(SECURITY_MODE_SECURITY_MODE, ENABLED));
|
|
}
|
|
|
|
bool GetSecureBootKey(void *dst) {
|
|
/* Get the sbk from fuse data. */
|
|
bool valid = false;
|
|
for (size_t i = 0; i < 4; ++i) {
|
|
const u32 key_word = GetChipRegistersCommon().FUSE_PRIVATE_KEY[i];
|
|
|
|
static_cast<u32 *>(dst)[i] = key_word;
|
|
valid |= key_word != 0xFFFFFFFF;
|
|
}
|
|
|
|
return valid;
|
|
}
|
|
|
|
void ConfigureFuseBypass() {
|
|
/* Make the fuse registers visible. */
|
|
clkrst::SetFuseVisibility(true);
|
|
|
|
/* Only perform bypass configuration if fuse programming is allowed. */
|
|
if (!reg::HasValue(GetRegisters().FUSE_DISABLEREGPROGRAM, FUSE_REG_BITS_ENUM(DISABLEREGPROGRAM_VAL, DISABLE))) {
|
|
return;
|
|
}
|
|
|
|
/* Enable software writes to fuses. */
|
|
reg::ReadWrite(GetRegisters().FUSE_WRITE_ACCESS_SW, FUSE_REG_BITS_ENUM(WRITE_ACCESS_SW_CTRL, READWRITE),
|
|
FUSE_REG_BITS_ENUM(WRITE_ACCESS_SW_STATUS, WRITE));
|
|
|
|
/* Enable fuse bypass. */
|
|
reg::Write(GetRegisters().FUSE_FUSEBYPASS, FUSE_REG_BITS_ENUM(FUSEBYPASS_VAL, ENABLE));
|
|
|
|
/* Override fuses. */
|
|
for (const auto &entry : FuseBypassEntries) {
|
|
reg::Write(g_register_address + entry.offset, entry.value);
|
|
}
|
|
|
|
/* Disable software writes to fuses. */
|
|
reg::ReadWrite(GetRegisters().FUSE_WRITE_ACCESS_SW, FUSE_REG_BITS_ENUM(WRITE_ACCESS_SW_CTRL, READONLY));
|
|
|
|
/* NOTE: Here, NVidia almost certainly intends to *disable* fuse bypass, but they write enable instead... */
|
|
reg::Write(GetRegisters().FUSE_FUSEBYPASS, FUSE_REG_BITS_ENUM(FUSEBYPASS_VAL, ENABLE));
|
|
|
|
/* NOTE: Here, NVidia intends to disable fuse programming. However, they fuck up -- and *clear* the disable bit. */
|
|
/* It should be noted that this is a sticky bit, and thus software clears have no effect. */
|
|
reg::ReadWrite(GetRegisters().FUSE_DISABLEREGPROGRAM, FUSE_REG_BITS_ENUM(DISABLEREGPROGRAM_VAL, DISABLE));
|
|
|
|
/* Configure FUSE_PRIVATEKEYDISABLE_TZ_STICKY_BIT. */
|
|
constexpr const uintptr_t PMC = secmon::MemoryRegionPhysicalDevicePmc.GetAddress();
|
|
const bool key_invisible = reg::HasValue(PMC + APBDEV_PMC_SECURE_SCRATCH21, FUSE_REG_BITS_ENUM(PRIVATEKEYDISABLE_TZ_STICKY_BIT_VAL, KEY_INVISIBLE));
|
|
|
|
reg::ReadWrite(GetRegisters().FUSE_PRIVATEKEYDISABLE, FUSE_REG_BITS_ENUM_SEL(PRIVATEKEYDISABLE_TZ_STICKY_BIT_VAL, key_invisible, KEY_INVISIBLE, KEY_VISIBLE));
|
|
|
|
/* Write-lock PMC_SECURE_SCRATCH21. */
|
|
reg::ReadWrite(PMC + APBDEV_PMC_SEC_DISABLE2, PMC_REG_BITS_ENUM(SEC_DISABLE2_WRITE21, ON));
|
|
}
|
|
|
|
}
|