mirror of
https://github.com/Atmosphere-NX/Atmosphere
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654 lines
24 KiB
ArmAsm
654 lines
24 KiB
ArmAsm
/*
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* Copyright (c) 2018-2020 Atmosphère-NX
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <mesosphere/kern_select_assembly_offsets.h>
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#if defined(MESOSPHERE_ENABLE_HARDWARE_SINGLE_STEP)
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.macro disable_single_step, scratch
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/* Clear MDSCR_EL1.SS. */
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mrs \scratch, mdscr_el1
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bic \scratch, \scratch, #1
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msr mdscr_el1, \scratch
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.endm
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.macro check_enable_single_step, scratch1, scratch2, spsr_value
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/* Check if single-step is requested. */
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ldrb \scratch1, [sp, #(EXCEPTION_CONTEXT_SIZE + THREAD_STACK_PARAMETERS_IS_SINGLE_STEP)]
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tbz \scratch1, #0, .skip_single_step\@
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/* If single-step is requested, enable the single-step machine by setting MDSCR_EL1.SS. */
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mrs \scratch2, mdscr_el1
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orr \scratch2, \scratch2, #1
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msr mdscr_el1, \scratch2
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/* Since we're returning from an exception, set SPSR.SS so we actually advance an instruction. */
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orr \spsr_value, \spsr_value, #(1 << 21)
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isb
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.skip_single_step\@:
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.endm
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#else
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.macro disable_single_step, scratch
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.endm
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.macro check_enable_single_step, scratch1, scratch2, spsr_value
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.endm
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#endif
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/* ams::kern::arch::arm64::EL1IrqExceptionHandler() */
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.section .text._ZN3ams4kern4arch5arm6422EL1IrqExceptionHandlerEv, "ax", %progbits
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.global _ZN3ams4kern4arch5arm6422EL1IrqExceptionHandlerEv
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.type _ZN3ams4kern4arch5arm6422EL1IrqExceptionHandlerEv, %function
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_ZN3ams4kern4arch5arm6422EL1IrqExceptionHandlerEv:
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/* Save registers that need saving. */
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sub sp, sp, #(8 * 24)
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stp x0, x1, [sp, #(8 * 0)]
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stp x2, x3, [sp, #(8 * 2)]
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stp x4, x5, [sp, #(8 * 4)]
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stp x6, x7, [sp, #(8 * 6)]
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stp x8, x9, [sp, #(8 * 8)]
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stp x10, x11, [sp, #(8 * 10)]
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stp x12, x13, [sp, #(8 * 12)]
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stp x14, x15, [sp, #(8 * 14)]
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stp x16, x17, [sp, #(8 * 16)]
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stp x19, x20, [sp, #(8 * 18)]
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stp x21, x30, [sp, #(8 * 20)]
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mrs x19, sp_el0
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mrs x20, elr_el1
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mrs x21, spsr_el1
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mov w21, w21
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/* Invoke KInterruptManager::HandleInterrupt(bool user_mode). */
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mov x0, #0
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bl _ZN3ams4kern4arch5arm6417KInterruptManager15HandleInterruptEb
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/* Restore registers that we saved. */
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msr sp_el0, x19
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msr elr_el1, x20
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msr spsr_el1, x21
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ldp x0, x1, [sp, #(8 * 0)]
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ldp x2, x3, [sp, #(8 * 2)]
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ldp x4, x5, [sp, #(8 * 4)]
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ldp x6, x7, [sp, #(8 * 6)]
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ldp x8, x9, [sp, #(8 * 8)]
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ldp x10, x11, [sp, #(8 * 10)]
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ldp x12, x13, [sp, #(8 * 12)]
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ldp x14, x15, [sp, #(8 * 14)]
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ldp x16, x17, [sp, #(8 * 16)]
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ldp x19, x20, [sp, #(8 * 18)]
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ldp x21, x30, [sp, #(8 * 20)]
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add sp, sp, #(8 * 24)
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/* Return from the exception. */
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eret
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/* ams::kern::arch::arm64::EL0IrqExceptionHandler() */
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.section .text._ZN3ams4kern4arch5arm6422EL0IrqExceptionHandlerEv, "ax", %progbits
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.global _ZN3ams4kern4arch5arm6422EL0IrqExceptionHandlerEv
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.type _ZN3ams4kern4arch5arm6422EL0IrqExceptionHandlerEv, %function
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_ZN3ams4kern4arch5arm6422EL0IrqExceptionHandlerEv:
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/* Save registers that need saving. */
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sub sp, sp, #(EXCEPTION_CONTEXT_SIZE)
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stp x0, x1, [sp, #(EXCEPTION_CONTEXT_X0_X1)]
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stp x2, x3, [sp, #(EXCEPTION_CONTEXT_X2_X3)]
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stp x4, x5, [sp, #(EXCEPTION_CONTEXT_X4_X5)]
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stp x6, x7, [sp, #(EXCEPTION_CONTEXT_X6_X7)]
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stp x8, x9, [sp, #(EXCEPTION_CONTEXT_X8_X9)]
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stp x10, x11, [sp, #(EXCEPTION_CONTEXT_X10_X11)]
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stp x12, x13, [sp, #(EXCEPTION_CONTEXT_X12_X13)]
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stp x14, x15, [sp, #(EXCEPTION_CONTEXT_X14_X15)]
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stp x16, x17, [sp, #(EXCEPTION_CONTEXT_X16_X17)]
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stp x18, x19, [sp, #(EXCEPTION_CONTEXT_X18_X19)]
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stp x20, x21, [sp, #(EXCEPTION_CONTEXT_X20_X21)]
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stp x22, x23, [sp, #(EXCEPTION_CONTEXT_X22_X23)]
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stp x24, x25, [sp, #(EXCEPTION_CONTEXT_X24_X25)]
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stp x26, x27, [sp, #(EXCEPTION_CONTEXT_X26_X27)]
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stp x28, x29, [sp, #(EXCEPTION_CONTEXT_X28_X29)]
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mrs x20, sp_el0
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mrs x21, elr_el1
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mrs x22, spsr_el1
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mrs x23, tpidr_el0
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mov w22, w22
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stp x30, x20, [sp, #(EXCEPTION_CONTEXT_X30_SP)]
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stp x21, x22, [sp, #(EXCEPTION_CONTEXT_PC_PSR)]
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str x23, [sp, #(EXCEPTION_CONTEXT_TPIDR)]
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disable_single_step x0
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/* Invoke KInterruptManager::HandleInterrupt(bool user_mode). */
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ldr x18, [sp, #(EXCEPTION_CONTEXT_SIZE + THREAD_STACK_PARAMETERS_CUR_THREAD)]
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mov x0, #1
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bl _ZN3ams4kern4arch5arm6417KInterruptManager15HandleInterruptEb
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/* Restore state from the context. */
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ldp x30, x20, [sp, #(EXCEPTION_CONTEXT_X30_SP)]
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ldp x21, x22, [sp, #(EXCEPTION_CONTEXT_PC_PSR)]
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ldr x23, [sp, #(EXCEPTION_CONTEXT_TPIDR)]
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check_enable_single_step w0, x0, x22
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msr sp_el0, x20
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msr elr_el1, x21
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msr spsr_el1, x22
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msr tpidr_el0, x23
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ldp x0, x1, [sp, #(EXCEPTION_CONTEXT_X0_X1)]
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ldp x2, x3, [sp, #(EXCEPTION_CONTEXT_X2_X3)]
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ldp x4, x5, [sp, #(EXCEPTION_CONTEXT_X4_X5)]
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ldp x6, x7, [sp, #(EXCEPTION_CONTEXT_X6_X7)]
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ldp x8, x9, [sp, #(EXCEPTION_CONTEXT_X8_X9)]
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ldp x10, x11, [sp, #(EXCEPTION_CONTEXT_X10_X11)]
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ldp x12, x13, [sp, #(EXCEPTION_CONTEXT_X12_X13)]
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ldp x14, x15, [sp, #(EXCEPTION_CONTEXT_X14_X15)]
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ldp x16, x17, [sp, #(EXCEPTION_CONTEXT_X16_X17)]
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ldp x18, x19, [sp, #(EXCEPTION_CONTEXT_X18_X19)]
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ldp x20, x21, [sp, #(EXCEPTION_CONTEXT_X20_X21)]
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ldp x22, x23, [sp, #(EXCEPTION_CONTEXT_X22_X23)]
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ldp x24, x25, [sp, #(EXCEPTION_CONTEXT_X24_X25)]
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ldp x26, x27, [sp, #(EXCEPTION_CONTEXT_X26_X27)]
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ldp x28, x29, [sp, #(EXCEPTION_CONTEXT_X28_X29)]
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add sp, sp, #(EXCEPTION_CONTEXT_SIZE)
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/* Return from the exception. */
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eret
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/* ams::kern::arch::arm64::EL0SynchronousExceptionHandler() */
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.section .text._ZN3ams4kern4arch5arm6430EL0SynchronousExceptionHandlerEv, "ax", %progbits
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.global _ZN3ams4kern4arch5arm6430EL0SynchronousExceptionHandlerEv
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.type _ZN3ams4kern4arch5arm6430EL0SynchronousExceptionHandlerEv, %function
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_ZN3ams4kern4arch5arm6430EL0SynchronousExceptionHandlerEv:
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/* Save x16 and x17, so that we can use them as scratch. */
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stp x16, x17, [sp, #-16]!
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/* Get and parse the exception syndrome register. */
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mrs x16, esr_el1
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lsr x17, x16, #0x1a
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/* Is this an aarch32 SVC? */
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cmp x17, #0x11
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b.eq 2f
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/* Is this an aarch64 SVC? */
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cmp x17, #0x15
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b.eq 3f
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/* Is this an FPU error? */
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cmp x17, #0x7
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b.eq 4f
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/* Is this a data abort? */
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cmp x17, #0x24
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b.eq 5f
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/* Is this an instruction abort? */
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cmp x17, #0x20
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b.eq 5f
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1: /* The exception is not a data abort or instruction abort caused by a TLB conflict. */
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/* It is also not an SVC or an FPU exception. Handle it generically! */
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/* Restore x16 and x17. */
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ldp x16, x17, [sp], 16
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/* Create a KExceptionContext to pass to HandleException. */
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sub sp, sp, #(EXCEPTION_CONTEXT_SIZE)
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stp x0, x1, [sp, #(EXCEPTION_CONTEXT_X0_X1)]
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stp x2, x3, [sp, #(EXCEPTION_CONTEXT_X2_X3)]
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stp x4, x5, [sp, #(EXCEPTION_CONTEXT_X4_X5)]
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stp x6, x7, [sp, #(EXCEPTION_CONTEXT_X6_X7)]
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stp x8, x9, [sp, #(EXCEPTION_CONTEXT_X8_X9)]
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stp x10, x11, [sp, #(EXCEPTION_CONTEXT_X10_X11)]
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stp x12, x13, [sp, #(EXCEPTION_CONTEXT_X12_X13)]
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stp x14, x15, [sp, #(EXCEPTION_CONTEXT_X14_X15)]
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stp x16, x17, [sp, #(EXCEPTION_CONTEXT_X16_X17)]
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stp x18, x19, [sp, #(EXCEPTION_CONTEXT_X18_X19)]
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stp x20, x21, [sp, #(EXCEPTION_CONTEXT_X20_X21)]
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stp x22, x23, [sp, #(EXCEPTION_CONTEXT_X22_X23)]
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stp x24, x25, [sp, #(EXCEPTION_CONTEXT_X24_X25)]
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stp x26, x27, [sp, #(EXCEPTION_CONTEXT_X26_X27)]
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stp x28, x29, [sp, #(EXCEPTION_CONTEXT_X28_X29)]
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mrs x20, sp_el0
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mrs x21, elr_el1
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mrs x22, spsr_el1
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mrs x23, tpidr_el0
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mov w22, w22
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stp x30, x20, [sp, #(EXCEPTION_CONTEXT_X30_SP)]
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stp x21, x22, [sp, #(EXCEPTION_CONTEXT_PC_PSR)]
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str x23, [sp, #(EXCEPTION_CONTEXT_TPIDR)]
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disable_single_step x16
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/* Call ams::kern::arch::arm64::HandleException(ams::kern::arch::arm64::KExceptionContext *) */
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ldr x18, [sp, #(EXCEPTION_CONTEXT_SIZE + THREAD_STACK_PARAMETERS_CUR_THREAD)]
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mov x0, sp
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bl _ZN3ams4kern4arch5arm6415HandleExceptionEPNS2_17KExceptionContextE
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/* Restore state from the context. */
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ldp x30, x20, [sp, #(EXCEPTION_CONTEXT_X30_SP)]
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ldp x21, x22, [sp, #(EXCEPTION_CONTEXT_PC_PSR)]
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ldr x23, [sp, #(EXCEPTION_CONTEXT_TPIDR)]
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check_enable_single_step w0, x0, x22
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msr sp_el0, x20
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msr elr_el1, x21
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msr spsr_el1, x22
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msr tpidr_el0, x23
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ldp x0, x1, [sp, #(EXCEPTION_CONTEXT_X0_X1)]
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ldp x2, x3, [sp, #(EXCEPTION_CONTEXT_X2_X3)]
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ldp x4, x5, [sp, #(EXCEPTION_CONTEXT_X4_X5)]
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ldp x6, x7, [sp, #(EXCEPTION_CONTEXT_X6_X7)]
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ldp x8, x9, [sp, #(EXCEPTION_CONTEXT_X8_X9)]
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ldp x10, x11, [sp, #(EXCEPTION_CONTEXT_X10_X11)]
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ldp x12, x13, [sp, #(EXCEPTION_CONTEXT_X12_X13)]
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ldp x14, x15, [sp, #(EXCEPTION_CONTEXT_X14_X15)]
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ldp x16, x17, [sp, #(EXCEPTION_CONTEXT_X16_X17)]
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ldp x18, x19, [sp, #(EXCEPTION_CONTEXT_X18_X19)]
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ldp x20, x21, [sp, #(EXCEPTION_CONTEXT_X20_X21)]
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ldp x22, x23, [sp, #(EXCEPTION_CONTEXT_X22_X23)]
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ldp x24, x25, [sp, #(EXCEPTION_CONTEXT_X24_X25)]
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ldp x26, x27, [sp, #(EXCEPTION_CONTEXT_X26_X27)]
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ldp x28, x29, [sp, #(EXCEPTION_CONTEXT_X28_X29)]
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add sp, sp, #(EXCEPTION_CONTEXT_SIZE)
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/* Return from the exception. */
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eret
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2: /* SVC from aarch32. */
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ldp x16, x17, [sp], 16
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b _ZN3ams4kern4arch5arm6412SvcHandler32Ev
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3: /* SVC from aarch64. */
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ldp x16, x17, [sp], 16
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b _ZN3ams4kern4arch5arm6412SvcHandler64Ev
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4: /* FPU exception. */
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ldp x16, x17, [sp], 16
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b _ZN3ams4kern4arch5arm6425FpuAccessExceptionHandlerEv
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5: /* Check if there's a TLB conflict that caused the abort. */
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and x17, x16, #0x3F
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cmp x17, #0x30
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b.ne 1b
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/* Get the ASID in x17. */
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mrs x17, ttbr0_el1
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and x17, x17, #(0xFFFF << 48)
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/* Check if FAR is valid by examining the FnV bit. */
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tbnz x16, #10, 6f
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/* FAR is valid, so we can invalidate the address it holds. */
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mrs x16, far_el1
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lsr x16, x16, #12
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orr x17, x16, x17
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tlbi vae1, x17
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b 7f
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6: /* There's a TLB conflict and FAR isn't valid. */
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/* Invalidate the entire TLB. */
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tlbi aside1, x17
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7: /* Return from a TLB conflict. */
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/* Ensure instruction consistency. */
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dsb ish
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isb
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/* Restore x16 and x17. */
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ldp x16, x17, [sp], 16
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/* Return from the exception. */
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eret
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/* ams::kern::arch::arm64::EL1SynchronousExceptionHandler() */
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.section .text._ZN3ams4kern4arch5arm6430EL1SynchronousExceptionHandlerEv, "ax", %progbits
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.global _ZN3ams4kern4arch5arm6430EL1SynchronousExceptionHandlerEv
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.type _ZN3ams4kern4arch5arm6430EL1SynchronousExceptionHandlerEv, %function
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_ZN3ams4kern4arch5arm6430EL1SynchronousExceptionHandlerEv:
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/* Nintendo uses tpidr_el1 as a scratch register. */
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msr tpidr_el1, x0
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/* Get and parse the exception syndrome register. */
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mrs x0, esr_el1
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lsr x0, x0, #0x1a
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/* Is this an instruction abort? */
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cmp x0, #0x21
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b.eq 5f
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/* Is this a data abort? */
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cmp x0, #0x25
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b.eq 5f
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1: /* The exception is not a data abort or instruction abort caused by a TLB conflict. */
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/* Load the exception stack top from otherwise "unused" virtual timer compare value. */
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mrs x0, cntv_cval_el0
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/* Setup the stack for a generic exception handle */
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lsl x0, x0, #8
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asr x0, x0, #8
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sub x0, x0, #0x20
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str x1, [x0, #8]
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mov x1, sp
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str x1, [x0]
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mov sp, x0
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ldr x1, [x0, #8]
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mrs x0, tpidr_el1
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str x0, [sp, #8]
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str x1, [sp, #16]
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/* Check again if this is a data abort from EL1. */
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mrs x0, esr_el1
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lsr x1, x0, #0x1a
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cmp x1, #0x25
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b.ne 3f
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/* Data abort. Check if it was from trying to access userspace memory. */
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mrs x1, elr_el1
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adr x0, _ZN3ams4kern4arch5arm6432UserspaceAccessFunctionAreaBeginEv
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cmp x1, x0
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b.lo 3f
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adr x0, _ZN3ams4kern4arch5arm6430UserspaceAccessFunctionAreaEndEv
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cmp x1, x0
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b.hs 3f
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/* We aborted trying to access userspace memory. */
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/* All functions that access user memory return a boolean for whether they succeeded. */
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/* With that in mind, we can simply restore the stack pointer and return false directly. */
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ldr x0, [sp]
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mov sp, x0
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/* Return false. */
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mov x0, #0x0
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msr elr_el1, x30
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eret
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3: /* The exception wasn't an triggered by copying memory from userspace. */
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ldr x0, [sp, #8]
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ldr x1, [sp, #16]
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/* Create a KExceptionContext to pass to HandleException. */
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sub sp, sp, #(EXCEPTION_CONTEXT_SIZE)
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stp x0, x1, [sp, #(EXCEPTION_CONTEXT_X0_X1)]
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stp x2, x3, [sp, #(EXCEPTION_CONTEXT_X2_X3)]
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stp x4, x5, [sp, #(EXCEPTION_CONTEXT_X4_X5)]
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stp x6, x7, [sp, #(EXCEPTION_CONTEXT_X6_X7)]
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|
stp x8, x9, [sp, #(EXCEPTION_CONTEXT_X8_X9)]
|
|
stp x10, x11, [sp, #(EXCEPTION_CONTEXT_X10_X11)]
|
|
stp x12, x13, [sp, #(EXCEPTION_CONTEXT_X12_X13)]
|
|
stp x14, x15, [sp, #(EXCEPTION_CONTEXT_X14_X15)]
|
|
stp x16, x17, [sp, #(EXCEPTION_CONTEXT_X16_X17)]
|
|
stp x18, x19, [sp, #(EXCEPTION_CONTEXT_X18_X19)]
|
|
stp x20, x21, [sp, #(EXCEPTION_CONTEXT_X20_X21)]
|
|
stp x22, x23, [sp, #(EXCEPTION_CONTEXT_X22_X23)]
|
|
stp x24, x25, [sp, #(EXCEPTION_CONTEXT_X24_X25)]
|
|
stp x26, x27, [sp, #(EXCEPTION_CONTEXT_X26_X27)]
|
|
stp x28, x29, [sp, #(EXCEPTION_CONTEXT_X28_X29)]
|
|
|
|
mrs x20, sp_el0
|
|
mrs x21, elr_el1
|
|
mrs x22, spsr_el1
|
|
mrs x23, tpidr_el0
|
|
mov w22, w22
|
|
|
|
stp x30, x20, [sp, #(EXCEPTION_CONTEXT_X30_SP)]
|
|
stp x21, x22, [sp, #(EXCEPTION_CONTEXT_PC_PSR)]
|
|
str x23, [sp, #(EXCEPTION_CONTEXT_TPIDR)]
|
|
|
|
/* Call ams::kern::arch::arm64::HandleException(ams::kern::arch::arm64::KExceptionContext *) */
|
|
mov x0, sp
|
|
bl _ZN3ams4kern4arch5arm6415HandleExceptionEPNS2_17KExceptionContextE
|
|
|
|
4: /* HandleException should never return. The best we can do is infinite loop. */
|
|
b 4b
|
|
|
|
5: /* Check if there's a TLB conflict that caused the abort. */
|
|
/* NOTE: There is a Nintendo bug in this code that we correct. */
|
|
/* Nintendo compares the low 6 bits of x0 without restoring the value. */
|
|
/* They intend to check the DFSC/IFSC bits of esr_el1, but because they */
|
|
/* shifted esr earlier, the check is invalid and always fails. */
|
|
mrs x0, esr_el1
|
|
and x0, x0, #0x3F
|
|
cmp x0, #0x30
|
|
b.ne 1b
|
|
|
|
/* Check if FAR is valid by examining the FnV bit. */
|
|
/* NOTE: Nintendo again has a bug here, the same as above. */
|
|
/* They do not refresh the value of x0, and again compare with */
|
|
/* the relevant bit already masked out of x0. */
|
|
mrs x0, esr_el1
|
|
tbnz x0, #10, 6f
|
|
|
|
/* FAR is valid, so we can invalidate the address it holds. */
|
|
mrs x0, far_el1
|
|
lsr x0, x0, #12
|
|
tlbi vaae1, x0
|
|
b 7f
|
|
|
|
6: /* There's a TLB conflict and FAR isn't valid. */
|
|
/* Invalidate the entire TLB. */
|
|
tlbi vmalle1
|
|
|
|
7: /* Return from a TLB conflict. */
|
|
/* Ensure instruction consistency. */
|
|
dsb ish
|
|
isb
|
|
|
|
/* Restore x0 from scratch. */
|
|
mrs x0, tpidr_el1
|
|
|
|
/* Return from the exception. */
|
|
eret
|
|
|
|
|
|
/* ams::kern::arch::arm64::FpuAccessExceptionHandler() */
|
|
.section .text._ZN3ams4kern4arch5arm6425FpuAccessExceptionHandlerEv, "ax", %progbits
|
|
.global _ZN3ams4kern4arch5arm6425FpuAccessExceptionHandlerEv
|
|
.type _ZN3ams4kern4arch5arm6425FpuAccessExceptionHandlerEv, %function
|
|
_ZN3ams4kern4arch5arm6425FpuAccessExceptionHandlerEv:
|
|
/* Save registers that need saving. */
|
|
sub sp, sp, #(EXCEPTION_CONTEXT_SIZE)
|
|
|
|
stp x0, x1, [sp, #(EXCEPTION_CONTEXT_X0_X1)]
|
|
stp x2, x3, [sp, #(EXCEPTION_CONTEXT_X2_X3)]
|
|
stp x4, x5, [sp, #(EXCEPTION_CONTEXT_X4_X5)]
|
|
stp x6, x7, [sp, #(EXCEPTION_CONTEXT_X6_X7)]
|
|
stp x8, x9, [sp, #(EXCEPTION_CONTEXT_X8_X9)]
|
|
stp x10, x11, [sp, #(EXCEPTION_CONTEXT_X10_X11)]
|
|
stp x12, x13, [sp, #(EXCEPTION_CONTEXT_X12_X13)]
|
|
stp x14, x15, [sp, #(EXCEPTION_CONTEXT_X14_X15)]
|
|
stp x16, x17, [sp, #(EXCEPTION_CONTEXT_X16_X17)]
|
|
stp x18, x19, [sp, #(EXCEPTION_CONTEXT_X18_X19)]
|
|
stp x20, x21, [sp, #(EXCEPTION_CONTEXT_X20_X21)]
|
|
|
|
mrs x19, sp_el0
|
|
mrs x20, elr_el1
|
|
mrs x21, spsr_el1
|
|
mov w21, w21
|
|
|
|
stp x30, x19, [sp, #(EXCEPTION_CONTEXT_X30_SP)]
|
|
stp x20, x21, [sp, #(EXCEPTION_CONTEXT_PC_PSR)]
|
|
|
|
/* Invoke the FPU context switch handler. */
|
|
ldr x18, [sp, #(EXCEPTION_CONTEXT_SIZE + THREAD_STACK_PARAMETERS_CUR_THREAD)]
|
|
bl _ZN3ams4kern4arch5arm6423FpuContextSwitchHandlerEv
|
|
|
|
/* Restore registers that we saved. */
|
|
ldp x30, x19, [sp, #(EXCEPTION_CONTEXT_X30_SP)]
|
|
ldp x20, x21, [sp, #(EXCEPTION_CONTEXT_PC_PSR)]
|
|
|
|
msr sp_el0, x19
|
|
msr elr_el1, x20
|
|
msr spsr_el1, x21
|
|
|
|
ldp x0, x1, [sp, #(EXCEPTION_CONTEXT_X0_X1)]
|
|
ldp x2, x3, [sp, #(EXCEPTION_CONTEXT_X2_X3)]
|
|
ldp x4, x5, [sp, #(EXCEPTION_CONTEXT_X4_X5)]
|
|
ldp x6, x7, [sp, #(EXCEPTION_CONTEXT_X6_X7)]
|
|
ldp x8, x9, [sp, #(EXCEPTION_CONTEXT_X8_X9)]
|
|
ldp x10, x11, [sp, #(EXCEPTION_CONTEXT_X10_X11)]
|
|
ldp x12, x13, [sp, #(EXCEPTION_CONTEXT_X12_X13)]
|
|
ldp x14, x15, [sp, #(EXCEPTION_CONTEXT_X14_X15)]
|
|
ldp x16, x17, [sp, #(EXCEPTION_CONTEXT_X16_X17)]
|
|
ldp x18, x19, [sp, #(EXCEPTION_CONTEXT_X18_X19)]
|
|
ldp x20, x21, [sp, #(EXCEPTION_CONTEXT_X20_X21)]
|
|
|
|
add sp, sp, #(EXCEPTION_CONTEXT_SIZE)
|
|
|
|
/* Return from the exception. */
|
|
eret
|
|
|
|
/* ams::kern::arch::arm64::EL1SystemErrorHandler() */
|
|
.section .text._ZN3ams4kern4arch5arm6421EL1SystemErrorHandlerEv, "ax", %progbits
|
|
.global _ZN3ams4kern4arch5arm6421EL1SystemErrorHandlerEv
|
|
.type _ZN3ams4kern4arch5arm6421EL1SystemErrorHandlerEv, %function
|
|
_ZN3ams4kern4arch5arm6421EL1SystemErrorHandlerEv:
|
|
/* Nintendo uses tpidr_el1 as a scratch register. */
|
|
msr tpidr_el1, x0
|
|
|
|
/* Load the exception stack top from otherwise "unused" virtual timer compare value. */
|
|
mrs x0, cntv_cval_el0
|
|
|
|
/* Setup the stack for a generic exception handle */
|
|
lsl x0, x0, #8
|
|
asr x0, x0, #8
|
|
sub x0, x0, #0x20
|
|
str x1, [x0, #8]
|
|
mov x1, sp
|
|
str x1, [x0]
|
|
mov sp, x0
|
|
ldr x1, [x0, #8]
|
|
mrs x0, tpidr_el1
|
|
|
|
/* Create a KExceptionContext to pass to HandleException. */
|
|
sub sp, sp, #(EXCEPTION_CONTEXT_SIZE)
|
|
stp x0, x1, [sp, #(EXCEPTION_CONTEXT_X0_X1)]
|
|
stp x2, x3, [sp, #(EXCEPTION_CONTEXT_X2_X3)]
|
|
stp x4, x5, [sp, #(EXCEPTION_CONTEXT_X4_X5)]
|
|
stp x6, x7, [sp, #(EXCEPTION_CONTEXT_X6_X7)]
|
|
stp x8, x9, [sp, #(EXCEPTION_CONTEXT_X8_X9)]
|
|
stp x10, x11, [sp, #(EXCEPTION_CONTEXT_X10_X11)]
|
|
stp x12, x13, [sp, #(EXCEPTION_CONTEXT_X12_X13)]
|
|
stp x14, x15, [sp, #(EXCEPTION_CONTEXT_X14_X15)]
|
|
stp x16, x17, [sp, #(EXCEPTION_CONTEXT_X16_X17)]
|
|
stp x18, x19, [sp, #(EXCEPTION_CONTEXT_X18_X19)]
|
|
stp x20, x21, [sp, #(EXCEPTION_CONTEXT_X20_X21)]
|
|
stp x22, x23, [sp, #(EXCEPTION_CONTEXT_X22_X23)]
|
|
stp x24, x25, [sp, #(EXCEPTION_CONTEXT_X24_X25)]
|
|
stp x26, x27, [sp, #(EXCEPTION_CONTEXT_X26_X27)]
|
|
stp x28, x29, [sp, #(EXCEPTION_CONTEXT_X28_X29)]
|
|
|
|
mrs x20, sp_el0
|
|
mrs x21, elr_el1
|
|
mrs x22, spsr_el1
|
|
mrs x23, tpidr_el0
|
|
mov w22, w22
|
|
|
|
stp x30, x20, [sp, #(EXCEPTION_CONTEXT_X30_SP)]
|
|
stp x21, x22, [sp, #(EXCEPTION_CONTEXT_PC_PSR)]
|
|
str x23, [sp, #(EXCEPTION_CONTEXT_TPIDR)]
|
|
|
|
/* Invoke ams::kern::arch::arm64::HandleException(ams::kern::arch::arm64::KExceptionContext *). */
|
|
mov x0, sp
|
|
bl _ZN3ams4kern4arch5arm6415HandleExceptionEPNS2_17KExceptionContextE
|
|
|
|
1: /* HandleException should never return. The best we can do is infinite loop. */
|
|
b 1b
|
|
|
|
/* ams::kern::arch::arm64::EL0SystemErrorHandler() */
|
|
.section .text._ZN3ams4kern4arch5arm6421EL0SystemErrorHandlerEv, "ax", %progbits
|
|
.global _ZN3ams4kern4arch5arm6421EL0SystemErrorHandlerEv
|
|
.type _ZN3ams4kern4arch5arm6421EL0SystemErrorHandlerEv, %function
|
|
_ZN3ams4kern4arch5arm6421EL0SystemErrorHandlerEv:
|
|
/* Create a KExceptionContext to pass to HandleException. */
|
|
sub sp, sp, #(EXCEPTION_CONTEXT_SIZE)
|
|
|
|
stp x0, x1, [sp, #(EXCEPTION_CONTEXT_X0_X1)]
|
|
stp x2, x3, [sp, #(EXCEPTION_CONTEXT_X2_X3)]
|
|
stp x4, x5, [sp, #(EXCEPTION_CONTEXT_X4_X5)]
|
|
stp x6, x7, [sp, #(EXCEPTION_CONTEXT_X6_X7)]
|
|
stp x8, x9, [sp, #(EXCEPTION_CONTEXT_X8_X9)]
|
|
stp x10, x11, [sp, #(EXCEPTION_CONTEXT_X10_X11)]
|
|
stp x12, x13, [sp, #(EXCEPTION_CONTEXT_X12_X13)]
|
|
stp x14, x15, [sp, #(EXCEPTION_CONTEXT_X14_X15)]
|
|
stp x16, x17, [sp, #(EXCEPTION_CONTEXT_X16_X17)]
|
|
stp x18, x19, [sp, #(EXCEPTION_CONTEXT_X18_X19)]
|
|
stp x20, x21, [sp, #(EXCEPTION_CONTEXT_X20_X21)]
|
|
stp x22, x23, [sp, #(EXCEPTION_CONTEXT_X22_X23)]
|
|
stp x24, x25, [sp, #(EXCEPTION_CONTEXT_X24_X25)]
|
|
stp x26, x27, [sp, #(EXCEPTION_CONTEXT_X26_X27)]
|
|
stp x28, x29, [sp, #(EXCEPTION_CONTEXT_X28_X29)]
|
|
|
|
mrs x20, sp_el0
|
|
mrs x21, elr_el1
|
|
mrs x22, spsr_el1
|
|
mrs x23, tpidr_el0
|
|
mov w22, w22
|
|
|
|
stp x30, x20, [sp, #(EXCEPTION_CONTEXT_X30_SP)]
|
|
stp x21, x22, [sp, #(EXCEPTION_CONTEXT_PC_PSR)]
|
|
str x23, [sp, #(EXCEPTION_CONTEXT_TPIDR)]
|
|
|
|
/* Invoke ams::kern::arch::arm64::HandleException(ams::kern::arch::arm64::KExceptionContext *). */
|
|
ldr x18, [sp, #(EXCEPTION_CONTEXT_SIZE + THREAD_STACK_PARAMETERS_CUR_THREAD)]
|
|
mov x0, sp
|
|
bl _ZN3ams4kern4arch5arm6415HandleExceptionEPNS2_17KExceptionContextE
|
|
|
|
/* Restore state from the context. */
|
|
ldp x30, x20, [sp, #(EXCEPTION_CONTEXT_X30_SP)]
|
|
ldp x21, x22, [sp, #(EXCEPTION_CONTEXT_PC_PSR)]
|
|
ldr x23, [sp, #(EXCEPTION_CONTEXT_TPIDR)]
|
|
|
|
msr sp_el0, x20
|
|
msr elr_el1, x21
|
|
msr spsr_el1, x22
|
|
msr tpidr_el0, x23
|
|
|
|
ldp x0, x1, [sp, #(EXCEPTION_CONTEXT_X0_X1)]
|
|
ldp x2, x3, [sp, #(EXCEPTION_CONTEXT_X2_X3)]
|
|
ldp x4, x5, [sp, #(EXCEPTION_CONTEXT_X4_X5)]
|
|
ldp x6, x7, [sp, #(EXCEPTION_CONTEXT_X6_X7)]
|
|
ldp x8, x9, [sp, #(EXCEPTION_CONTEXT_X8_X9)]
|
|
ldp x10, x11, [sp, #(EXCEPTION_CONTEXT_X10_X11)]
|
|
ldp x12, x13, [sp, #(EXCEPTION_CONTEXT_X12_X13)]
|
|
ldp x14, x15, [sp, #(EXCEPTION_CONTEXT_X14_X15)]
|
|
ldp x16, x17, [sp, #(EXCEPTION_CONTEXT_X16_X17)]
|
|
ldp x18, x19, [sp, #(EXCEPTION_CONTEXT_X18_X19)]
|
|
ldp x20, x21, [sp, #(EXCEPTION_CONTEXT_X20_X21)]
|
|
ldp x22, x23, [sp, #(EXCEPTION_CONTEXT_X22_X23)]
|
|
ldp x24, x25, [sp, #(EXCEPTION_CONTEXT_X24_X25)]
|
|
ldp x26, x27, [sp, #(EXCEPTION_CONTEXT_X26_X27)]
|
|
ldp x28, x29, [sp, #(EXCEPTION_CONTEXT_X28_X29)]
|
|
|
|
add sp, sp, #(EXCEPTION_CONTEXT_SIZE)
|
|
|
|
/* Return from the exception. */
|
|
eret
|
|
|