mirror of
https://github.com/Atmosphere-NX/Atmosphere
synced 2024-11-10 07:06:34 +00:00
302 lines
No EOL
9.5 KiB
C
302 lines
No EOL
9.5 KiB
C
/*
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* Copyright (c) 2018 naehrwert
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* Copyright (c) 2018 CTCaer
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* Copyright (c) 2018-2019 Atmosphère-NX
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "hwinit.h"
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#include "apb_misc.h"
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#include "car.h"
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#include "di.h"
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#include "fuse.h"
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#include "gpio.h"
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#include "i2c.h"
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#include "max77620.h"
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#include "mc.h"
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#include "pinmux.h"
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#include "pmc.h"
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#include "se.h"
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#include "sdram.h"
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#include "sysctr0.h"
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#include "sysreg.h"
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#include "timers.h"
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#include "uart.h"
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void config_oscillators()
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{
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volatile tegra_car_t *car = car_get_regs();
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volatile tegra_pmc_t *pmc = pmc_get_regs();
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car->spare_reg0 = ((car->spare_reg0 & 0xFFFFFFF3) | 4);
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SYSCTR0_CNTFID0_0 = 19200000;
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TIMERUS_USEC_CFG_0 = 0x45F;
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car->osc_ctrl = 0x50000071;
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pmc->osc_edpd_over = ((pmc->osc_edpd_over & 0xFFFFFF81) | 0xE);
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pmc->osc_edpd_over = ((pmc->osc_edpd_over & 0xFFBFFFFF) | 0x400000);
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pmc->cntrl2 = ((pmc->cntrl2 & 0xFFFFEFFF) | 0x1000);
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pmc->scratch188 = ((pmc->scratch188 & 0xFCFFFFFF) | 0x2000000);
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car->clk_sys_rate = 0x10;
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car->pllmb_base &= 0xBFFFFFFF;
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pmc->tsc_mult = ((pmc->tsc_mult & 0xFFFF0000) | 0x249F); /* 0x249F = 19200000 * (16 / 32.768 kHz) */
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car->sclk_brst_pol = 0x20004444;
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car->super_sclk_div = 0x80000000;
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car->clk_sys_rate = 2;
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}
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void config_gpios()
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{
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volatile tegra_pinmux_t *pinmux = pinmux_get_regs();
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pinmux->uart2_tx = 0;
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pinmux->uart3_tx = 0;
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pinmux->pe6 = PINMUX_INPUT;
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pinmux->ph6 = PINMUX_INPUT;
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gpio_configure_mode(TEGRA_GPIO(G, 0), GPIO_MODE_GPIO);
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gpio_configure_mode(TEGRA_GPIO(D, 1), GPIO_MODE_GPIO);
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gpio_configure_mode(TEGRA_GPIO(E, 6), GPIO_MODE_GPIO);
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gpio_configure_mode(TEGRA_GPIO(H, 6), GPIO_MODE_GPIO);
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gpio_configure_direction(TEGRA_GPIO(G, 0), GPIO_DIRECTION_INPUT);
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gpio_configure_direction(TEGRA_GPIO(D, 1), GPIO_DIRECTION_INPUT);
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gpio_configure_direction(TEGRA_GPIO(E, 6), GPIO_DIRECTION_INPUT);
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gpio_configure_direction(TEGRA_GPIO(H, 6), GPIO_DIRECTION_INPUT);
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pinmux->gen1_i2c_scl = PINMUX_INPUT;
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pinmux->gen1_i2c_sda = PINMUX_INPUT;
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pinmux->pwr_i2c_scl = PINMUX_INPUT;
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pinmux->pwr_i2c_sda = PINMUX_INPUT;
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pinmux->uart1_rx = 0;
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pinmux->uart1_tx = (PINMUX_INPUT | PINMUX_PULL_UP);
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pinmux->uart1_rts = 0;
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pinmux->uart1_cts = (PINMUX_INPUT | PINMUX_PULL_DOWN);
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/* Configure volume up/down as inputs. */
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gpio_configure_mode(GPIO_BUTTON_VOL_UP, GPIO_MODE_GPIO);
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gpio_configure_mode(GPIO_BUTTON_VOL_DOWN, GPIO_MODE_GPIO);
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gpio_configure_direction(GPIO_BUTTON_VOL_UP, GPIO_DIRECTION_INPUT);
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gpio_configure_direction(GPIO_BUTTON_VOL_DOWN, GPIO_DIRECTION_INPUT);
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}
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void config_pmc_scratch()
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{
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volatile tegra_pmc_t *pmc = pmc_get_regs();
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pmc->scratch20 &= 0xFFF3FFFF;
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pmc->scratch190 &= 0xFFFFFFFE;
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pmc->secure_scratch21 |= 0x10;
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}
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void mbist_workaround()
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{
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volatile tegra_car_t *car = car_get_regs();
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car->clk_source_sor1 = ((car->clk_source_sor1 | 0x8000) & 0xFFFFBFFF);
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car->plld_base |= 0x40800000u;
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car->rst_dev_y_clr = 0x40;
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car->rst_dev_x_clr = 0x40000;
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car->rst_dev_l_clr = 0x18000000;
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udelay(2);
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/* Setup I2S. */
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MAKE_I2S_REG(0x0A0) |= 0x400;
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MAKE_I2S_REG(0x088) &= 0xFFFFFFFE;
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MAKE_I2S_REG(0x1A0) |= 0x400;
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MAKE_I2S_REG(0x188) &= 0xFFFFFFFE;
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MAKE_I2S_REG(0x2A0) |= 0x400;
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MAKE_I2S_REG(0x288) &= 0xFFFFFFFE;
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MAKE_I2S_REG(0x3A0) |= 0x400;
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MAKE_I2S_REG(0x388) &= 0xFFFFFFFE;
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MAKE_I2S_REG(0x4A0) |= 0x400;
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MAKE_I2S_REG(0x488) &= 0xFFFFFFFE;
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MAKE_DI_REG(DC_COM_DSC_TOP_CTL) |= 4;
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MAKE_VIC_REG(0x8C) = 0xFFFFFFFF;
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udelay(2);
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/* Set devices in reset. */
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car->rst_dev_y_set = 0x40;
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car->rst_dev_l_set = 0x18000000;
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car->rst_dev_x_set = 0x40000;
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/* Clock out enables. */
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car->clk_out_enb_h = 0xC0;
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car->clk_out_enb_l = 0x80000130;
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car->clk_out_enb_u = 0x1F00200;
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car->clk_out_enb_v = 0x80400808;
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car->clk_out_enb_w = 0x402000FC;
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car->clk_out_enb_x = 0x23000780;
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car->clk_out_enb_y = 0x300;
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/* LVL2 clock gate overrides. */
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car->lvl2_clk_gate_ovra = 0;
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car->lvl2_clk_gate_ovrb = 0;
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car->lvl2_clk_gate_ovrc = 0;
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car->lvl2_clk_gate_ovrd = 0;
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car->lvl2_clk_gate_ovre = 0;
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/* Configure clock sources. */
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car->plld_base &= 0x1F7FFFFF;
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car->clk_source_sor1 &= 0xFFFF3FFF;
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car->clk_source_vi = ((car->clk_source_vi & 0x1FFFFFFF) | 0x80000000);
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car->clk_source_host1x = ((car->clk_source_host1x & 0x1FFFFFFF) | 0x80000000);
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car->clk_source_nvenc = ((car->clk_source_nvenc & 0x1FFFFFFF) | 0x80000000);
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}
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void config_se_brom()
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{
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volatile tegra_fuse_chip_t *fuse_chip = fuse_chip_get_regs();
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volatile tegra_se_t *se = se_get_regs();
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volatile tegra_pmc_t *pmc = pmc_get_regs();
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/* Bootrom part we skipped. */
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uint32_t sbk[4] = {fuse_chip->FUSE_PRIVATE_KEY[0], fuse_chip->FUSE_PRIVATE_KEY[1], fuse_chip->FUSE_PRIVATE_KEY[2], fuse_chip->FUSE_PRIVATE_KEY[3]};
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set_aes_keyslot(0xE, sbk, 0x10);
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/* Lock SBK from being read. */
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se->AES_KEYSLOT_FLAGS[0xE] = 0x7E;
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/* This memset needs to happen here, else TZRAM will behave weirdly later on. */
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memset((void *)0x7C010000, 0, 0x10000);
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pmc->crypto_op = 0;
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se->INT_STATUS_REG = 0x1F;
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/* Lock SSK (although it's not set and unused anyways). */
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se->AES_KEYSLOT_FLAGS[0xF] = 0x7E;
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/* Clear the boot reason to avoid problems later */
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pmc->scratch200 = 0;
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pmc->reset_status = 0;
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}
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void nx_hwinit()
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{
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volatile tegra_pmc_t *pmc = pmc_get_regs();
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volatile tegra_car_t *car = car_get_regs();
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/* Bootrom stuff we skipped by going through RCM. */
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config_se_brom();
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AHB_AHB_SPARE_REG_0 &= 0xFFFFFF9F;
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pmc->scratch49 = (((pmc->scratch49 >> 1) << 1) & 0xFFFFFFFD);
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/* Apply the memory built-in self test workaround. */
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mbist_workaround();
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/* Reboot SE. */
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clkrst_reboot(CARDEVICE_SE);
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/* Initialize the fuse driver. */
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fuse_init();
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/* Initialize the memory controller. */
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mc_enable();
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/* Configure oscillators. */
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config_oscillators();
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/* Disable pinmux tristate input clamping. */
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APB_MISC_PP_PINMUX_GLOBAL_0 = 0;
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/* Configure GPIOs. */
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/* NOTE: [3.0.0+] Part of the GPIO configuration is skipped if the unit is SDEV. */
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/* NOTE: [6.0.0+] The GPIO configuration's order was changed a bit. */
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config_gpios();
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/* Uncomment for UART debugging. */
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/*
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clkrst_reboot(CARDEVICE_UARTC);
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uart_init(UART_C, 115200);
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*/
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/* Reboot CL-DVFS. */
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clkrst_reboot(CARDEVICE_CL_DVFS);
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/* Reboot I2C1. */
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clkrst_reboot(CARDEVICE_I2C1);
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/* Reboot I2C5. */
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clkrst_reboot(CARDEVICE_I2C5);
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/* Reboot SE. */
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/* NOTE: [4.0.0+] This was removed. */
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/* clkrst_reboot(CARDEVICE_SE); */
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/* Reboot unknown device. */
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clkrst_reboot(CARDEVICE_UNK);
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/* Initialize I2C1. */
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/* NOTE: [6.0.0+] This was moved to after the PMIC is configured. */
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i2c_init(I2C_1);
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/* Initialize I2C5. */
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i2c_init(I2C_5);
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/* Configure the PMIC. */
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uint8_t val = 0x40;
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i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_CNFGBBC, &val, 1);
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val = 0x60;
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i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_ONOFFCNFG1, &val, 1);
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val = 0x38;
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i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_FPS_CFG0, &val, 1);
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val = 0x3A;
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i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_FPS_CFG1, &val, 1);
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val = 0x38;
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i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_FPS_CFG2, &val, 1);
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val = 0xF;
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i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_FPS_LDO4, &val, 1);
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val = 0xC7;
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i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_FPS_LDO8, &val, 1);
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val = 0x4F;
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i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_FPS_SD0, &val, 1);
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val = 0x29;
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i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_FPS_SD1, &val, 1);
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val = 0x1B;
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i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_FPS_SD3, &val, 1);
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/* NOTE: [3.0.0+] This was added. */
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val = 0x22;
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i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_FPS_GPIO3, &val, 1);
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/* TODO: In 3.x+, if the unit is SDEV, the MBLPD bit is set. */
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/*
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i2c_query(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_CNFGGLBL1, &val, 1);
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val |= 0x40;
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i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_CNFGGLBL1, &val, 1);
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*/
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/* Configure SD0 voltage. */
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val = 42; /* 42 = (1125000 - 600000) / 12500 -> 1.125V */
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i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_SD0, &val, 1);
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/* Configure and lock PMC scratch registers. */
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/* NOTE: [4.0.0+] This was removed. */
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config_pmc_scratch();
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/* Set super clock burst policy. */
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car->sclk_brst_pol = ((car->sclk_brst_pol & 0xFFFF8888) | 0x3333);
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/* Configure memory controller carveouts. */
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/* NOTE: [4.0.0+] This is now done in the Secure Monitor. */
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/* mc_config_carveout(); */
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/* Initialize SDRAM. */
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sdram_init();
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/* Save SDRAM LP0 parameters. */
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sdram_lp0_save_params(sdram_get_params());
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} |