From fccadfdbf6dc66f048a99afed672141ee0709a4f Mon Sep 17 00:00:00 2001
From: TuxSH <1922548+TuxSH@users.noreply.github.com>
Date: Mon, 2 Mar 2020 00:42:34 +0000
Subject: [PATCH] thermosphere: add TCR_TG0 back

---
 thermosphere/src/cpu/hvisor_cpu_sysreg_general.hpp | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/thermosphere/src/cpu/hvisor_cpu_sysreg_general.hpp b/thermosphere/src/cpu/hvisor_cpu_sysreg_general.hpp
index 6f043aac1..ea12caeb3 100644
--- a/thermosphere/src/cpu/hvisor_cpu_sysreg_general.hpp
+++ b/thermosphere/src/cpu/hvisor_cpu_sysreg_general.hpp
@@ -469,7 +469,7 @@ namespace ams::hvisor::cpu {
     };
 
     // Could have used enum class here, but can't start identifiers with a digit...
-    enum TranslationGranuleSize {
+    enum TranslationGranuleSize : u64 {
         TranslationGranule_4K   = 0,
         TranslationGranule_64K  = 1,
         TranslationGranule_16K  = 2,
@@ -485,6 +485,10 @@ namespace ams::hvisor::cpu {
         }
     }
 
+    constexpr u64 TCR_TG0(TranslationGranuleSize granuleSize)
+    {
+        return (granuleSize & 3) << 14;
+    }
     constexpr u64 TCR_T0SZ(size_t addressSpaceSize) { return (64ul - (addressSpaceSize & 0x3F)) << 0; }
     constexpr u64 TCR_PS(u64 n)                     { return (n & 7) << 16; }
     constexpr u64 VTCR_SL0(u64 n)                   { return (n & 3) << 6; }