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dmnt: implement debug log opcode

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This commit is contained in:
Michael Scire 2019-05-27 18:44:09 -07:00
parent c2cb94062a
commit f38965d0bd
2 changed files with 235 additions and 67 deletions
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202
stratosphere/dmnt/source/dmnt_cheat_vm.cpp
View file

@ -14,12 +14,27 @@
* along with this program. If not, see <http://www.gnu.org/licenses/>. * along with this program. If not, see <http://www.gnu.org/licenses/>.
*/ */
#include <sys/stat.h>
#include <switch.h> #include <switch.h>
#include "dmnt_cheat_types.hpp" #include "dmnt_cheat_types.hpp"
#include "dmnt_cheat_vm.hpp" #include "dmnt_cheat_vm.hpp"
#include "dmnt_cheat_manager.hpp" #include "dmnt_cheat_manager.hpp"
#include "dmnt_hid.hpp" #include "dmnt_hid.hpp"
void DmntCheatVm::DebugLog(u32 log_id, u64 value) {
/* Just unconditionally try to create the log folder. */
mkdir("/atmosphere/cheat_vm_logs", 0777);
FILE *f_log = NULL;
{
char log_path[FS_MAX_PATH];
snprintf(log_path, sizeof(log_path), "/atmosphere/cheat_vm_logs/%x.log", log_id);
f_log = fopen(log_path, "ab");
}
if (f_log != NULL) {
ON_SCOPE_EXIT { fclose(f_log); };
fprintf(f_log, "%016lx\n", value);
}
}
void DmntCheatVm::OpenDebugLogFile() { void DmntCheatVm::OpenDebugLogFile() {
#ifdef DMNT_CHEAT_VM_DEBUG_LOG #ifdef DMNT_CHEAT_VM_DEBUG_LOG
@ -157,36 +172,36 @@ void DmntCheatVm::LogOpcode(const CheatVmOpcode *opcode) {
this->LogToDebugFile("Bit Width: %x\n", opcode->begin_reg_cond.bit_width); this->LogToDebugFile("Bit Width: %x\n", opcode->begin_reg_cond.bit_width);
this->LogToDebugFile("Cond Type: %x\n", opcode->begin_reg_cond.cond_type); this->LogToDebugFile("Cond Type: %x\n", opcode->begin_reg_cond.cond_type);
this->LogToDebugFile("V Reg Idx: %x\n", opcode->begin_reg_cond.val_reg_index); this->LogToDebugFile("V Reg Idx: %x\n", opcode->begin_reg_cond.val_reg_index);
switch (opcode->begin_reg_cond.comp_type) { switch (opcode->begin_reg_cond.comp_type) {
case CompareRegisterValueType_StaticValue: case CompareRegisterValueType_StaticValue:
this->LogToDebugFile("Comp Type: Static Value\n"); this->LogToDebugFile("Comp Type: Static Value\n");
this->LogToDebugFile("Value: %lx\n", opcode->begin_reg_cond.value.bit64); this->LogToDebugFile("Value: %lx\n", opcode->begin_reg_cond.value.bit64);
break; break;
case CompareRegisterValueType_OtherRegister: case CompareRegisterValueType_OtherRegister:
this->LogToDebugFile("Comp Type: Other Register\n"); this->LogToDebugFile("Comp Type: Other Register\n");
this->LogToDebugFile("X Reg Idx: %x\n", opcode->begin_reg_cond.other_reg_index); this->LogToDebugFile("X Reg Idx: %x\n", opcode->begin_reg_cond.other_reg_index);
break; break;
case CompareRegisterValueType_MemoryRelAddr: case CompareRegisterValueType_MemoryRelAddr:
this->LogToDebugFile("Comp Type: Memory Relative Address\n"); this->LogToDebugFile("Comp Type: Memory Relative Address\n");
this->LogToDebugFile("Mem Type: %x\n", opcode->begin_reg_cond.mem_type); this->LogToDebugFile("Mem Type: %x\n", opcode->begin_reg_cond.mem_type);
this->LogToDebugFile("Rel Addr: %lx\n", opcode->begin_reg_cond.rel_address); this->LogToDebugFile("Rel Addr: %lx\n", opcode->begin_reg_cond.rel_address);
break; break;
case CompareRegisterValueType_MemoryOfsReg: case CompareRegisterValueType_MemoryOfsReg:
this->LogToDebugFile("Comp Type: Memory Offset Register\n"); this->LogToDebugFile("Comp Type: Memory Offset Register\n");
this->LogToDebugFile("Mem Type: %x\n", opcode->begin_reg_cond.mem_type); this->LogToDebugFile("Mem Type: %x\n", opcode->begin_reg_cond.mem_type);
this->LogToDebugFile("O Reg Idx: %x\n", opcode->begin_reg_cond.ofs_reg_index); this->LogToDebugFile("O Reg Idx: %x\n", opcode->begin_reg_cond.ofs_reg_index);
break; break;
case CompareRegisterValueType_RegisterRelAddr: case CompareRegisterValueType_RegisterRelAddr:
this->LogToDebugFile("Comp Type: Register Relative Address\n"); this->LogToDebugFile("Comp Type: Register Relative Address\n");
this->LogToDebugFile("A Reg Idx: %x\n", opcode->begin_reg_cond.addr_reg_index); this->LogToDebugFile("A Reg Idx: %x\n", opcode->begin_reg_cond.addr_reg_index);
this->LogToDebugFile("Rel Addr: %lx\n", opcode->begin_reg_cond.rel_address); this->LogToDebugFile("Rel Addr: %lx\n", opcode->begin_reg_cond.rel_address);
break; break;
case CompareRegisterValueType_RegisterOfsReg: case CompareRegisterValueType_RegisterOfsReg:
this->LogToDebugFile("Comp Type: Register Offset Register\n"); this->LogToDebugFile("Comp Type: Register Offset Register\n");
this->LogToDebugFile("A Reg Idx: %x\n", opcode->begin_reg_cond.addr_reg_index); this->LogToDebugFile("A Reg Idx: %x\n", opcode->begin_reg_cond.addr_reg_index);
this->LogToDebugFile("O Reg Idx: %x\n", opcode->begin_reg_cond.ofs_reg_index); this->LogToDebugFile("O Reg Idx: %x\n", opcode->begin_reg_cond.ofs_reg_index);
break; break;
} }
break; break;
case CheatVmOpcodeType_SaveRestoreRegister: case CheatVmOpcodeType_SaveRestoreRegister:
this->LogToDebugFile("Opcode: Save or Restore Register\n"); this->LogToDebugFile("Opcode: Save or Restore Register\n");
@ -201,6 +216,37 @@ void DmntCheatVm::LogOpcode(const CheatVmOpcode *opcode) {
this->LogToDebugFile("Act[%02x]: %d\n", i, opcode->save_restore_regmask.should_operate[i]); this->LogToDebugFile("Act[%02x]: %d\n", i, opcode->save_restore_regmask.should_operate[i]);
} }
break; break;
case CheatVmOpcodeType_DebugLog:
this->LogToDebugFile("Opcode: Debug Log\n");
this->LogToDebugFile("Bit Width: %x\n", opcode->debug_log.bit_width);
this->LogToDebugFile("Log ID: %x\n", opcode->debug_log.log_id);
this->LogToDebugFile("Val Type: %x\n", opcode->debug_log.val_type);
switch (opcode->debug_log.val_type) {
case DebugLogValueType_RegisterValue:
this->LogToDebugFile("Val Type: Register Value\n");
this->LogToDebugFile("X Reg Idx: %x\n", opcode->debug_log.val_reg_index);
break;
case DebugLogValueType_MemoryRelAddr:
this->LogToDebugFile("Val Type: Memory Relative Address\n");
this->LogToDebugFile("Mem Type: %x\n", opcode->debug_log.mem_type);
this->LogToDebugFile("Rel Addr: %lx\n", opcode->debug_log.rel_address);
break;
case DebugLogValueType_MemoryOfsReg:
this->LogToDebugFile("Val Type: Memory Offset Register\n");
this->LogToDebugFile("Mem Type: %x\n", opcode->debug_log.mem_type);
this->LogToDebugFile("O Reg Idx: %x\n", opcode->debug_log.ofs_reg_index);
break;
case DebugLogValueType_RegisterRelAddr:
this->LogToDebugFile("Val Type: Register Relative Address\n");
this->LogToDebugFile("A Reg Idx: %x\n", opcode->debug_log.addr_reg_index);
this->LogToDebugFile("Rel Addr: %lx\n", opcode->debug_log.rel_address);
break;
case DebugLogValueType_RegisterOfsReg:
this->LogToDebugFile("Val Type: Register Offset Register\n");
this->LogToDebugFile("A Reg Idx: %x\n", opcode->debug_log.addr_reg_index);
this->LogToDebugFile("O Reg Idx: %x\n", opcode->debug_log.ofs_reg_index);
break;
}
default: default:
this->LogToDebugFile("Unknown opcode: %x\n", opcode->opcode); this->LogToDebugFile("Unknown opcode: %x\n", opcode->opcode);
break; break;
@ -503,6 +549,51 @@ bool DmntCheatVm::DecodeNextOpcode(CheatVmOpcode *out) {
} }
} }
break; break;
case CheatVmOpcodeType_DebugLog:
{
/* FFFTIX## */
/* FFFTI0Ma aaaaaaaa */
/* FFFTI1Mr */
/* FFFTI2Ra aaaaaaaa */
/* FFFTI3Rr */
/* FFFTI4X0 */
/* FFF = opcode 0xFFF */
/* T = bit width. */
/* I = log id. */
/* X = value operand type, 0 = main/heap with relative offset, 1 = main/heap with offset register, */
/* 2 = register with relative offset, 3 = register with offset register, 4 = register value. */
/* M = memory type. */
/* R = address register. */
/* a = relative address. */
/* r = offset register. */
/* X = value register. */
opcode.debug_log.bit_width = (first_dword >> 16) & 0xF;
opcode.debug_log.log_id = ((first_dword >> 12) & 0xF);
opcode.debug_log.val_type = (DebugLogValueType)((first_dword >> 8) & 0xF);
switch (opcode.debug_log.val_type) {
case DebugLogValueType_RegisterValue:
opcode.debug_log.val_reg_index = ((first_dword >> 4) & 0xF);
break;
case DebugLogValueType_MemoryRelAddr:
opcode.debug_log.mem_type = (MemoryAccessType)((first_dword >> 4) & 0xF);
opcode.debug_log.rel_address = (((u64)(first_dword & 0xF) << 32ul) | ((u64)GetNextDword()));
break;
case DebugLogValueType_MemoryOfsReg:
opcode.debug_log.mem_type = (MemoryAccessType)((first_dword >> 4) & 0xF);
opcode.debug_log.ofs_reg_index = (first_dword & 0xF);
break;
case DebugLogValueType_RegisterRelAddr:
opcode.debug_log.addr_reg_index = ((first_dword >> 4) & 0xF);
opcode.debug_log.rel_address = (((u64)(first_dword & 0xF) << 32ul) | ((u64)GetNextDword()));
break;
case DebugLogValueType_RegisterOfsReg:
opcode.debug_log.addr_reg_index = ((first_dword >> 4) & 0xF);
opcode.debug_log.ofs_reg_index = (first_dword & 0xF);
break;
}
}
break;
case CheatVmOpcodeType_ExtendedWidth: case CheatVmOpcodeType_ExtendedWidth:
case CheatVmOpcodeType_DoubleExtendedWidth: case CheatVmOpcodeType_DoubleExtendedWidth:
default: default:
@ -1062,6 +1153,57 @@ void DmntCheatVm::Execute(const CheatProcessMetadata *metadata) {
} }
} }
break; break;
case CheatVmOpcodeType_DebugLog:
{
/* Read value from memory. */
u64 log_value = 0;
if (cur_opcode.debug_log.val_type == DebugLogValueType_RegisterValue) {
switch (cur_opcode.debug_log.bit_width) {
case 1:
log_value = static_cast<u8>(this->registers[cur_opcode.debug_log.val_reg_index] & 0xFFul);
break;
case 2:
log_value = static_cast<u16>(this->registers[cur_opcode.debug_log.val_reg_index] & 0xFFFFul);
break;
case 4:
log_value = static_cast<u32>(this->registers[cur_opcode.debug_log.val_reg_index] & 0xFFFFFFFFul);
break;
case 8:
log_value = static_cast<u64>(this->registers[cur_opcode.debug_log.val_reg_index] & 0xFFFFFFFFFFFFFFFFul);
break;
}
} else {
u64 val_address = 0;
switch (cur_opcode.debug_log.val_type) {
case DebugLogValueType_MemoryRelAddr:
val_address = GetCheatProcessAddress(metadata, cur_opcode.debug_log.mem_type, cur_opcode.debug_log.rel_address);
break;
case DebugLogValueType_MemoryOfsReg:
val_address = GetCheatProcessAddress(metadata, cur_opcode.debug_log.mem_type, this->registers[cur_opcode.debug_log.ofs_reg_index]);
break;
case DebugLogValueType_RegisterRelAddr:
val_address = this->registers[cur_opcode.debug_log.addr_reg_index] + cur_opcode.debug_log.rel_address;
break;
case DebugLogValueType_RegisterOfsReg:
val_address = this->registers[cur_opcode.debug_log.addr_reg_index] + this->registers[cur_opcode.debug_log.ofs_reg_index];
break;
default:
break;
}
switch (cur_opcode.debug_log.bit_width) {
case 1:
case 2:
case 4:
case 8:
DmntCheatManager::ReadCheatProcessMemoryForVm(val_address, &log_value, cur_opcode.debug_log.bit_width);
break;
}
}
/* Log value. */
this->DebugLog(cur_opcode.debug_log.log_id, log_value);
}
break;
default: default:
/* By default, we do a no-op. */ /* By default, we do a no-op. */
break; break;

26
stratosphere/dmnt/source/dmnt_cheat_vm.hpp
View file

@ -49,6 +49,9 @@ enum CheatVmOpcodeType : u32 {
/* This is a meta entry, and not a real opcode. */ /* This is a meta entry, and not a real opcode. */
/* This is to facilitate multi-nybble instruction decoding. */ /* This is to facilitate multi-nybble instruction decoding. */
CheatVmOpcodeType_DoubleExtendedWidth = 0xF0, CheatVmOpcodeType_DoubleExtendedWidth = 0xF0,
/* Double-extended width opcodes. */
CheatVmOpcodeType_DebugLog = 0xFFF,
}; };
enum MemoryAccessType : u32 { enum MemoryAccessType : u32 {
@ -106,6 +109,14 @@ enum SaveRestoreRegisterOpType : u32 {
SaveRestoreRegisterOpType_ClearRegs = 3, SaveRestoreRegisterOpType_ClearRegs = 3,
}; };
enum DebugLogValueType : u32 {
DebugLogValueType_MemoryRelAddr = 0,
DebugLogValueType_MemoryOfsReg = 1,
DebugLogValueType_RegisterRelAddr = 2,
DebugLogValueType_RegisterOfsReg = 3,
DebugLogValueType_RegisterValue = 4,
};
union VmInt { union VmInt {
u8 bit8; u8 bit8;
u16 bit16; u16 bit16;
@ -215,6 +226,17 @@ struct SaveRestoreRegisterMaskOpcode {
bool should_operate[0x10]; bool should_operate[0x10];
}; };
struct DebugLogOpcode {
u32 bit_width;
u32 log_id;
DebugLogValueType val_type;
MemoryAccessType mem_type;
u32 addr_reg_index;
u32 val_reg_index;
u32 ofs_reg_index;
u64 rel_address;
};
struct CheatVmOpcode { struct CheatVmOpcode {
CheatVmOpcodeType opcode; CheatVmOpcodeType opcode;
bool begin_conditional_block; bool begin_conditional_block;
@ -233,6 +255,7 @@ struct CheatVmOpcode {
BeginRegisterConditionalOpcode begin_reg_cond; BeginRegisterConditionalOpcode begin_reg_cond;
SaveRestoreRegisterOpcode save_restore_reg; SaveRestoreRegisterOpcode save_restore_reg;
SaveRestoreRegisterMaskOpcode save_restore_regmask; SaveRestoreRegisterMaskOpcode save_restore_regmask;
DebugLogOpcode debug_log;
}; };
}; };
@ -254,6 +277,9 @@ class DmntCheatVm {
void SkipConditionalBlock(); void SkipConditionalBlock();
void ResetState(); void ResetState();
/* For implementing the DebugLog opcode. */
void DebugLog(u32 log_id, u64 value);
/* For debugging. These will be IFDEF'd out normally. */ /* For debugging. These will be IFDEF'd out normally. */
void OpenDebugLogFile(); void OpenDebugLogFile();
void CloseDebugLogFile(); void CloseDebugLogFile();