mirror of
https://github.com/Atmosphere-NX/Atmosphere
synced 2024-09-19 22:59:00 +00:00
dmnt: implement debug log opcode
This commit is contained in:
Michael Scire
parent
c2cb94062a
commit
f38965d0bd
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@ -13,13 +13,28 @@
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <sys/stat.h>
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#include <switch.h>
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#include "dmnt_cheat_types.hpp"
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#include "dmnt_cheat_vm.hpp"
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#include "dmnt_cheat_manager.hpp"
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#include "dmnt_hid.hpp"
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void DmntCheatVm::DebugLog(u32 log_id, u64 value) {
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/* Just unconditionally try to create the log folder. */
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mkdir("/atmosphere/cheat_vm_logs", 0777);
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FILE *f_log = NULL;
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{
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char log_path[FS_MAX_PATH];
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snprintf(log_path, sizeof(log_path), "/atmosphere/cheat_vm_logs/%x.log", log_id);
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f_log = fopen(log_path, "ab");
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}
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if (f_log != NULL) {
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ON_SCOPE_EXIT { fclose(f_log); };
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fprintf(f_log, "%016lx\n", value);
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}
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}
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void DmntCheatVm::OpenDebugLogFile() {
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#ifdef DMNT_CHEAT_VM_DEBUG_LOG
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@ -152,55 +167,86 @@ void DmntCheatVm::LogOpcode(const CheatVmOpcode *opcode) {
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break;
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}
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break;
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case CheatVmOpcodeType_BeginRegisterConditionalBlock:
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case CheatVmOpcodeType_BeginRegisterConditionalBlock:
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this->LogToDebugFile("Opcode: Begin Register Conditional\n");
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this->LogToDebugFile("Bit Width: %x\n", opcode->begin_reg_cond.bit_width);
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this->LogToDebugFile("Cond Type: %x\n", opcode->begin_reg_cond.cond_type);
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this->LogToDebugFile("V Reg Idx: %x\n", opcode->begin_reg_cond.val_reg_index);
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switch (opcode->begin_reg_cond.comp_type) {
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case CompareRegisterValueType_StaticValue:
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this->LogToDebugFile("Comp Type: Static Value\n");
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this->LogToDebugFile("Value: %lx\n", opcode->begin_reg_cond.value.bit64);
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break;
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case CompareRegisterValueType_OtherRegister:
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this->LogToDebugFile("Comp Type: Other Register\n");
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this->LogToDebugFile("X Reg Idx: %x\n", opcode->begin_reg_cond.other_reg_index);
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break;
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case CompareRegisterValueType_MemoryRelAddr:
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this->LogToDebugFile("Comp Type: Memory Relative Address\n");
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this->LogToDebugFile("Mem Type: %x\n", opcode->begin_reg_cond.mem_type);
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this->LogToDebugFile("Rel Addr: %lx\n", opcode->begin_reg_cond.rel_address);
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break;
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case CompareRegisterValueType_MemoryOfsReg:
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this->LogToDebugFile("Comp Type: Memory Offset Register\n");
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this->LogToDebugFile("Mem Type: %x\n", opcode->begin_reg_cond.mem_type);
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this->LogToDebugFile("O Reg Idx: %x\n", opcode->begin_reg_cond.ofs_reg_index);
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break;
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case CompareRegisterValueType_RegisterRelAddr:
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this->LogToDebugFile("Comp Type: Register Relative Address\n");
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this->LogToDebugFile("A Reg Idx: %x\n", opcode->begin_reg_cond.addr_reg_index);
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this->LogToDebugFile("Rel Addr: %lx\n", opcode->begin_reg_cond.rel_address);
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break;
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case CompareRegisterValueType_RegisterOfsReg:
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this->LogToDebugFile("Comp Type: Register Offset Register\n");
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this->LogToDebugFile("A Reg Idx: %x\n", opcode->begin_reg_cond.addr_reg_index);
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this->LogToDebugFile("O Reg Idx: %x\n", opcode->begin_reg_cond.ofs_reg_index);
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break;
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}
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switch (opcode->begin_reg_cond.comp_type) {
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case CompareRegisterValueType_StaticValue:
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this->LogToDebugFile("Comp Type: Static Value\n");
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this->LogToDebugFile("Value: %lx\n", opcode->begin_reg_cond.value.bit64);
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break;
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case CompareRegisterValueType_OtherRegister:
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this->LogToDebugFile("Comp Type: Other Register\n");
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this->LogToDebugFile("X Reg Idx: %x\n", opcode->begin_reg_cond.other_reg_index);
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break;
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case CompareRegisterValueType_MemoryRelAddr:
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this->LogToDebugFile("Comp Type: Memory Relative Address\n");
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this->LogToDebugFile("Mem Type: %x\n", opcode->begin_reg_cond.mem_type);
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this->LogToDebugFile("Rel Addr: %lx\n", opcode->begin_reg_cond.rel_address);
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break;
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case CompareRegisterValueType_MemoryOfsReg:
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this->LogToDebugFile("Comp Type: Memory Offset Register\n");
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this->LogToDebugFile("Mem Type: %x\n", opcode->begin_reg_cond.mem_type);
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this->LogToDebugFile("O Reg Idx: %x\n", opcode->begin_reg_cond.ofs_reg_index);
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break;
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case CompareRegisterValueType_RegisterRelAddr:
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this->LogToDebugFile("Comp Type: Register Relative Address\n");
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this->LogToDebugFile("A Reg Idx: %x\n", opcode->begin_reg_cond.addr_reg_index);
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this->LogToDebugFile("Rel Addr: %lx\n", opcode->begin_reg_cond.rel_address);
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break;
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case CompareRegisterValueType_RegisterOfsReg:
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this->LogToDebugFile("Comp Type: Register Offset Register\n");
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this->LogToDebugFile("A Reg Idx: %x\n", opcode->begin_reg_cond.addr_reg_index);
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this->LogToDebugFile("O Reg Idx: %x\n", opcode->begin_reg_cond.ofs_reg_index);
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break;
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}
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break;
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case CheatVmOpcodeType_SaveRestoreRegister:
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case CheatVmOpcodeType_SaveRestoreRegister:
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this->LogToDebugFile("Opcode: Save or Restore Register\n");
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this->LogToDebugFile("Dst Idx: %x\n", opcode->save_restore_reg.dst_index);
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this->LogToDebugFile("Src Idx: %x\n", opcode->save_restore_reg.src_index);
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this->LogToDebugFile("Op Type: %d\n", opcode->save_restore_reg.op_type);
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break;
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case CheatVmOpcodeType_SaveRestoreRegisterMask:
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case CheatVmOpcodeType_SaveRestoreRegisterMask:
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this->LogToDebugFile("Opcode: Save or Restore Register Mask\n");
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this->LogToDebugFile("Op Type: %d\n", opcode->save_restore_regmask.op_type);
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for (size_t i = 0; i < NumRegisters; i++) {
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this->LogToDebugFile("Act[%02x]: %d\n", i, opcode->save_restore_regmask.should_operate[i]);
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}
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break;
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case CheatVmOpcodeType_DebugLog:
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this->LogToDebugFile("Opcode: Debug Log\n");
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this->LogToDebugFile("Bit Width: %x\n", opcode->debug_log.bit_width);
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this->LogToDebugFile("Log ID: %x\n", opcode->debug_log.log_id);
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this->LogToDebugFile("Val Type: %x\n", opcode->debug_log.val_type);
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switch (opcode->debug_log.val_type) {
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case DebugLogValueType_RegisterValue:
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this->LogToDebugFile("Val Type: Register Value\n");
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this->LogToDebugFile("X Reg Idx: %x\n", opcode->debug_log.val_reg_index);
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break;
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case DebugLogValueType_MemoryRelAddr:
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this->LogToDebugFile("Val Type: Memory Relative Address\n");
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this->LogToDebugFile("Mem Type: %x\n", opcode->debug_log.mem_type);
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this->LogToDebugFile("Rel Addr: %lx\n", opcode->debug_log.rel_address);
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break;
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case DebugLogValueType_MemoryOfsReg:
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this->LogToDebugFile("Val Type: Memory Offset Register\n");
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this->LogToDebugFile("Mem Type: %x\n", opcode->debug_log.mem_type);
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this->LogToDebugFile("O Reg Idx: %x\n", opcode->debug_log.ofs_reg_index);
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break;
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case DebugLogValueType_RegisterRelAddr:
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this->LogToDebugFile("Val Type: Register Relative Address\n");
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this->LogToDebugFile("A Reg Idx: %x\n", opcode->debug_log.addr_reg_index);
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this->LogToDebugFile("Rel Addr: %lx\n", opcode->debug_log.rel_address);
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break;
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case DebugLogValueType_RegisterOfsReg:
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this->LogToDebugFile("Val Type: Register Offset Register\n");
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this->LogToDebugFile("A Reg Idx: %x\n", opcode->debug_log.addr_reg_index);
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this->LogToDebugFile("O Reg Idx: %x\n", opcode->debug_log.ofs_reg_index);
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break;
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}
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default:
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this->LogToDebugFile("Unknown opcode: %x\n", opcode->opcode);
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break;
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@ -217,7 +263,7 @@ bool DmntCheatVm::DecodeNextOpcode(CheatVmOpcode *out) {
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*out = opcode;
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}
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};
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/* Helper function for getting instruction dwords. */
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auto GetNextDword = [&]() {
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if (this->instruction_ptr >= this->num_opcodes) {
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@ -226,11 +272,11 @@ bool DmntCheatVm::DecodeNextOpcode(CheatVmOpcode *out) {
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}
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return this->program[this->instruction_ptr++];
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};
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/* Helper function for parsing a VmInt. */
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auto GetNextVmInt = [&](const u32 bit_width) {
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VmInt val = {0};
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const u32 first_dword = GetNextDword();
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switch (bit_width) {
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case 1:
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@ -246,16 +292,16 @@ bool DmntCheatVm::DecodeNextOpcode(CheatVmOpcode *out) {
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val.bit64 = (((u64)first_dword) << 32ul) | ((u64)GetNextDword());
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break;
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}
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return val;
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};
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/* Read opcode. */
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const u32 first_dword = GetNextDword();
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if (!valid) {
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return valid;
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}
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opcode.opcode = (CheatVmOpcodeType)(((first_dword >> 28) & 0xF));
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if (opcode.opcode >= CheatVmOpcodeType_ExtendedWidth) {
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opcode.opcode = (CheatVmOpcodeType)((((u32)opcode.opcode) << 4) | ((first_dword >> 24) & 0xF));
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@ -263,7 +309,7 @@ bool DmntCheatVm::DecodeNextOpcode(CheatVmOpcode *out) {
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if (opcode.opcode >= CheatVmOpcodeType_DoubleExtendedWidth) {
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opcode.opcode = (CheatVmOpcodeType)((((u32)opcode.opcode) << 4) | ((first_dword >> 20) & 0xF));
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}
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/* detect condition start. */
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switch (opcode.opcode) {
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case CheatVmOpcodeType_BeginConditionalBlock:
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@ -275,7 +321,7 @@ bool DmntCheatVm::DecodeNextOpcode(CheatVmOpcode *out) {
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opcode.begin_conditional_block = false;
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break;
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}
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switch (opcode.opcode) {
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case CheatVmOpcodeType_StoreStatic:
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{
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@ -314,7 +360,7 @@ bool DmntCheatVm::DecodeNextOpcode(CheatVmOpcode *out) {
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/* Parse register, whether loop start or loop end. */
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opcode.ctrl_loop.start_loop = ((first_dword >> 24) & 0xF) == 0;
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opcode.ctrl_loop.reg_index = ((first_dword >> 20) & 0xF);
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/* Read number of iters if loop start. */
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if (opcode.ctrl_loop.start_loop) {
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opcode.ctrl_loop.num_iters = GetNextDword();
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@ -451,7 +497,7 @@ bool DmntCheatVm::DecodeNextOpcode(CheatVmOpcode *out) {
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opcode.begin_reg_cond.cond_type = (ConditionalComparisonType)((first_dword >> 16) & 0xF);
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opcode.begin_reg_cond.val_reg_index = ((first_dword >> 12) & 0xF);
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opcode.begin_reg_cond.comp_type = (CompareRegisterValueType)((first_dword >> 8) & 0xF);
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switch (opcode.begin_reg_cond.comp_type) {
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case CompareRegisterValueType_StaticValue:
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opcode.begin_reg_cond.value = GetNextVmInt(opcode.begin_reg_cond.bit_width);
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@ -503,6 +549,51 @@ bool DmntCheatVm::DecodeNextOpcode(CheatVmOpcode *out) {
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}
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}
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break;
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case CheatVmOpcodeType_DebugLog:
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{
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/* FFFTIX## */
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/* FFFTI0Ma aaaaaaaa */
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/* FFFTI1Mr */
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/* FFFTI2Ra aaaaaaaa */
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/* FFFTI3Rr */
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/* FFFTI4X0 */
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/* FFF = opcode 0xFFF */
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/* T = bit width. */
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/* I = log id. */
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/* X = value operand type, 0 = main/heap with relative offset, 1 = main/heap with offset register, */
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/* 2 = register with relative offset, 3 = register with offset register, 4 = register value. */
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/* M = memory type. */
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/* R = address register. */
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/* a = relative address. */
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/* r = offset register. */
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/* X = value register. */
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opcode.debug_log.bit_width = (first_dword >> 16) & 0xF;
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opcode.debug_log.log_id = ((first_dword >> 12) & 0xF);
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opcode.debug_log.val_type = (DebugLogValueType)((first_dword >> 8) & 0xF);
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switch (opcode.debug_log.val_type) {
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case DebugLogValueType_RegisterValue:
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opcode.debug_log.val_reg_index = ((first_dword >> 4) & 0xF);
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break;
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case DebugLogValueType_MemoryRelAddr:
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opcode.debug_log.mem_type = (MemoryAccessType)((first_dword >> 4) & 0xF);
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opcode.debug_log.rel_address = (((u64)(first_dword & 0xF) << 32ul) | ((u64)GetNextDword()));
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break;
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case DebugLogValueType_MemoryOfsReg:
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opcode.debug_log.mem_type = (MemoryAccessType)((first_dword >> 4) & 0xF);
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opcode.debug_log.ofs_reg_index = (first_dword & 0xF);
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break;
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case DebugLogValueType_RegisterRelAddr:
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opcode.debug_log.addr_reg_index = ((first_dword >> 4) & 0xF);
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opcode.debug_log.rel_address = (((u64)(first_dword & 0xF) << 32ul) | ((u64)GetNextDword()));
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break;
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case DebugLogValueType_RegisterOfsReg:
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opcode.debug_log.addr_reg_index = ((first_dword >> 4) & 0xF);
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opcode.debug_log.ofs_reg_index = (first_dword & 0xF);
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break;
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}
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}
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break;
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case CheatVmOpcodeType_ExtendedWidth:
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case CheatVmOpcodeType_DoubleExtendedWidth:
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default:
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@ -510,7 +601,7 @@ bool DmntCheatVm::DecodeNextOpcode(CheatVmOpcode *out) {
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valid = false;
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break;
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}
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/* End decoding. */
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return valid;
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}
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@ -519,7 +610,7 @@ void DmntCheatVm::SkipConditionalBlock() {
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if (this->condition_depth > 0) {
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/* We want to continue until we're out of the current block. */
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const size_t desired_depth = this->condition_depth - 1;
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CheatVmOpcode skip_opcode;
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while (this->condition_depth > desired_depth && this->DecodeNextOpcode(&skip_opcode)) {
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/* Decode instructions until we see end of the current conditional block. */
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@ -527,7 +618,7 @@ void DmntCheatVm::SkipConditionalBlock() {
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/* Gateway currently checks for "0x2" instead of "0x20000000" */
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/* In addition, they do a linear scan instead of correctly decoding opcodes. */
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/* This causes issues if "0x2" appears as an immediate in the conditional block... */
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/* We also support nesting of conditional blocks, and Gateway does not. */
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if (skip_opcode.begin_conditional_block) {
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this->condition_depth++;
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@ -585,7 +676,7 @@ void DmntCheatVm::ResetState() {
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bool DmntCheatVm::LoadProgram(const CheatEntry *cheats, size_t num_cheats) {
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/* Reset opcode count. */
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this->num_opcodes = 0;
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for (size_t i = 0; i < num_cheats; i++) {
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if (cheats[i].enabled) {
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/* Bounds check. */
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@ -593,34 +684,34 @@ bool DmntCheatVm::LoadProgram(const CheatEntry *cheats, size_t num_cheats) {
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this->num_opcodes = 0;
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return false;
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}
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for (size_t n = 0; n < cheats[i].definition.num_opcodes; n++) {
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this->program[this->num_opcodes++] = cheats[i].definition.opcodes[n];
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}
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}
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}
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return true;
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}
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void DmntCheatVm::Execute(const CheatProcessMetadata *metadata) {
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CheatVmOpcode cur_opcode;
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u64 kDown = 0;
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/* Get Keys down. */
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HidManagement::GetKeysDown(&kDown);
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this->OpenDebugLogFile();
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ON_SCOPE_EXIT { this->CloseDebugLogFile(); };
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this->LogToDebugFile("Started VM execution.\n");
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this->LogToDebugFile("Main NSO: %012lx\n", metadata->main_nso_extents.base);
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this->LogToDebugFile("Heap: %012lx\n", metadata->main_nso_extents.base);
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this->LogToDebugFile("Keys Down: %08x\n", (u32)(kDown & 0x0FFFFFFF));
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/* Clear VM state. */
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this->ResetState();
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/* Loop until program finishes. */
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while (this->DecodeNextOpcode(&cur_opcode)) {
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this->LogToDebugFile("Instruction Ptr: %04x\n", (u32)this->instruction_ptr);
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@ -633,12 +724,12 @@ void DmntCheatVm::Execute(const CheatProcessMetadata *metadata) {
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this->LogToDebugFile("SavedRegs[%02x]: %016lx\n", i, this->saved_values[i]);
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}
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this->LogOpcode(&cur_opcode);
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/* Increment conditional depth, if relevant. */
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if (cur_opcode.begin_conditional_block) {
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this->condition_depth++;
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}
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switch (cur_opcode.opcode) {
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case CheatVmOpcodeType_StoreStatic:
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{
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@ -814,10 +905,10 @@ void DmntCheatVm::Execute(const CheatProcessMetadata *metadata) {
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case CheatVmOpcodeType_PerformArithmeticRegister:
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{
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const u64 operand_1_value = this->registers[cur_opcode.perform_math_reg.src_reg_1_index];
|
||||
const u64 operand_2_value = cur_opcode.perform_math_reg.has_immediate ?
|
||||
const u64 operand_2_value = cur_opcode.perform_math_reg.has_immediate ?
|
||||
GetVmInt(cur_opcode.perform_math_reg.value, cur_opcode.perform_math_reg.bit_width) :
|
||||
this->registers[cur_opcode.perform_math_reg.src_reg_2_index];
|
||||
|
||||
|
||||
u64 res_val = 0;
|
||||
/* Do requested math. */
|
||||
switch (cur_opcode.perform_math_reg.math_type) {
|
||||
|
|
@ -852,8 +943,8 @@ void DmntCheatVm::Execute(const CheatProcessMetadata *metadata) {
|
|||
res_val = operand_1_value;
|
||||
break;
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
/* Apply bit width. */
|
||||
switch (cur_opcode.perform_math_reg.bit_width) {
|
||||
case 1:
|
||||
|
|
@ -869,7 +960,7 @@ void DmntCheatVm::Execute(const CheatProcessMetadata *metadata) {
|
|||
res_val = static_cast<u64>(res_val);
|
||||
break;
|
||||
}
|
||||
|
||||
|
||||
/* Save to register. */
|
||||
this->registers[cur_opcode.perform_math_reg.dst_reg_index] = res_val;
|
||||
}
|
||||
|
|
@ -899,7 +990,7 @@ void DmntCheatVm::Execute(const CheatProcessMetadata *metadata) {
|
|||
dst_address = GetCheatProcessAddress(metadata, cur_opcode.str_register.mem_type, this->registers[cur_opcode.str_register.addr_reg_index] + cur_opcode.str_register.rel_address);
|
||||
break;
|
||||
}
|
||||
|
||||
|
||||
/* Write value to memory. Write only on valid bitwidth. */
|
||||
switch (cur_opcode.str_register.bit_width) {
|
||||
case 1:
|
||||
|
|
@ -909,7 +1000,7 @@ void DmntCheatVm::Execute(const CheatProcessMetadata *metadata) {
|
|||
DmntCheatManager::WriteCheatProcessMemoryForVm(dst_address, &dst_value, cur_opcode.str_register.bit_width);
|
||||
break;
|
||||
}
|
||||
|
||||
|
||||
/* Increment register if relevant. */
|
||||
if (cur_opcode.str_register.increment_reg) {
|
||||
this->registers[cur_opcode.str_register.addr_reg_index] += cur_opcode.str_register.bit_width;
|
||||
|
|
@ -934,7 +1025,7 @@ void DmntCheatVm::Execute(const CheatProcessMetadata *metadata) {
|
|||
src_value = static_cast<u64>(this->registers[cur_opcode.begin_reg_cond.val_reg_index] & 0xFFFFFFFFFFFFFFFFul);
|
||||
break;
|
||||
}
|
||||
|
||||
|
||||
/* Read value from memory. */
|
||||
u64 cond_value = 0;
|
||||
if (cur_opcode.begin_reg_cond.comp_type == CompareRegisterValueType_StaticValue) {
|
||||
|
|
@ -981,7 +1072,7 @@ void DmntCheatVm::Execute(const CheatProcessMetadata *metadata) {
|
|||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/* Check against condition. */
|
||||
bool cond_met = false;
|
||||
switch (cur_opcode.begin_reg_cond.cond_type) {
|
||||
|
|
@ -1004,7 +1095,7 @@ void DmntCheatVm::Execute(const CheatProcessMetadata *metadata) {
|
|||
cond_met = src_value != cond_value;
|
||||
break;
|
||||
}
|
||||
|
||||
|
||||
/* Skip conditional block if condition not met. */
|
||||
if (!cond_met) {
|
||||
this->SkipConditionalBlock();
|
||||
|
|
@ -1062,6 +1153,57 @@ void DmntCheatVm::Execute(const CheatProcessMetadata *metadata) {
|
|||
}
|
||||
}
|
||||
break;
|
||||
case CheatVmOpcodeType_DebugLog:
|
||||
{
|
||||
/* Read value from memory. */
|
||||
u64 log_value = 0;
|
||||
if (cur_opcode.debug_log.val_type == DebugLogValueType_RegisterValue) {
|
||||
switch (cur_opcode.debug_log.bit_width) {
|
||||
case 1:
|
||||
log_value = static_cast<u8>(this->registers[cur_opcode.debug_log.val_reg_index] & 0xFFul);
|
||||
break;
|
||||
case 2:
|
||||
log_value = static_cast<u16>(this->registers[cur_opcode.debug_log.val_reg_index] & 0xFFFFul);
|
||||
break;
|
||||
case 4:
|
||||
log_value = static_cast<u32>(this->registers[cur_opcode.debug_log.val_reg_index] & 0xFFFFFFFFul);
|
||||
break;
|
||||
case 8:
|
||||
log_value = static_cast<u64>(this->registers[cur_opcode.debug_log.val_reg_index] & 0xFFFFFFFFFFFFFFFFul);
|
||||
break;
|
||||
}
|
||||
} else {
|
||||
u64 val_address = 0;
|
||||
switch (cur_opcode.debug_log.val_type) {
|
||||
case DebugLogValueType_MemoryRelAddr:
|
||||
val_address = GetCheatProcessAddress(metadata, cur_opcode.debug_log.mem_type, cur_opcode.debug_log.rel_address);
|
||||
break;
|
||||
case DebugLogValueType_MemoryOfsReg:
|
||||
val_address = GetCheatProcessAddress(metadata, cur_opcode.debug_log.mem_type, this->registers[cur_opcode.debug_log.ofs_reg_index]);
|
||||
break;
|
||||
case DebugLogValueType_RegisterRelAddr:
|
||||
val_address = this->registers[cur_opcode.debug_log.addr_reg_index] + cur_opcode.debug_log.rel_address;
|
||||
break;
|
||||
case DebugLogValueType_RegisterOfsReg:
|
||||
val_address = this->registers[cur_opcode.debug_log.addr_reg_index] + this->registers[cur_opcode.debug_log.ofs_reg_index];
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
switch (cur_opcode.debug_log.bit_width) {
|
||||
case 1:
|
||||
case 2:
|
||||
case 4:
|
||||
case 8:
|
||||
DmntCheatManager::ReadCheatProcessMemoryForVm(val_address, &log_value, cur_opcode.debug_log.bit_width);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* Log value. */
|
||||
this->DebugLog(cur_opcode.debug_log.log_id, log_value);
|
||||
}
|
||||
break;
|
||||
default:
|
||||
/* By default, we do a no-op. */
|
||||
break;
|
||||
|
|
|
|||
|
|
@ -49,6 +49,9 @@ enum CheatVmOpcodeType : u32 {
|
|||
/* This is a meta entry, and not a real opcode. */
|
||||
/* This is to facilitate multi-nybble instruction decoding. */
|
||||
CheatVmOpcodeType_DoubleExtendedWidth = 0xF0,
|
||||
|
||||
/* Double-extended width opcodes. */
|
||||
CheatVmOpcodeType_DebugLog = 0xFFF,
|
||||
};
|
||||
|
||||
enum MemoryAccessType : u32 {
|
||||
|
|
@ -106,6 +109,14 @@ enum SaveRestoreRegisterOpType : u32 {
|
|||
SaveRestoreRegisterOpType_ClearRegs = 3,
|
||||
};
|
||||
|
||||
enum DebugLogValueType : u32 {
|
||||
DebugLogValueType_MemoryRelAddr = 0,
|
||||
DebugLogValueType_MemoryOfsReg = 1,
|
||||
DebugLogValueType_RegisterRelAddr = 2,
|
||||
DebugLogValueType_RegisterOfsReg = 3,
|
||||
DebugLogValueType_RegisterValue = 4,
|
||||
};
|
||||
|
||||
union VmInt {
|
||||
u8 bit8;
|
||||
u16 bit16;
|
||||
|
|
@ -215,6 +226,17 @@ struct SaveRestoreRegisterMaskOpcode {
|
|||
bool should_operate[0x10];
|
||||
};
|
||||
|
||||
struct DebugLogOpcode {
|
||||
u32 bit_width;
|
||||
u32 log_id;
|
||||
DebugLogValueType val_type;
|
||||
MemoryAccessType mem_type;
|
||||
u32 addr_reg_index;
|
||||
u32 val_reg_index;
|
||||
u32 ofs_reg_index;
|
||||
u64 rel_address;
|
||||
};
|
||||
|
||||
struct CheatVmOpcode {
|
||||
CheatVmOpcodeType opcode;
|
||||
bool begin_conditional_block;
|
||||
|
|
@ -233,6 +255,7 @@ struct CheatVmOpcode {
|
|||
BeginRegisterConditionalOpcode begin_reg_cond;
|
||||
SaveRestoreRegisterOpcode save_restore_reg;
|
||||
SaveRestoreRegisterMaskOpcode save_restore_regmask;
|
||||
DebugLogOpcode debug_log;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -254,6 +277,9 @@ class DmntCheatVm {
|
|||
void SkipConditionalBlock();
|
||||
void ResetState();
|
||||
|
||||
/* For implementing the DebugLog opcode. */
|
||||
void DebugLog(u32 log_id, u64 value);
|
||||
|
||||
/* For debugging. These will be IFDEF'd out normally. */
|
||||
void OpenDebugLogFile();
|
||||
void CloseDebugLogFile();
|
||||
|
|
|
|||
Loading…
Reference in a new issue