mirror of
https://github.com/Atmosphere-NX/Atmosphere
synced 2024-12-22 20:31:14 +00:00
fusee/sept: build fixes
This commit is contained in:
Michael Scire
parent
a35a30efcd
commit
ec398dc612
7 changed files with 145 additions and 128 deletions
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@ -14,9 +14,9 @@
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <stdint.h>
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#include "cluster.h"
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#include "flow.h"
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#include "sysreg.h"
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@ -37,40 +37,46 @@ static bool is_soc_mariko() {
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static void cluster_enable_power(uint32_t regulator) {
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switch (regulator) {
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case 0: /* Regulator_Max77621 */
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uint8_t val = 0;
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i2c_query(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_AME_GPIO, &val, 1);
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val &= 0xDF;
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i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_AME_GPIO, &val, 1);
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val = 0x09;
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i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_GPIO5, &val, 1);
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val = 0x20;
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i2c_send(I2C_5, MAX77621_CPU_I2C_ADDR, 0x02, &val, 1);
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val = 0x8D;
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i2c_send(I2C_5, MAX77621_CPU_I2C_ADDR, 0x03, &val, 1);
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val = 0xB7;
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i2c_send(I2C_5, MAX77621_CPU_I2C_ADDR, 0x00, &val, 1);
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val = 0xB7;
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i2c_send(I2C_5, MAX77621_CPU_I2C_ADDR, 0x01, &val, 1);
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{
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uint8_t val = 0;
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i2c_query(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_AME_GPIO, &val, 1);
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val &= 0xDF;
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i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_AME_GPIO, &val, 1);
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val = 0x09;
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i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_GPIO5, &val, 1);
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val = 0x20;
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i2c_send(I2C_5, MAX77621_CPU_I2C_ADDR, 0x02, &val, 1);
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val = 0x8D;
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i2c_send(I2C_5, MAX77621_CPU_I2C_ADDR, 0x03, &val, 1);
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val = 0xB7;
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i2c_send(I2C_5, MAX77621_CPU_I2C_ADDR, 0x00, &val, 1);
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val = 0xB7;
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i2c_send(I2C_5, MAX77621_CPU_I2C_ADDR, 0x01, &val, 1);
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}
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break;
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case 1: /* Regulator_Max77812PhaseConfiguration31 */
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uint8_t val = 0;
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i2c_query(I2C_5, MAX77812_PHASE31_CPU_I2C_ADDR, MAX77812_REG_EN_CTRL, &val, 1);
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if (val) {
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val |= 0x40;
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i2c_send(I2C_5, MAX77812_PHASE31_CPU_I2C_ADDR, MAX77812_REG_EN_CTRL, &val, 1);
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{
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uint8_t val = 0;
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i2c_query(I2C_5, MAX77812_PHASE31_CPU_I2C_ADDR, MAX77812_REG_EN_CTRL, &val, 1);
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if (val) {
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val |= 0x40;
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i2c_send(I2C_5, MAX77812_PHASE31_CPU_I2C_ADDR, MAX77812_REG_EN_CTRL, &val, 1);
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}
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val = 0x6E;
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i2c_send(I2C_5, MAX77812_PHASE31_CPU_I2C_ADDR, MAX77812_REG_M4_VOUT, &val, 1);
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}
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val = 0x6E;
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i2c_send(I2C_5, MAX77812_PHASE31_CPU_I2C_ADDR, MAX77812_REG_M4_VOUT, &val, 1);
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break;
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case 2: /* Regulator_Max77812PhaseConfiguration211 */
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uint8_t val = 0;
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i2c_query(I2C_5, MAX77812_PHASE211_CPU_I2C_ADDR, MAX77812_REG_EN_CTRL, &val, 1);
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if (val) {
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val |= 0x40;
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i2c_send(I2C_5, MAX77812_PHASE211_CPU_I2C_ADDR, MAX77812_REG_EN_CTRL, &val, 1);
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{
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uint8_t val = 0;
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i2c_query(I2C_5, MAX77812_PHASE211_CPU_I2C_ADDR, MAX77812_REG_EN_CTRL, &val, 1);
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if (val) {
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val |= 0x40;
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i2c_send(I2C_5, MAX77812_PHASE211_CPU_I2C_ADDR, MAX77812_REG_EN_CTRL, &val, 1);
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}
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val = 0x6E;
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i2c_send(I2C_5, MAX77812_PHASE211_CPU_I2C_ADDR, MAX77812_REG_M4_VOUT, &val, 1);
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}
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val = 0x6E;
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i2c_send(I2C_5, MAX77812_PHASE211_CPU_I2C_ADDR, MAX77812_REG_M4_VOUT, &val, 1);
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break;
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default: return;
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}
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@ -78,7 +84,7 @@ static void cluster_enable_power(uint32_t regulator) {
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static void cluster_pmc_enable_partition(uint32_t part, uint32_t toggle) {
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volatile tegra_pmc_t *pmc = pmc_get_regs();
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/* Check if the partition has already been turned on. */
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if (pmc->pwrgate_status & part) {
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return;
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@ -110,13 +116,13 @@ static void cluster_pmc_enable_partition(uint32_t part, uint32_t toggle) {
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void cluster_boot_cpu0(uint32_t entry) {
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volatile tegra_car_t *car = car_get_regs();
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bool is_mariko = is_soc_mariko();
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/* Set ACTIVE_CLUSER to FAST. */
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FLOW_CTLR_BPMP_CLUSTER_CONTROL_0 &= 0xFFFFFFFE;
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/* Enable VddCpu. */
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cluster_enable_power(is_mariko ? fuse_get_regulator() : 0);
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if (!(car->pllx_base & 0x40000000)) {
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car->pllx_misc3 &= 0xFFFFFFF7;
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udelay(2);
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@ -127,7 +133,7 @@ void cluster_boot_cpu0(uint32_t entry) {
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car->pllx_misc = ((car->pllx_misc & 0xFFFBFFFF) | 0x40000);
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car->pllx_base = 0x40404E02;
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}
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while (!(car->pllx_base & 0x8000000)) {
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/* Wait. */
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}
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@ -139,7 +145,7 @@ void cluster_boot_cpu0(uint32_t entry) {
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car->cclk_brst_pol = 0x20008888;
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car->super_cclk_div = 0x80000000;
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car->clk_enb_v_set = 1;
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/* Reboot CORESIGHT. */
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clkrst_reboot(CARDEVICE_CORESIGHT);
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@ -148,10 +154,10 @@ void cluster_boot_cpu0(uint32_t entry) {
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/* Enable CPU rail. */
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cluster_pmc_enable_partition(1, 0);
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/* Enable cluster 0 non-CPU. */
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cluster_pmc_enable_partition(0x8000, 15);
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/* Enable CE0. */
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cluster_pmc_enable_partition(0x4000, 14);
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@ -166,7 +172,7 @@ void cluster_boot_cpu0(uint32_t entry) {
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/* Set reset vector. */
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SB_AA64_RESET_LOW_0 = (entry | 1);
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SB_AA64_RESET_HIGH_0 = 0;
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/* Non-secure reset vector write disable. */
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SB_CSR_0 = 2;
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(void)SB_CSR_0;
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@ -174,15 +180,15 @@ void cluster_boot_cpu0(uint32_t entry) {
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/* Set CPU_STRICT_TZ_APERTURE_CHECK. */
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/* NOTE: This breaks Exosphère. */
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/* MAKE_MC_REG(MC_TZ_SECURITY_CTRL) = 1; */
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/* Clear MSELECT reset. */
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rst_disable(CARDEVICE_MSELECT);
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if (!is_mariko) {
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/* Clear NONCPU reset. */
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car->rst_cpug_cmplx_clr = 0x20000000;
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}
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/* Clear CPU{0} POR and CORE, CX0, L2, and DBG reset.*/
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car->rst_cpug_cmplx_clr = 0x41010001;
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}
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@ -470,7 +470,7 @@ uint64_t fuse_get_device_id(void);
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uint32_t fuse_get_dram_id(void);
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uint32_t fuse_get_hardware_type_with_firmware_check(uint32_t target_firmware);
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uint32_t fuse_get_hardware_type(void);
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uint32_t fuse_get_retail_type(void);
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uint32_t fuse_get_hardware_state(void);
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void fuse_get_hardware_info(void *dst);
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bool fuse_is_new_format(void);
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uint32_t fuse_get_device_unique_key_generation(void);
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@ -15,7 +15,7 @@
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*/
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#include <stdio.h>
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#include "lib/log.h"
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#include "../../../fusee/common/log.h"
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#include "key_derivation.h"
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#include "masterkey.h"
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#include "se.h"
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@ -229,7 +229,7 @@ int derive_nx_keydata_mariko(uint32_t target_firmware) {
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decrypt_data_into_keyslot(0xA, 0xE, devicekey_4x_seed, 0x10);
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decrypt_data_into_keyslot(0x7, 0xC, &master_kek_seeds_mariko[target_firmware - MASTERKEY_REVISION_600_610], 0x10);
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decrypt_data_into_keyslot(0x7, 0x7, masterkey_seed, 0x10);
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/* Setup master key revision, derive older master keys for use. */
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return mkey_detect_revision(fuse_get_hardware_state() != 0);
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}
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@ -691,7 +691,7 @@ uint32_t nxboot_main(void) {
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FILE *boot0, *pk2file;
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void *exosphere_memaddr;
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exo_emummc_config_t exo_emummc_cfg;
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/* Configure emummc or mount the real NAND. */
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if (!nxboot_configure_emummc(&exo_emummc_cfg)) {
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emummc = NULL;
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@ -771,9 +771,11 @@ uint32_t nxboot_main(void) {
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fatal_error("[NXBOOT] Failed to open boot0: %s!\n", strerror(errno));
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}
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if (is_mariko) {
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/* TODO*/
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if (package1_read_and_parse_boot0_mariko(&package1loader, &package1loader_size, boot0) == -1) {
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fatal_error("[NXBOOT] Couldn't parse boot0: %s!\n", strerror(errno));
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}
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} else {
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if (package1_read_and_parse_boot0(&package1loader, &package1loader_size, g_keyblobs, &available_revision, boot0) == -1) {
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if (package1_read_and_parse_boot0_erista(&package1loader, &package1loader_size, g_keyblobs, &available_revision, boot0) == -1) {
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fatal_error("[NXBOOT] Couldn't parse boot0: %s!\n", strerror(errno));
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}
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}
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@ -782,12 +784,15 @@ uint32_t nxboot_main(void) {
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/* Find the system's target firmware. */
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uint32_t target_firmware = nxboot_get_target_firmware(package1loader);
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if (!target_firmware)
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if (!target_firmware) {
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fatal_error("[NXBOOT] Failed to detect target firmware!\n");
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else
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} else {
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print(SCREEN_LOG_LEVEL_INFO, "[NXBOOT] Detected target firmware %ld!\n", target_firmware);
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}
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/* Handle TSEC and Sept (Erista only). */
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uint8_t tsec_key[0x10] = {0};
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uint8_t tsec_root_keys[0x20][0x10] = {0};
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if (!is_mariko) {
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/* Read the TSEC firmware from a file, otherwise from PK1L. */
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if (loader_ctx->tsecfw_path[0] != '\0') {
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@ -859,8 +864,6 @@ uint32_t nxboot_main(void) {
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print(SCREEN_LOG_LEVEL_INFO, "[NXBOOT] Loaded firmware from eMMC...\n");
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/* Get the TSEC keys. */
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uint8_t tsec_key[0x10] = {0};
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uint8_t tsec_root_keys[0x20][0x10] = {0};
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if (target_firmware >= ATMOSPHERE_TARGET_FIRMWARE_7_0_0) {
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/* Detect whether we need to run sept-secondary in order to derive keys. */
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if (!get_and_clear_has_run_sept()) {
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@ -958,6 +961,8 @@ uint32_t nxboot_main(void) {
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} else {
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if (is_mariko) {
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/* TODO */
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warmboot_fw = NULL;
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warmboot_fw_size = 0;
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} else {
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/* Use Atmosphere's warmboot firmware implementation. */
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warmboot_fw_size = warmboot_bin_size;
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@ -1000,7 +1005,7 @@ uint32_t nxboot_main(void) {
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pmc->scratch1 = (uint32_t)warmboot_memaddr;
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}
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}
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/* Handle warmboot security check. */
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if (is_mariko) {
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/* TODO */
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@ -1125,7 +1130,7 @@ uint32_t nxboot_main(void) {
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rst_enable(CARDEVICE_AHBDMA);
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rst_enable(CARDEVICE_APBDMA);
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}
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/* Return the memory address for booting CPU0. */
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return (uint32_t)exosphere_memaddr;
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}
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@ -38,7 +38,7 @@ static void setup_exception_vectors(void) {
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static void mbist_workaround(void)
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{
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volatile tegra_car_t *car = car_get_regs();
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car->clk_source_sor1 = ((car->clk_source_sor1 | 0x8000) & 0xFFFFBFFF);
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car->plld_base |= 0x40800000u;
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car->rst_dev_y_clr = 0x40;
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@ -57,7 +57,7 @@ static void mbist_workaround(void)
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MAKE_I2S_REG(0x388) &= 0xFFFFFFFE;
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MAKE_I2S_REG(0x4A0) |= 0x400;
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MAKE_I2S_REG(0x488) &= 0xFFFFFFFE;
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MAKE_DI_REG(DC_COM_DSC_TOP_CTL) |= 4;
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MAKE_VIC_REG(0x8C) = 0xFFFFFFFF;
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udelay(3);
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@ -66,7 +66,7 @@ static void mbist_workaround(void)
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car->rst_dev_y_set = 0x40;
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car->rst_dev_l_set = 0x18000000;
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car->rst_dev_x_set = 0x40000;
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/* Clock out enables. */
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car->clk_out_enb_h = 0xC0;
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car->clk_out_enb_l = 0x80000130;
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@ -75,14 +75,14 @@ static void mbist_workaround(void)
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car->clk_out_enb_w = 0x402000FC;
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car->clk_out_enb_x = 0x23000780;
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car->clk_out_enb_y = 0x300;
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/* LVL2 clock gate overrides. */
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car->lvl2_clk_gate_ovra = 0;
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car->lvl2_clk_gate_ovrb = 0;
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car->lvl2_clk_gate_ovrc = 0;
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car->lvl2_clk_gate_ovrd = 0;
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car->lvl2_clk_gate_ovre = 0;
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/* Configure clock sources. */
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car->plld_base &= 0x1F7FFFFF;
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car->clk_source_sor1 &= 0xFFFF3FFF;
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@ -93,7 +93,7 @@ static void mbist_workaround(void)
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static int tsec_dma_wait_idle()
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{
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volatile tegra_tsec_t *tsec = tsec_get_regs();
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volatile tegra_tsec_t *tsec = tsec_get_regs();
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uint32_t timeout = (get_time_ms() + 10000);
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while (!(tsec->TSEC_FALCON_DMATRFCMD & 2))
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@ -101,13 +101,13 @@ static int tsec_dma_wait_idle()
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if (get_time_ms() > timeout)
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return 0;
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}
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return 1;
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}
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static int tsec_dma_phys_to_flcn(bool is_imem, uint32_t flcn_offset, uint32_t phys_offset)
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{
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volatile tegra_tsec_t *tsec = tsec_get_regs();
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volatile tegra_tsec_t *tsec = tsec_get_regs();
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uint32_t cmd = 0;
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if (!is_imem)
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@ -123,16 +123,16 @@ static int tsec_dma_phys_to_flcn(bool is_imem, uint32_t flcn_offset, uint32_t ph
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}
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static int tsec_kfuse_wait_ready()
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{
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{
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uint32_t timeout = (get_time_ms() + 10000);
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/* Wait for STATE_DONE. */
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while (!(KFUSE_STATE & 0x10000))
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{
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if (get_time_ms() > timeout)
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return 0;
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}
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/* Check for STATE_CRCPASS. */
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if (!(KFUSE_STATE & 0x20000))
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return 0;
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@ -143,7 +143,7 @@ static int tsec_kfuse_wait_ready()
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int load_tsec_fw(void) {
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volatile uint32_t* tsec_fw = (volatile uint32_t*)0x40010F00;
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const uint32_t tsec_fw_length = MAKE_REG32(0x40010EFC);
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volatile tegra_tsec_t *tsec = tsec_get_regs();
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/* Enable clocks. */
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@ -153,7 +153,7 @@ int load_tsec_fw(void) {
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clkrst_reboot(CARDEVICE_SOR0);
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clkrst_reboot(CARDEVICE_SOR1);
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clkrst_reboot(CARDEVICE_KFUSE);
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||||
|
||||
/* Make sure KFUSE is ready. */
|
||||
if (!tsec_kfuse_wait_ready())
|
||||
{
|
||||
|
|
@ -164,16 +164,16 @@ int load_tsec_fw(void) {
|
|||
clkrst_disable(CARDEVICE_SOR_SAFE);
|
||||
clkrst_disable(CARDEVICE_TSEC);
|
||||
clkrst_disable(CARDEVICE_HOST1X);
|
||||
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
|
||||
/* Configure Falcon. */
|
||||
tsec->TSEC_FALCON_DMACTL = 0;
|
||||
tsec->TSEC_FALCON_IRQMSET = 0xFFF2;
|
||||
tsec->TSEC_FALCON_IRQDEST = 0xFFF0;
|
||||
tsec->TSEC_FALCON_ITFEN = 3;
|
||||
|
||||
|
||||
/* Make sure the DMA block is idle. */
|
||||
if (!tsec_dma_wait_idle())
|
||||
{
|
||||
|
|
@ -184,10 +184,10 @@ int load_tsec_fw(void) {
|
|||
clkrst_disable(CARDEVICE_SOR_SAFE);
|
||||
clkrst_disable(CARDEVICE_TSEC);
|
||||
clkrst_disable(CARDEVICE_HOST1X);
|
||||
|
||||
|
||||
return -2;
|
||||
}
|
||||
|
||||
|
||||
/* Load firmware. */
|
||||
tsec->TSEC_FALCON_DMATRFBASE = (uint32_t)tsec_fw >> 8;
|
||||
for (uint32_t addr = 0; addr < tsec_fw_length; addr += 0x100)
|
||||
|
|
@ -201,57 +201,57 @@ int load_tsec_fw(void) {
|
|||
clkrst_disable(CARDEVICE_SOR_SAFE);
|
||||
clkrst_disable(CARDEVICE_TSEC);
|
||||
clkrst_disable(CARDEVICE_HOST1X);
|
||||
|
||||
|
||||
return -3;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/* Write magic value to HOST1X scratch register. */
|
||||
MAKE_HOST1X_REG(0x3300) = 0x34C2E1DA;
|
||||
|
||||
|
||||
/* Execute firmware. */
|
||||
tsec->TSEC_FALCON_MAILBOX1 = 0;
|
||||
tsec->TSEC_FALCON_MAILBOX0 = 1;
|
||||
tsec->TSEC_FALCON_BOOTVEC = 0;
|
||||
tsec->TSEC_FALCON_CPUCTL = 2;
|
||||
|
||||
|
||||
while (true) {
|
||||
/* Yield to Nintendo's TSEC firmware. */
|
||||
}
|
||||
}
|
||||
|
||||
int main(void) {
|
||||
int main(void) {
|
||||
/* Setup vectors */
|
||||
setup_exception_vectors();
|
||||
|
||||
volatile tegra_pmc_t *pmc = pmc_get_regs();
|
||||
volatile tegra_car_t *car = car_get_regs();
|
||||
|
||||
|
||||
/* Clear the boot reason to avoid problems later */
|
||||
pmc->scratch200 = 0;
|
||||
pmc->reset_status = 0;
|
||||
|
||||
pmc->rst_status = 0;
|
||||
|
||||
//AHB_AHB_SPARE_REG_0 &= 0xFFFFFF9F;
|
||||
//pmc->scratch49 = (((pmc->scratch49 >> 1) << 1) & 0xFFFFFFFD);
|
||||
|
||||
|
||||
/* Apply the memory built-in self test workaround. */
|
||||
mbist_workaround();
|
||||
|
||||
|
||||
/* Reboot SE. */
|
||||
clkrst_reboot(CARDEVICE_SE);
|
||||
|
||||
|
||||
/* Initialize the fuse driver. */
|
||||
fuse_init();
|
||||
|
||||
|
||||
/* Don't bother checking SKU, fuses, or bootloader version. */
|
||||
mc_enable_for_tsec();
|
||||
|
||||
|
||||
/* 7.0.0 package1ldr holds I2C5 in reset, clears SYS clock. */
|
||||
car->clk_source_sys = 0;
|
||||
rst_enable(CARDEVICE_I2C5);
|
||||
|
||||
|
||||
load_tsec_fw();
|
||||
|
||||
|
||||
while (true) { }
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -13,7 +13,7 @@ PHDRS
|
|||
MEMORY
|
||||
{
|
||||
NULL : ORIGIN = 0x00000000, LENGTH = 0x1000
|
||||
main : ORIGIN = 0x40010000, LENGTH = 0x20000
|
||||
main : ORIGIN = 0x40010000, LENGTH = 0x28000
|
||||
low_iram : ORIGIN = 0x40003000, LENGTH = 0x8000
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -14,9 +14,9 @@
|
|||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
|
||||
#include "cluster.h"
|
||||
#include "flow.h"
|
||||
#include "sysreg.h"
|
||||
|
|
@ -37,40 +37,46 @@ static bool is_soc_mariko() {
|
|||
static void cluster_enable_power(uint32_t regulator) {
|
||||
switch (regulator) {
|
||||
case 0: /* Regulator_Max77621 */
|
||||
uint8_t val = 0;
|
||||
i2c_query(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_AME_GPIO, &val, 1);
|
||||
val &= 0xDF;
|
||||
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_AME_GPIO, &val, 1);
|
||||
val = 0x09;
|
||||
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_GPIO5, &val, 1);
|
||||
val = 0x20;
|
||||
i2c_send(I2C_5, MAX77621_CPU_I2C_ADDR, 0x02, &val, 1);
|
||||
val = 0x8D;
|
||||
i2c_send(I2C_5, MAX77621_CPU_I2C_ADDR, 0x03, &val, 1);
|
||||
val = 0xB7;
|
||||
i2c_send(I2C_5, MAX77621_CPU_I2C_ADDR, 0x00, &val, 1);
|
||||
val = 0xB7;
|
||||
i2c_send(I2C_5, MAX77621_CPU_I2C_ADDR, 0x01, &val, 1);
|
||||
{
|
||||
uint8_t val = 0;
|
||||
i2c_query(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_AME_GPIO, &val, 1);
|
||||
val &= 0xDF;
|
||||
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_AME_GPIO, &val, 1);
|
||||
val = 0x09;
|
||||
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_GPIO5, &val, 1);
|
||||
val = 0x20;
|
||||
i2c_send(I2C_5, MAX77621_CPU_I2C_ADDR, 0x02, &val, 1);
|
||||
val = 0x8D;
|
||||
i2c_send(I2C_5, MAX77621_CPU_I2C_ADDR, 0x03, &val, 1);
|
||||
val = 0xB7;
|
||||
i2c_send(I2C_5, MAX77621_CPU_I2C_ADDR, 0x00, &val, 1);
|
||||
val = 0xB7;
|
||||
i2c_send(I2C_5, MAX77621_CPU_I2C_ADDR, 0x01, &val, 1);
|
||||
}
|
||||
break;
|
||||
case 1: /* Regulator_Max77812PhaseConfiguration31 */
|
||||
uint8_t val = 0;
|
||||
i2c_query(I2C_5, MAX77812_PHASE31_CPU_I2C_ADDR, MAX77812_REG_EN_CTRL, &val, 1);
|
||||
if (val) {
|
||||
val |= 0x40;
|
||||
i2c_send(I2C_5, MAX77812_PHASE31_CPU_I2C_ADDR, MAX77812_REG_EN_CTRL, &val, 1);
|
||||
{
|
||||
uint8_t val = 0;
|
||||
i2c_query(I2C_5, MAX77812_PHASE31_CPU_I2C_ADDR, MAX77812_REG_EN_CTRL, &val, 1);
|
||||
if (val) {
|
||||
val |= 0x40;
|
||||
i2c_send(I2C_5, MAX77812_PHASE31_CPU_I2C_ADDR, MAX77812_REG_EN_CTRL, &val, 1);
|
||||
}
|
||||
val = 0x6E;
|
||||
i2c_send(I2C_5, MAX77812_PHASE31_CPU_I2C_ADDR, MAX77812_REG_M4_VOUT, &val, 1);
|
||||
}
|
||||
val = 0x6E;
|
||||
i2c_send(I2C_5, MAX77812_PHASE31_CPU_I2C_ADDR, MAX77812_REG_M4_VOUT, &val, 1);
|
||||
break;
|
||||
case 2: /* Regulator_Max77812PhaseConfiguration211 */
|
||||
uint8_t val = 0;
|
||||
i2c_query(I2C_5, MAX77812_PHASE211_CPU_I2C_ADDR, MAX77812_REG_EN_CTRL, &val, 1);
|
||||
if (val) {
|
||||
val |= 0x40;
|
||||
i2c_send(I2C_5, MAX77812_PHASE211_CPU_I2C_ADDR, MAX77812_REG_EN_CTRL, &val, 1);
|
||||
{
|
||||
uint8_t val = 0;
|
||||
i2c_query(I2C_5, MAX77812_PHASE211_CPU_I2C_ADDR, MAX77812_REG_EN_CTRL, &val, 1);
|
||||
if (val) {
|
||||
val |= 0x40;
|
||||
i2c_send(I2C_5, MAX77812_PHASE211_CPU_I2C_ADDR, MAX77812_REG_EN_CTRL, &val, 1);
|
||||
}
|
||||
val = 0x6E;
|
||||
i2c_send(I2C_5, MAX77812_PHASE211_CPU_I2C_ADDR, MAX77812_REG_M4_VOUT, &val, 1);
|
||||
}
|
||||
val = 0x6E;
|
||||
i2c_send(I2C_5, MAX77812_PHASE211_CPU_I2C_ADDR, MAX77812_REG_M4_VOUT, &val, 1);
|
||||
break;
|
||||
default: return;
|
||||
}
|
||||
|
|
@ -78,7 +84,7 @@ static void cluster_enable_power(uint32_t regulator) {
|
|||
|
||||
static void cluster_pmc_enable_partition(uint32_t part, uint32_t toggle) {
|
||||
volatile tegra_pmc_t *pmc = pmc_get_regs();
|
||||
|
||||
|
||||
/* Check if the partition has already been turned on. */
|
||||
if (pmc->pwrgate_status & part) {
|
||||
return;
|
||||
|
|
@ -110,13 +116,13 @@ static void cluster_pmc_enable_partition(uint32_t part, uint32_t toggle) {
|
|||
void cluster_boot_cpu0(uint32_t entry) {
|
||||
volatile tegra_car_t *car = car_get_regs();
|
||||
bool is_mariko = is_soc_mariko();
|
||||
|
||||
|
||||
/* Set ACTIVE_CLUSER to FAST. */
|
||||
FLOW_CTLR_BPMP_CLUSTER_CONTROL_0 &= 0xFFFFFFFE;
|
||||
|
||||
/* Enable VddCpu. */
|
||||
cluster_enable_power(is_mariko ? fuse_get_regulator() : 0);
|
||||
|
||||
|
||||
if (!(car->pllx_base & 0x40000000)) {
|
||||
car->pllx_misc3 &= 0xFFFFFFF7;
|
||||
udelay(2);
|
||||
|
|
@ -127,7 +133,7 @@ void cluster_boot_cpu0(uint32_t entry) {
|
|||
car->pllx_misc = ((car->pllx_misc & 0xFFFBFFFF) | 0x40000);
|
||||
car->pllx_base = 0x40404E02;
|
||||
}
|
||||
|
||||
|
||||
while (!(car->pllx_base & 0x8000000)) {
|
||||
/* Wait. */
|
||||
}
|
||||
|
|
@ -139,7 +145,7 @@ void cluster_boot_cpu0(uint32_t entry) {
|
|||
car->cclk_brst_pol = 0x20008888;
|
||||
car->super_cclk_div = 0x80000000;
|
||||
car->clk_enb_v_set = 1;
|
||||
|
||||
|
||||
/* Reboot CORESIGHT. */
|
||||
clkrst_reboot(CARDEVICE_CORESIGHT);
|
||||
|
||||
|
|
@ -148,10 +154,10 @@ void cluster_boot_cpu0(uint32_t entry) {
|
|||
|
||||
/* Enable CPU rail. */
|
||||
cluster_pmc_enable_partition(1, 0);
|
||||
|
||||
|
||||
/* Enable cluster 0 non-CPU. */
|
||||
cluster_pmc_enable_partition(0x8000, 15);
|
||||
|
||||
|
||||
/* Enable CE0. */
|
||||
cluster_pmc_enable_partition(0x4000, 14);
|
||||
|
||||
|
|
@ -166,7 +172,7 @@ void cluster_boot_cpu0(uint32_t entry) {
|
|||
/* Set reset vector. */
|
||||
SB_AA64_RESET_LOW_0 = (entry | 1);
|
||||
SB_AA64_RESET_HIGH_0 = 0;
|
||||
|
||||
|
||||
/* Non-secure reset vector write disable. */
|
||||
SB_CSR_0 = 2;
|
||||
(void)SB_CSR_0;
|
||||
|
|
@ -174,15 +180,15 @@ void cluster_boot_cpu0(uint32_t entry) {
|
|||
/* Set CPU_STRICT_TZ_APERTURE_CHECK. */
|
||||
/* NOTE: This breaks Exosphère. */
|
||||
/* MAKE_MC_REG(MC_TZ_SECURITY_CTRL) = 1; */
|
||||
|
||||
|
||||
/* Clear MSELECT reset. */
|
||||
rst_disable(CARDEVICE_MSELECT);
|
||||
|
||||
|
||||
if (!is_mariko) {
|
||||
/* Clear NONCPU reset. */
|
||||
car->rst_cpug_cmplx_clr = 0x20000000;
|
||||
}
|
||||
|
||||
|
||||
/* Clear CPU{0} POR and CORE, CX0, L2, and DBG reset.*/
|
||||
car->rst_cpug_cmplx_clr = 0x41010001;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in a new issue