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fusee/sept: build fixes

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This commit is contained in:
Michael Scire 2020-12-31 17:37:57 -08:00
parent a35a30efcd
commit ec398dc612
7 changed files with 145 additions and 128 deletions
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62
fusee/fusee-secondary/src/cluster.c
View file

@ -37,40 +37,46 @@ static bool is_soc_mariko() {
static void cluster_enable_power(uint32_t regulator) { static void cluster_enable_power(uint32_t regulator) {
switch (regulator) { switch (regulator) {
case 0: /* Regulator_Max77621 */ case 0: /* Regulator_Max77621 */
uint8_t val = 0; {
i2c_query(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_AME_GPIO, &val, 1); uint8_t val = 0;
val &= 0xDF; i2c_query(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_AME_GPIO, &val, 1);
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_AME_GPIO, &val, 1); val &= 0xDF;
val = 0x09; i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_AME_GPIO, &val, 1);
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_GPIO5, &val, 1); val = 0x09;
val = 0x20; i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_GPIO5, &val, 1);
i2c_send(I2C_5, MAX77621_CPU_I2C_ADDR, 0x02, &val, 1); val = 0x20;
val = 0x8D; i2c_send(I2C_5, MAX77621_CPU_I2C_ADDR, 0x02, &val, 1);
i2c_send(I2C_5, MAX77621_CPU_I2C_ADDR, 0x03, &val, 1); val = 0x8D;
val = 0xB7; i2c_send(I2C_5, MAX77621_CPU_I2C_ADDR, 0x03, &val, 1);
i2c_send(I2C_5, MAX77621_CPU_I2C_ADDR, 0x00, &val, 1); val = 0xB7;
val = 0xB7; i2c_send(I2C_5, MAX77621_CPU_I2C_ADDR, 0x00, &val, 1);
i2c_send(I2C_5, MAX77621_CPU_I2C_ADDR, 0x01, &val, 1); val = 0xB7;
i2c_send(I2C_5, MAX77621_CPU_I2C_ADDR, 0x01, &val, 1);
}
break; break;
case 1: /* Regulator_Max77812PhaseConfiguration31 */ case 1: /* Regulator_Max77812PhaseConfiguration31 */
uint8_t val = 0; {
i2c_query(I2C_5, MAX77812_PHASE31_CPU_I2C_ADDR, MAX77812_REG_EN_CTRL, &val, 1); uint8_t val = 0;
if (val) { i2c_query(I2C_5, MAX77812_PHASE31_CPU_I2C_ADDR, MAX77812_REG_EN_CTRL, &val, 1);
val |= 0x40; if (val) {
i2c_send(I2C_5, MAX77812_PHASE31_CPU_I2C_ADDR, MAX77812_REG_EN_CTRL, &val, 1); val |= 0x40;
i2c_send(I2C_5, MAX77812_PHASE31_CPU_I2C_ADDR, MAX77812_REG_EN_CTRL, &val, 1);
}
val = 0x6E;
i2c_send(I2C_5, MAX77812_PHASE31_CPU_I2C_ADDR, MAX77812_REG_M4_VOUT, &val, 1);
} }
val = 0x6E;
i2c_send(I2C_5, MAX77812_PHASE31_CPU_I2C_ADDR, MAX77812_REG_M4_VOUT, &val, 1);
break; break;
case 2: /* Regulator_Max77812PhaseConfiguration211 */ case 2: /* Regulator_Max77812PhaseConfiguration211 */
uint8_t val = 0; {
i2c_query(I2C_5, MAX77812_PHASE211_CPU_I2C_ADDR, MAX77812_REG_EN_CTRL, &val, 1); uint8_t val = 0;
if (val) { i2c_query(I2C_5, MAX77812_PHASE211_CPU_I2C_ADDR, MAX77812_REG_EN_CTRL, &val, 1);
val |= 0x40; if (val) {
i2c_send(I2C_5, MAX77812_PHASE211_CPU_I2C_ADDR, MAX77812_REG_EN_CTRL, &val, 1); val |= 0x40;
i2c_send(I2C_5, MAX77812_PHASE211_CPU_I2C_ADDR, MAX77812_REG_EN_CTRL, &val, 1);
}
val = 0x6E;
i2c_send(I2C_5, MAX77812_PHASE211_CPU_I2C_ADDR, MAX77812_REG_M4_VOUT, &val, 1);
} }
val = 0x6E;
i2c_send(I2C_5, MAX77812_PHASE211_CPU_I2C_ADDR, MAX77812_REG_M4_VOUT, &val, 1);
break; break;
default: return; default: return;
} }

2
fusee/fusee-secondary/src/fuse.h
View file

@ -470,7 +470,7 @@ uint64_t fuse_get_device_id(void);
uint32_t fuse_get_dram_id(void); uint32_t fuse_get_dram_id(void);
uint32_t fuse_get_hardware_type_with_firmware_check(uint32_t target_firmware); uint32_t fuse_get_hardware_type_with_firmware_check(uint32_t target_firmware);
uint32_t fuse_get_hardware_type(void); uint32_t fuse_get_hardware_type(void);
uint32_t fuse_get_retail_type(void); uint32_t fuse_get_hardware_state(void);
void fuse_get_hardware_info(void *dst); void fuse_get_hardware_info(void *dst);
bool fuse_is_new_format(void); bool fuse_is_new_format(void);
uint32_t fuse_get_device_unique_key_generation(void); uint32_t fuse_get_device_unique_key_generation(void);

2
fusee/fusee-secondary/src/key_derivation.c
View file

@ -15,7 +15,7 @@
*/ */
#include <stdio.h> #include <stdio.h>
#include "lib/log.h" #include "../../../fusee/common/log.h"
#include "key_derivation.h" #include "key_derivation.h"
#include "masterkey.h" #include "masterkey.h"
#include "se.h" #include "se.h"

17
fusee/fusee-secondary/src/nxboot.c
View file

@ -771,9 +771,11 @@ uint32_t nxboot_main(void) {
fatal_error("[NXBOOT] Failed to open boot0: %s!\n", strerror(errno)); fatal_error("[NXBOOT] Failed to open boot0: %s!\n", strerror(errno));
} }
if (is_mariko) { if (is_mariko) {
/* TODO*/ if (package1_read_and_parse_boot0_mariko(&package1loader, &package1loader_size, boot0) == -1) {
fatal_error("[NXBOOT] Couldn't parse boot0: %s!\n", strerror(errno));
}
} else { } else {
if (package1_read_and_parse_boot0(&package1loader, &package1loader_size, g_keyblobs, &available_revision, boot0) == -1) { if (package1_read_and_parse_boot0_erista(&package1loader, &package1loader_size, g_keyblobs, &available_revision, boot0) == -1) {
fatal_error("[NXBOOT] Couldn't parse boot0: %s!\n", strerror(errno)); fatal_error("[NXBOOT] Couldn't parse boot0: %s!\n", strerror(errno));
} }
} }
@ -782,12 +784,15 @@ uint32_t nxboot_main(void) {
/* Find the system's target firmware. */ /* Find the system's target firmware. */
uint32_t target_firmware = nxboot_get_target_firmware(package1loader); uint32_t target_firmware = nxboot_get_target_firmware(package1loader);
if (!target_firmware) if (!target_firmware) {
fatal_error("[NXBOOT] Failed to detect target firmware!\n"); fatal_error("[NXBOOT] Failed to detect target firmware!\n");
else } else {
print(SCREEN_LOG_LEVEL_INFO, "[NXBOOT] Detected target firmware %ld!\n", target_firmware); print(SCREEN_LOG_LEVEL_INFO, "[NXBOOT] Detected target firmware %ld!\n", target_firmware);
}
/* Handle TSEC and Sept (Erista only). */ /* Handle TSEC and Sept (Erista only). */
uint8_t tsec_key[0x10] = {0};
uint8_t tsec_root_keys[0x20][0x10] = {0};
if (!is_mariko) { if (!is_mariko) {
/* Read the TSEC firmware from a file, otherwise from PK1L. */ /* Read the TSEC firmware from a file, otherwise from PK1L. */
if (loader_ctx->tsecfw_path[0] != '\0') { if (loader_ctx->tsecfw_path[0] != '\0') {
@ -859,8 +864,6 @@ uint32_t nxboot_main(void) {
print(SCREEN_LOG_LEVEL_INFO, "[NXBOOT] Loaded firmware from eMMC...\n"); print(SCREEN_LOG_LEVEL_INFO, "[NXBOOT] Loaded firmware from eMMC...\n");
/* Get the TSEC keys. */ /* Get the TSEC keys. */
uint8_t tsec_key[0x10] = {0};
uint8_t tsec_root_keys[0x20][0x10] = {0};
if (target_firmware >= ATMOSPHERE_TARGET_FIRMWARE_7_0_0) { if (target_firmware >= ATMOSPHERE_TARGET_FIRMWARE_7_0_0) {
/* Detect whether we need to run sept-secondary in order to derive keys. */ /* Detect whether we need to run sept-secondary in order to derive keys. */
if (!get_and_clear_has_run_sept()) { if (!get_and_clear_has_run_sept()) {
@ -958,6 +961,8 @@ uint32_t nxboot_main(void) {
} else { } else {
if (is_mariko) { if (is_mariko) {
/* TODO */ /* TODO */
warmboot_fw = NULL;
warmboot_fw_size = 0;
} else { } else {
/* Use Atmosphere's warmboot firmware implementation. */ /* Use Atmosphere's warmboot firmware implementation. */
warmboot_fw_size = warmboot_bin_size; warmboot_fw_size = warmboot_bin_size;

2
sept/sept-primary/src/main.c
View file

@ -229,7 +229,7 @@ int main(void) {
/* Clear the boot reason to avoid problems later */ /* Clear the boot reason to avoid problems later */
pmc->scratch200 = 0; pmc->scratch200 = 0;
pmc->reset_status = 0; pmc->rst_status = 0;
//AHB_AHB_SPARE_REG_0 &= 0xFFFFFF9F; //AHB_AHB_SPARE_REG_0 &= 0xFFFFFF9F;
//pmc->scratch49 = (((pmc->scratch49 >> 1) << 1) & 0xFFFFFFFD); //pmc->scratch49 = (((pmc->scratch49 >> 1) << 1) & 0xFFFFFFFD);

2
sept/sept-secondary/linker.ld
View file

@ -13,7 +13,7 @@ PHDRS
MEMORY MEMORY
{ {
NULL : ORIGIN = 0x00000000, LENGTH = 0x1000 NULL : ORIGIN = 0x00000000, LENGTH = 0x1000
main : ORIGIN = 0x40010000, LENGTH = 0x20000 main : ORIGIN = 0x40010000, LENGTH = 0x28000
low_iram : ORIGIN = 0x40003000, LENGTH = 0x8000 low_iram : ORIGIN = 0x40003000, LENGTH = 0x8000
} }

62
sept/sept-secondary/src/cluster.c
View file

@ -37,40 +37,46 @@ static bool is_soc_mariko() {
static void cluster_enable_power(uint32_t regulator) { static void cluster_enable_power(uint32_t regulator) {
switch (regulator) { switch (regulator) {
case 0: /* Regulator_Max77621 */ case 0: /* Regulator_Max77621 */
uint8_t val = 0; {
i2c_query(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_AME_GPIO, &val, 1); uint8_t val = 0;
val &= 0xDF; i2c_query(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_AME_GPIO, &val, 1);
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_AME_GPIO, &val, 1); val &= 0xDF;
val = 0x09; i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_AME_GPIO, &val, 1);
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_GPIO5, &val, 1); val = 0x09;
val = 0x20; i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_GPIO5, &val, 1);
i2c_send(I2C_5, MAX77621_CPU_I2C_ADDR, 0x02, &val, 1); val = 0x20;
val = 0x8D; i2c_send(I2C_5, MAX77621_CPU_I2C_ADDR, 0x02, &val, 1);
i2c_send(I2C_5, MAX77621_CPU_I2C_ADDR, 0x03, &val, 1); val = 0x8D;
val = 0xB7; i2c_send(I2C_5, MAX77621_CPU_I2C_ADDR, 0x03, &val, 1);
i2c_send(I2C_5, MAX77621_CPU_I2C_ADDR, 0x00, &val, 1); val = 0xB7;
val = 0xB7; i2c_send(I2C_5, MAX77621_CPU_I2C_ADDR, 0x00, &val, 1);
i2c_send(I2C_5, MAX77621_CPU_I2C_ADDR, 0x01, &val, 1); val = 0xB7;
i2c_send(I2C_5, MAX77621_CPU_I2C_ADDR, 0x01, &val, 1);
}
break; break;
case 1: /* Regulator_Max77812PhaseConfiguration31 */ case 1: /* Regulator_Max77812PhaseConfiguration31 */
uint8_t val = 0; {
i2c_query(I2C_5, MAX77812_PHASE31_CPU_I2C_ADDR, MAX77812_REG_EN_CTRL, &val, 1); uint8_t val = 0;
if (val) { i2c_query(I2C_5, MAX77812_PHASE31_CPU_I2C_ADDR, MAX77812_REG_EN_CTRL, &val, 1);
val |= 0x40; if (val) {
i2c_send(I2C_5, MAX77812_PHASE31_CPU_I2C_ADDR, MAX77812_REG_EN_CTRL, &val, 1); val |= 0x40;
i2c_send(I2C_5, MAX77812_PHASE31_CPU_I2C_ADDR, MAX77812_REG_EN_CTRL, &val, 1);
}
val = 0x6E;
i2c_send(I2C_5, MAX77812_PHASE31_CPU_I2C_ADDR, MAX77812_REG_M4_VOUT, &val, 1);
} }
val = 0x6E;
i2c_send(I2C_5, MAX77812_PHASE31_CPU_I2C_ADDR, MAX77812_REG_M4_VOUT, &val, 1);
break; break;
case 2: /* Regulator_Max77812PhaseConfiguration211 */ case 2: /* Regulator_Max77812PhaseConfiguration211 */
uint8_t val = 0; {
i2c_query(I2C_5, MAX77812_PHASE211_CPU_I2C_ADDR, MAX77812_REG_EN_CTRL, &val, 1); uint8_t val = 0;
if (val) { i2c_query(I2C_5, MAX77812_PHASE211_CPU_I2C_ADDR, MAX77812_REG_EN_CTRL, &val, 1);
val |= 0x40; if (val) {
i2c_send(I2C_5, MAX77812_PHASE211_CPU_I2C_ADDR, MAX77812_REG_EN_CTRL, &val, 1); val |= 0x40;
i2c_send(I2C_5, MAX77812_PHASE211_CPU_I2C_ADDR, MAX77812_REG_EN_CTRL, &val, 1);
}
val = 0x6E;
i2c_send(I2C_5, MAX77812_PHASE211_CPU_I2C_ADDR, MAX77812_REG_M4_VOUT, &val, 1);
} }
val = 0x6E;
i2c_send(I2C_5, MAX77812_PHASE211_CPU_I2C_ADDR, MAX77812_REG_M4_VOUT, &val, 1);
break; break;
default: return; default: return;
} }