Update cheat docs with latest opcodes (#479)

* Update cheat docs with latest opcodes

This covers changes made to Opcode 10 as well as the new 0xC0 opcode

* Corrected Opcode 10 documentation
This commit is contained in:
tslater2006 2019-03-16 00:20:20 -05:00 committed by SciresM
parent 51fa778fb2
commit e7f941fa3d

View file

@ -283,22 +283,24 @@ Code type 10 allows writing a register to memory.
#### Encoding #### Encoding
`ATSRIOra (aaaaaaaa)` `ATSRIOxa (aaaaaaaa)`
+ T: width of memory write (1, 2, 4, or 8 bytes) + T: width of memory write (1, 2, 4, or 8 bytes)
+ S: Register to write to memory. + S: Register to write to memory.
+ R: Register to use as base address. + R: Register to use as base address.
+ I: Increment register flag (0 = do not increment R, 1 = increment R by T). + I: Increment register flag (0 = do not increment R, 1 = increment R by T).
+ O: Offset type, see below. + O: Offset type, see below.
+ r: Register used as offset when O is 1. + x: Register used as offset when O is 1, Memory type when O is 3, 4 or 5.
+ a: Value used as offset when O is 2. + a: Value used as offset when O is 2, 4 or 5.
#### Offset Types #### Offset Types
+ 0: No Offset + 0: No Offset
+ 1: Use Offset Register + 1: Use Offset Register
+ 2: Use Fixed Offset + 2: Use Fixed Offset
+ 3: Memory Region + Base Register
+ 4: Memory Region + Relative Address (ignore address register)
+ 5: Memory Region + Relative Address + Offset Register
--- ---
### Code Type 11: Reserved ### Code Type 11: Reserved
@ -314,3 +316,50 @@ Code Types 12-15 signal to the VM to treat the upper two nybbles of the first dw
This reserves an additional 64 opcodes for future use. This reserves an additional 64 opcodes for future use.
--- ---
### Code Type 0xC0: Begin Register Conditional Block
Code type 0xC0 performs a comparison of the contents of a register and another value. This code support multiple operand types, see below.
If the condition is not met, all instructions until the appropriate conditional block terminator are skipped.
#### Encoding
```
C0TcSX##
C0TcS0Ma aaaaaaaa
C0TcS1Mr
C0TcS2Ra aaaaaaaa
C0TcS3Rr
C0TcS400 VVVVVVVV (VVVVVVVV)
C0TcS5X0
```
+ T: width of memory write (1, 2, 4, or 8 bytes)
+ c: Condition to use, see below.
+ S: Source Register
+ X: Operand Type, see below.
+ M: Memory Type (operand types 0 and 1)
+ R: Address Register (operand types 2 and 3)
+ a: Relative Address (operand types 0 and 2)
+ r: Offset Register (operand types 1 and 3)
+ X: Other Register (used for operand type 5)
+ V: Value to compare to (operand type 4)
#### Operand Type
+ 0: Memory Base + Relative Offset
+ 1: Memory Base + Offset Register
+ 2: Register + Relative Offset
+ 3: Register + Offset Register
+ 4: Static Value
+ 5: Other Register
#### Conditions
+ 1: >
+ 2: >=
+ 3: <
+ 4: <=
+ 5: ==
+ 6: !=