mirror of
https://github.com/Atmosphere-NX/Atmosphere
synced 2024-12-22 20:31:14 +00:00
fusee: Remove obsolete MC carveout configuration.
exosphere: Fix client access for MC carveout 2.
This commit is contained in:
parent
164fb96da0
commit
e5e9968d22
14 changed files with 957 additions and 184 deletions
|
@ -46,17 +46,16 @@
|
||||||
|
|
||||||
static bool g_has_booted_up = false;
|
static bool g_has_booted_up = false;
|
||||||
|
|
||||||
|
|
||||||
void setup_dram_magic_numbers(void) {
|
void setup_dram_magic_numbers(void) {
|
||||||
/* TODO: Why does these DRAM write occur? */
|
/* These DRAM writes test and set values for the GPU UCODE carveout. */
|
||||||
unsigned int target_fw = exosphere_get_target_firmware();
|
unsigned int target_fw = exosphere_get_target_firmware();
|
||||||
if (EXOSPHERE_TARGET_FIRMWARE_400 <= target_fw) {
|
if (EXOSPHERE_TARGET_FIRMWARE_400 <= target_fw) {
|
||||||
(*(volatile uint32_t *)(0x8005FFFC)) = 0xC0EDBBCC;
|
(*(volatile uint32_t *)(0x8005FFFC)) = 0xC0EDBBCC; /* Access test value. */
|
||||||
flush_dcache_range((void *)0x8005FFFC, (void *)0x80060000);
|
flush_dcache_range((void *)0x8005FFFC, (void *)0x80060000);
|
||||||
if (EXOSPHERE_TARGET_FIRMWARE_600 <= target_fw) {
|
if (EXOSPHERE_TARGET_FIRMWARE_600 <= target_fw) {
|
||||||
(*(volatile uint32_t *)(0x8005FF00)) = 0x00000083;
|
(*(volatile uint32_t *)(0x8005FF00)) = 0x00000083; /* SKU code. */
|
||||||
(*(volatile uint32_t *)(0x8005FF04)) = 0x00000002;
|
(*(volatile uint32_t *)(0x8005FF04)) = 0x00000002;
|
||||||
(*(volatile uint32_t *)(0x8005FF08)) = 0x00000210;
|
(*(volatile uint32_t *)(0x8005FF08)) = 0x00000210; /* Tegra210 code. */
|
||||||
flush_dcache_range((void *)0x8005FF00, (void *)0x8005FF0C);
|
flush_dcache_range((void *)0x8005FF00, (void *)0x8005FF0C);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
@ -87,8 +86,8 @@ void bootup_misc_mmio(void) {
|
||||||
setup_dram_magic_numbers();
|
setup_dram_magic_numbers();
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Todo: What? */
|
/* Mark TMR5, TMR6, TMR7, TMR8, WDT0, WDT1, WDT2 and WDT3 as secure. */
|
||||||
MAKE_TIMERS_REG(0x1A4) = 0xF1E0;
|
SHARED_TIMER_SECURE_CFG_0 = 0xF1E0;
|
||||||
|
|
||||||
FLOW_CTLR_BPMP_CLUSTER_CONTROL_0 = 4; /* ACTIVE_CLUSTER_LOCK. */
|
FLOW_CTLR_BPMP_CLUSTER_CONTROL_0 = 4; /* ACTIVE_CLUSTER_LOCK. */
|
||||||
FLOW_CTLR_FLOW_DBG_QUAL_0 = 0x10000000; /* Enable FIQ2CCPLEX */
|
FLOW_CTLR_FLOW_DBG_QUAL_0 = 0x10000000; /* Enable FIQ2CCPLEX */
|
||||||
|
@ -96,22 +95,21 @@ void bootup_misc_mmio(void) {
|
||||||
/* Disable Deep Power Down. */
|
/* Disable Deep Power Down. */
|
||||||
APBDEV_PMC_DPD_ENABLE_0 = 0;
|
APBDEV_PMC_DPD_ENABLE_0 = 0;
|
||||||
|
|
||||||
/* Setup MC. */
|
/* Setup MC carveouts. */
|
||||||
/* TODO: What are these MC reg writes? */
|
MAKE_MC_REG(MC_VIDEO_PROTECT_GPU_OVERRIDE_0) = 1;
|
||||||
MAKE_MC_REG(0x984) = 1;
|
MAKE_MC_REG(MC_VIDEO_PROTECT_BOM) = 0;
|
||||||
MAKE_MC_REG(0x648) = 0;
|
MAKE_MC_REG(MC_VIDEO_PROTECT_SIZE_MB) = 0;
|
||||||
MAKE_MC_REG(0x64C) = 0;
|
MAKE_MC_REG(MC_VIDEO_PROTECT_REG_CTRL) = 1;
|
||||||
MAKE_MC_REG(0x650) = 1;
|
MAKE_MC_REG(MC_SEC_CARVEOUT_BOM) = 0;
|
||||||
MAKE_MC_REG(0x670) = 0;
|
MAKE_MC_REG(MC_SEC_CARVEOUT_SIZE_MB) = 0;
|
||||||
MAKE_MC_REG(0x674) = 0;
|
MAKE_MC_REG(MC_SEC_CARVEOUT_REG_CTRL) = 1;
|
||||||
MAKE_MC_REG(0x678) = 1;
|
MAKE_MC_REG(MC_MTS_CARVEOUT_BOM) = 0;
|
||||||
MAKE_MC_REG(0x9A0) = 0;
|
MAKE_MC_REG(MC_MTS_CARVEOUT_SIZE_MB) = 0;
|
||||||
MAKE_MC_REG(0x9A4) = 0;
|
MAKE_MC_REG(MC_MTS_CARVEOUT_ADR_HI) = 0;
|
||||||
MAKE_MC_REG(0x9A8) = 0;
|
MAKE_MC_REG(MC_MTS_CARVEOUT_REG_CTRL) = 1;
|
||||||
MAKE_MC_REG(0x9AC) = 1;
|
MAKE_MC_REG(MC_SECURITY_CFG0) = 0;
|
||||||
MC_SECURITY_CFG0_0 = 0;
|
MAKE_MC_REG(MC_SECURITY_CFG1) = 0;
|
||||||
MC_SECURITY_CFG1_0 = 0;
|
MAKE_MC_REG(MC_SECURITY_CFG3) = 3;
|
||||||
MC_SECURITY_CFG3_0 = 3;
|
|
||||||
configure_default_carveouts();
|
configure_default_carveouts();
|
||||||
|
|
||||||
/* Mark registers secure world only. */
|
/* Mark registers secure world only. */
|
||||||
|
@ -142,12 +140,12 @@ void bootup_misc_mmio(void) {
|
||||||
APB_MISC_SECURE_REGS_APB_SLAVE_SECURITY_ENABLE_REG2_0 = sec_disable_2;
|
APB_MISC_SECURE_REGS_APB_SLAVE_SECURITY_ENABLE_REG2_0 = sec_disable_2;
|
||||||
}
|
}
|
||||||
|
|
||||||
/* reset Translation Enable Registers */
|
/* Reset Translation Enable Registers. */
|
||||||
MC_SMMU_TRANSLATION_ENABLE_0_0 = 0xFFFFFFFF;
|
MAKE_MC_REG(MC_SMMU_TRANSLATION_ENABLE_0) = 0xFFFFFFFF;
|
||||||
MC_SMMU_TRANSLATION_ENABLE_1_0 = 0xFFFFFFFF;
|
MAKE_MC_REG(MC_SMMU_TRANSLATION_ENABLE_1) = 0xFFFFFFFF;
|
||||||
MC_SMMU_TRANSLATION_ENABLE_2_0 = 0xFFFFFFFF;
|
MAKE_MC_REG(MC_SMMU_TRANSLATION_ENABLE_2) = 0xFFFFFFFF;
|
||||||
MC_SMMU_TRANSLATION_ENABLE_3_0 = 0xFFFFFFFF;
|
MAKE_MC_REG(MC_SMMU_TRANSLATION_ENABLE_3) = 0xFFFFFFFF;
|
||||||
MC_SMMU_TRANSLATION_ENABLE_4_0 = 0xFFFFFFFF;
|
MAKE_MC_REG(MC_SMMU_TRANSLATION_ENABLE_4) = 0xFFFFFFFF;
|
||||||
|
|
||||||
/* TODO: What are these MC reg writes? */
|
/* TODO: What are these MC reg writes? */
|
||||||
if (exosphere_get_target_firmware() >= EXOSPHERE_TARGET_FIRMWARE_400) {
|
if (exosphere_get_target_firmware() >= EXOSPHERE_TARGET_FIRMWARE_400) {
|
||||||
|
@ -157,7 +155,7 @@ void bootup_misc_mmio(void) {
|
||||||
}
|
}
|
||||||
MAKE_MC_REG(0x03C) = 0;
|
MAKE_MC_REG(0x03C) = 0;
|
||||||
|
|
||||||
/* MISC registers*/
|
/* MISC registers. */
|
||||||
MAKE_MC_REG(0x9E0) = 0;
|
MAKE_MC_REG(0x9E0) = 0;
|
||||||
MAKE_MC_REG(0x9E4) = 0;
|
MAKE_MC_REG(0x9E4) = 0;
|
||||||
MAKE_MC_REG(0x9E8) = 0;
|
MAKE_MC_REG(0x9E8) = 0;
|
||||||
|
@ -166,18 +164,18 @@ void bootup_misc_mmio(void) {
|
||||||
MAKE_MC_REG(0x9F4) = 0;
|
MAKE_MC_REG(0x9F4) = 0;
|
||||||
|
|
||||||
if (exosphere_get_target_firmware() >= EXOSPHERE_TARGET_FIRMWARE_400) {
|
if (exosphere_get_target_firmware() >= EXOSPHERE_TARGET_FIRMWARE_400) {
|
||||||
MC_SMMU_PTB_ASID_0 = 0;
|
MAKE_MC_REG(MC_SMMU_PTB_ASID) = 0;
|
||||||
}
|
}
|
||||||
MC_SMMU_PTB_DATA_0 = 0;
|
MAKE_MC_REG(MC_SMMU_PTB_DATA) = 0;
|
||||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030;
|
MAKE_MC_REG(MC_SMMU_TLB_CONFIG) = 0x30000030;
|
||||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F;
|
MAKE_MC_REG(MC_SMMU_PTC_CONFIG) = 0x2800003F;
|
||||||
(void)MC_SMMU_TLB_CONFIG_0;
|
(void)MAKE_MC_REG(MC_SMMU_TLB_CONFIG);
|
||||||
MC_SMMU_PTC_FLUSH_0 = 0;
|
MAKE_MC_REG(MC_SMMU_PTC_FLUSH) = 0;
|
||||||
(void)MC_SMMU_TLB_CONFIG_0;
|
(void)MAKE_MC_REG(MC_SMMU_TLB_CONFIG);
|
||||||
MC_SMMU_TLB_FLUSH_0 = 0;
|
MAKE_MC_REG(MC_SMMU_TLB_FLUSH) = 0;
|
||||||
(void)MC_SMMU_TLB_CONFIG_0;
|
(void)MAKE_MC_REG(MC_SMMU_TLB_CONFIG);
|
||||||
MC_SMMU_CONFIG_0 = 1; /* enable SMMU */
|
MAKE_MC_REG(MC_SMMU_CONFIG) = 1; /* Enable SMMU. */
|
||||||
(void)MC_SMMU_TLB_CONFIG_0;
|
(void)MAKE_MC_REG(MC_SMMU_TLB_CONFIG);
|
||||||
|
|
||||||
/* Clear RESET Vector, setup CPU Secure Boot RESET Vectors. */
|
/* Clear RESET Vector, setup CPU Secure Boot RESET Vectors. */
|
||||||
uint32_t reset_vec;
|
uint32_t reset_vec;
|
||||||
|
@ -200,13 +198,13 @@ void bootup_misc_mmio(void) {
|
||||||
|
|
||||||
/* Setup FIQs. */
|
/* Setup FIQs. */
|
||||||
|
|
||||||
|
|
||||||
/* And assign "se_operation_completed" to Interrupt 0x5A. */
|
/* And assign "se_operation_completed" to Interrupt 0x5A. */
|
||||||
intr_set_priority(INTERRUPT_ID_SECURITY_ENGINE, 0);
|
intr_set_priority(INTERRUPT_ID_SECURITY_ENGINE, 0);
|
||||||
intr_set_group(INTERRUPT_ID_SECURITY_ENGINE, 0);
|
intr_set_group(INTERRUPT_ID_SECURITY_ENGINE, 0);
|
||||||
intr_set_enabled(INTERRUPT_ID_SECURITY_ENGINE, 1);
|
intr_set_enabled(INTERRUPT_ID_SECURITY_ENGINE, 1);
|
||||||
intr_set_cpu_mask(INTERRUPT_ID_SECURITY_ENGINE, 8);
|
intr_set_cpu_mask(INTERRUPT_ID_SECURITY_ENGINE, 8);
|
||||||
intr_set_edge_level(INTERRUPT_ID_SECURITY_ENGINE, 0);
|
intr_set_edge_level(INTERRUPT_ID_SECURITY_ENGINE, 0);
|
||||||
|
|
||||||
if (exosphere_get_target_firmware() >= EXOSPHERE_TARGET_FIRMWARE_400) {
|
if (exosphere_get_target_firmware() >= EXOSPHERE_TARGET_FIRMWARE_400) {
|
||||||
intr_set_priority(INTERRUPT_ID_ACTIVITY_MONITOR_4X, 0);
|
intr_set_priority(INTERRUPT_ID_ACTIVITY_MONITOR_4X, 0);
|
||||||
intr_set_group(INTERRUPT_ID_ACTIVITY_MONITOR_4X, 0);
|
intr_set_group(INTERRUPT_ID_ACTIVITY_MONITOR_4X, 0);
|
||||||
|
@ -225,10 +223,10 @@ void bootup_misc_mmio(void) {
|
||||||
}
|
}
|
||||||
g_has_booted_up = true;
|
g_has_booted_up = true;
|
||||||
} else if (exosphere_get_target_firmware() < EXOSPHERE_TARGET_FIRMWARE_400) {
|
} else if (exosphere_get_target_firmware() < EXOSPHERE_TARGET_FIRMWARE_400) {
|
||||||
/* TODO: What are these MC reg writes? */
|
/* Disable AHB redirect. */
|
||||||
MAKE_MC_REG(0x65C) = 0xFFFFF000;
|
MAKE_MC_REG(MC_IRAM_BOM) = 0xFFFFF000;
|
||||||
MAKE_MC_REG(0x660) = 0;
|
MAKE_MC_REG(MC_IRAM_TOM) = 0;
|
||||||
MAKE_MC_REG(0x964) |= 1;
|
MAKE_MC_REG(MC_IRAM_REG_CTRL) |= 1;
|
||||||
CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD_0 &= 0xFFF7FFFF;
|
CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD_0 &= 0xFFF7FFFF;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
@ -237,10 +235,11 @@ void setup_4x_mmio(void) {
|
||||||
if (exosphere_get_target_firmware() >= EXOSPHERE_TARGET_FIRMWARE_600) {
|
if (exosphere_get_target_firmware() >= EXOSPHERE_TARGET_FIRMWARE_600) {
|
||||||
configure_gpu_ucode_carveout();
|
configure_gpu_ucode_carveout();
|
||||||
}
|
}
|
||||||
/* TODO: What are these MC reg writes? */
|
|
||||||
MAKE_MC_REG(0x65C) = 0xFFFFF000;
|
/* Disable AHB redirect. */
|
||||||
MAKE_MC_REG(0x660) = 0;
|
MAKE_MC_REG(MC_IRAM_BOM) = 0xFFFFF000;
|
||||||
MAKE_MC_REG(0x964) |= 1;
|
MAKE_MC_REG(MC_IRAM_TOM) = 0;
|
||||||
|
MAKE_MC_REG(MC_IRAM_REG_CTRL) |= 1;
|
||||||
CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD_0 &= 0xFFF7FFFF;
|
CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD_0 &= 0xFFF7FFFF;
|
||||||
|
|
||||||
/* TODO: What are these PMC scratch writes? */
|
/* TODO: What are these PMC scratch writes? */
|
||||||
|
@ -275,16 +274,16 @@ void setup_4x_mmio(void) {
|
||||||
AHB_ARBITRATION_DISABLE_0 |= 2;
|
AHB_ARBITRATION_DISABLE_0 |= 2;
|
||||||
|
|
||||||
/* Set SMMU for BPMP/APB-DMA to point to TZRAM. */
|
/* Set SMMU for BPMP/APB-DMA to point to TZRAM. */
|
||||||
MC_SMMU_PTB_ASID_0 = 1;
|
MAKE_MC_REG(MC_SMMU_PTB_ASID) = 1;
|
||||||
(void)MC_SMMU_TLB_CONFIG_0;
|
(void)MAKE_MC_REG(MC_SMMU_TLB_CONFIG);
|
||||||
MC_SMMU_PTB_DATA_0 = 0x70012;
|
MAKE_MC_REG(MC_SMMU_PTB_DATA) = 0x70012;
|
||||||
MC_SMMU_AVPC_ASID_0 = 0x80000001;
|
MAKE_MC_REG(MC_SMMU_AVPC_ASID) = 0x80000001;
|
||||||
MC_SMMU_PPCS1_ASID_0 = 0x80000001;
|
MAKE_MC_REG(MC_SMMU_PPCS1_ASID) = 0x80000001;
|
||||||
(void)MC_SMMU_TLB_CONFIG_0;
|
(void)MAKE_MC_REG(MC_SMMU_TLB_CONFIG);
|
||||||
MC_SMMU_PTC_FLUSH_0 = 0;
|
MAKE_MC_REG(MC_SMMU_PTC_FLUSH) = 0;
|
||||||
(void)MC_SMMU_TLB_CONFIG_0;
|
(void)MAKE_MC_REG(MC_SMMU_TLB_CONFIG);
|
||||||
MC_SMMU_TLB_FLUSH_0 = 0;
|
MAKE_MC_REG(MC_SMMU_TLB_FLUSH) = 0;
|
||||||
(void)MC_SMMU_TLB_CONFIG_0;
|
(void)MAKE_MC_REG(MC_SMMU_TLB_CONFIG);
|
||||||
|
|
||||||
/* Wait for the BPMP to halt. */
|
/* Wait for the BPMP to halt. */
|
||||||
while ((FLOW_CTLR_HALT_COP_EVENTS_0 >> 29) != 2) {
|
while ((FLOW_CTLR_HALT_COP_EVENTS_0 >> 29) != 2) {
|
||||||
|
@ -321,7 +320,7 @@ void setup_current_core_state(void) {
|
||||||
|
|
||||||
__isb();
|
__isb();
|
||||||
|
|
||||||
SET_SYSREG(cntfrq_el0, MAKE_SYSCTR0_REG(0x20)); /* TODO: Reg name. */
|
SET_SYSREG(cntfrq_el0, SYSCTR0_CNTFID0_0);
|
||||||
SET_SYSREG(cnthctl_el2, 3ull);
|
SET_SYSREG(cnthctl_el2, 3ull);
|
||||||
|
|
||||||
__isb();
|
__isb();
|
||||||
|
|
|
@ -39,23 +39,23 @@ volatile security_carveout_t *get_carveout_by_id(unsigned int carveout) {
|
||||||
}
|
}
|
||||||
|
|
||||||
void configure_gpu_ucode_carveout(void) {
|
void configure_gpu_ucode_carveout(void) {
|
||||||
/* Starting in 6.0.0, Carveout 2 is configured later on. */
|
/* Starting in 6.0.0, Carveout 2 is configured later on and adds read permission to TSEC. */
|
||||||
/* This is a helper function to make this easier... */
|
/* This is a helper function to make this easier... */
|
||||||
volatile security_carveout_t *carveout = get_carveout_by_id(2);
|
volatile security_carveout_t *carveout = get_carveout_by_id(2);
|
||||||
carveout->paddr_low = 0x80020000;
|
carveout->paddr_low = 0x80020000;
|
||||||
carveout->paddr_high = 0;
|
carveout->paddr_high = 0;
|
||||||
carveout->size_big_pages = 2; /* 0x40000 */
|
carveout->size_big_pages = 2; /* 0x40000 */
|
||||||
carveout->flags_0 = 0;
|
carveout->client_access_0 = 0;
|
||||||
carveout->flags_1 = 0;
|
carveout->client_access_1 = 0;
|
||||||
carveout->flags_2 = 0x3000000;
|
carveout->client_access_2 = (exosphere_get_target_firmware() >= EXOSPHERE_TARGET_FIRMWARE_600) ? (BIT(CSR_GPUSRD) | BIT(CSW_GPUSWR) | BIT(CSR_TSECSRD)) : (BIT(CSR_GPUSRD) | BIT(CSW_GPUSWR));
|
||||||
carveout->flags_3 = 0;
|
carveout->client_access_3 = 0;
|
||||||
carveout->flags_4 = 0x300;
|
carveout->client_access_4 = (BIT(CSR_GPUSRD2) | BIT(CSW_GPUSWR2));
|
||||||
carveout->flags_5 = 0;
|
carveout->client_force_internal_access_0 = 0;
|
||||||
carveout->flags_6 = 0;
|
carveout->client_force_internal_access_1 = 0;
|
||||||
carveout->flags_7 = 0;
|
carveout->client_force_internal_access_2 = 0;
|
||||||
carveout->flags_8 = 0;
|
carveout->client_force_internal_access_3 = 0;
|
||||||
carveout->flags_9 = 0;
|
carveout->client_force_internal_access_4 = 0;
|
||||||
carveout->allowed_clients = 0x440167E;
|
carveout->config = 0x440167E;
|
||||||
}
|
}
|
||||||
|
|
||||||
void configure_default_carveouts(void) {
|
void configure_default_carveouts(void) {
|
||||||
|
@ -64,17 +64,17 @@ void configure_default_carveouts(void) {
|
||||||
carveout->paddr_low = 0;
|
carveout->paddr_low = 0;
|
||||||
carveout->paddr_high = 0;
|
carveout->paddr_high = 0;
|
||||||
carveout->size_big_pages = 0;
|
carveout->size_big_pages = 0;
|
||||||
carveout->flags_0 = 0;
|
carveout->client_access_0 = 0;
|
||||||
carveout->flags_1 = 0;
|
carveout->client_access_1 = 0;
|
||||||
carveout->flags_2 = 0;
|
carveout->client_access_2 = 0;
|
||||||
carveout->flags_3 = 0;
|
carveout->client_access_3 = 0;
|
||||||
carveout->flags_4 = 0;
|
carveout->client_access_4 = 0;
|
||||||
carveout->flags_5 = 0;
|
carveout->client_force_internal_access_0 = 0;
|
||||||
carveout->flags_6 = 0;
|
carveout->client_force_internal_access_1 = 0;
|
||||||
carveout->flags_7 = 0;
|
carveout->client_force_internal_access_2 = 0;
|
||||||
carveout->flags_8 = 0;
|
carveout->client_force_internal_access_3 = 0;
|
||||||
carveout->flags_9 = 0;
|
carveout->client_force_internal_access_4 = 0;
|
||||||
carveout->allowed_clients = 0x04000006;
|
carveout->config = 0x4000006;
|
||||||
|
|
||||||
/* Configure Carveout 2 (GPU UCODE) */
|
/* Configure Carveout 2 (GPU UCODE) */
|
||||||
if (exosphere_get_target_firmware() < EXOSPHERE_TARGET_FIRMWARE_600) {
|
if (exosphere_get_target_firmware() < EXOSPHERE_TARGET_FIRMWARE_600) {
|
||||||
|
@ -86,17 +86,17 @@ void configure_default_carveouts(void) {
|
||||||
carveout->paddr_low = 0;
|
carveout->paddr_low = 0;
|
||||||
carveout->paddr_high = 0;
|
carveout->paddr_high = 0;
|
||||||
carveout->size_big_pages = 0;
|
carveout->size_big_pages = 0;
|
||||||
carveout->flags_0 = 0;
|
carveout->client_access_0 = 0;
|
||||||
carveout->flags_1 = 0;
|
carveout->client_access_1 = 0;
|
||||||
carveout->flags_2 = 0x3000000;
|
carveout->client_access_2 = (BIT(CSR_GPUSRD) | BIT(CSW_GPUSWR));
|
||||||
carveout->flags_3 = 0;
|
carveout->client_access_3 = 0;
|
||||||
carveout->flags_4 = 0x300;
|
carveout->client_access_4 = (BIT(CSR_GPUSRD2) | BIT(CSW_GPUSWR2));
|
||||||
carveout->flags_5 = 0;
|
carveout->client_force_internal_access_0 = 0;
|
||||||
carveout->flags_6 = 0;
|
carveout->client_force_internal_access_1 = 0;
|
||||||
carveout->flags_7 = 0;
|
carveout->client_force_internal_access_2 = 0;
|
||||||
carveout->flags_8 = 0;
|
carveout->client_force_internal_access_3 = 0;
|
||||||
carveout->flags_9 = 0;
|
carveout->client_force_internal_access_4 = 0;
|
||||||
carveout->allowed_clients = 0x4401E7E;
|
carveout->config = 0x4401E7E;
|
||||||
|
|
||||||
/* Configure default Kernel carveouts based on 2.0.0+. */
|
/* Configure default Kernel carveouts based on 2.0.0+. */
|
||||||
if (exosphere_get_target_firmware() >= EXOSPHERE_TARGET_FIRMWARE_200) {
|
if (exosphere_get_target_firmware() >= EXOSPHERE_TARGET_FIRMWARE_200) {
|
||||||
|
@ -111,17 +111,17 @@ void configure_default_carveouts(void) {
|
||||||
carveout->paddr_low = 0;
|
carveout->paddr_low = 0;
|
||||||
carveout->paddr_high = 0;
|
carveout->paddr_high = 0;
|
||||||
carveout->size_big_pages = 0;
|
carveout->size_big_pages = 0;
|
||||||
carveout->flags_0 = 0;
|
carveout->client_access_0 = 0;
|
||||||
carveout->flags_1 = 0;
|
carveout->client_access_1 = 0;
|
||||||
carveout->flags_2 = 0;
|
carveout->client_access_2 = 0;
|
||||||
carveout->flags_3 = 0;
|
carveout->client_access_3 = 0;
|
||||||
carveout->flags_4 = 0;
|
carveout->client_access_4 = 0;
|
||||||
carveout->flags_5 = 0;
|
carveout->client_force_internal_access_0 = 0;
|
||||||
carveout->flags_6 = 0;
|
carveout->client_force_internal_access_1 = 0;
|
||||||
carveout->flags_7 = 0;
|
carveout->client_force_internal_access_2 = 0;
|
||||||
carveout->flags_8 = 0;
|
carveout->client_force_internal_access_3 = 0;
|
||||||
carveout->flags_9 = 0;
|
carveout->client_force_internal_access_4 = 0;
|
||||||
carveout->allowed_clients = 0x4000006;
|
carveout->config = 0x4000006;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
@ -138,15 +138,15 @@ void configure_kernel_carveout(unsigned int carveout_id, uint64_t address, uint6
|
||||||
carveout->paddr_low = (uint32_t)(address & 0xFFFFFFFF);
|
carveout->paddr_low = (uint32_t)(address & 0xFFFFFFFF);
|
||||||
carveout->paddr_high = (uint32_t)(address >> 32);
|
carveout->paddr_high = (uint32_t)(address >> 32);
|
||||||
carveout->size_big_pages = (uint32_t)(size >> 17);
|
carveout->size_big_pages = (uint32_t)(size >> 17);
|
||||||
carveout->flags_0 = 0x70E3407F;
|
carveout->client_access_0 = (BIT(CSR_PTCR) | BIT(CSR_DISPLAY0A) | BIT(CSR_DISPLAY0AB) | BIT(CSR_DISPLAY0B) | BIT(CSR_DISPLAY0BB) | BIT(CSR_DISPLAY0C) | BIT(CSR_DISPLAY0CB) | BIT(CSR_AFIR) | BIT(CSR_DISPLAYHC) | BIT(CSR_DISPLAYHCB) | BIT(CSR_HDAR) | BIT(CSR_HOST1XDMAR) | BIT(CSR_HOST1XR) | BIT(CSR_NVENCSRD) | BIT(CSR_PPCSAHBDMAR) | BIT(CSR_PPCSAHBSLVR));
|
||||||
carveout->flags_1 = 0x1A620880;
|
carveout->client_access_1 = (BIT(CSR_MPCORER) | BIT(CSW_NVENCSWR) | BIT(CSW_AFIW) | BIT(CSW_HDAW) | BIT(CSW_HOST1XW) | BIT(CSW_MPCOREW) | BIT(CSW_PPCSAHBDMAW) | BIT(CSW_PPCSAHBSLVW));
|
||||||
carveout->flags_2 = 0x303C00;
|
carveout->client_access_2 = (BIT(CSR_XUSB_HOSTR) | BIT(CSW_XUSB_HOSTW) | BIT(CSR_XUSB_DEVR) | BIT(CSW_XUSB_DEVW) | BIT(CSR_TSECSRD) | BIT(CSW_TSECSWR));
|
||||||
carveout->flags_3 = 0xCF0830BB;
|
carveout->client_access_3 = (BIT(CSR_SDMMCRA) | BIT(CSR_SDMMCRAA) | BIT(CSR_SDMMCRAB) | BIT(CSW_SDMMCWA) | BIT(CSW_SDMMCWAA) | BIT(CSW_SDMMCWAB) | BIT(CSR_VICSRD) | BIT(CSW_VICSWR) | BIT(CSR_DISPLAYD) | BIT(CSR_NVDECSRD) | BIT(CSW_NVDECSWR) | BIT(CSR_APER) | BIT(CSW_APEW) | BIT(CSR_NVJPGSRD) | BIT(CSW_NVJPGSWR));
|
||||||
carveout->flags_4 = 0x3;
|
carveout->client_access_4 = (BIT(CSR_SESRD) | BIT(CSW_SESWR));
|
||||||
carveout->flags_5 = exosphere_get_target_firmware() >= EXOSPHERE_TARGET_FIRMWARE_400 && carveout_id == 4 ? 0x8000 : 0;
|
carveout->client_force_internal_access_0 = ((exosphere_get_target_firmware() >= EXOSPHERE_TARGET_FIRMWARE_400) && (carveout_id == 4)) ? BIT(CSR_AVPCARM7R) : 0;
|
||||||
carveout->flags_6 = exosphere_get_target_firmware() >= EXOSPHERE_TARGET_FIRMWARE_400 && carveout_id == 4 ? 0x40000 : 0;
|
carveout->client_force_internal_access_1 = ((exosphere_get_target_firmware() >= EXOSPHERE_TARGET_FIRMWARE_400) && (carveout_id == 4)) ? BIT(CSW_AVPCARM7W) : 0;
|
||||||
carveout->flags_7 = 0;
|
carveout->client_force_internal_access_2 = 0;
|
||||||
carveout->flags_8 = 0;
|
carveout->client_force_internal_access_3 = 0;
|
||||||
carveout->flags_9 = 0;
|
carveout->client_force_internal_access_4 = 0;
|
||||||
carveout->allowed_clients = 0x8B;
|
carveout->config = 0x8B;
|
||||||
}
|
}
|
||||||
|
|
|
@ -27,60 +27,594 @@ static inline uintptr_t get_mc_base(void) {
|
||||||
}
|
}
|
||||||
|
|
||||||
#define MC_BASE (get_mc_base())
|
#define MC_BASE (get_mc_base())
|
||||||
|
|
||||||
#define MAKE_MC_REG(n) MAKE_REG32(MC_BASE + n)
|
#define MAKE_MC_REG(n) MAKE_REG32(MC_BASE + n)
|
||||||
|
|
||||||
#define MC_SMMU_CONFIG_0 MAKE_MC_REG(0x010)
|
#define MC_INTSTATUS 0x0
|
||||||
#define MC_SMMU_TLB_CONFIG_0 MAKE_MC_REG(0x014)
|
#define MC_INTMASK 0x4
|
||||||
#define MC_SMMU_PTC_CONFIG_0 MAKE_MC_REG(0x018)
|
#define MC_ERR_STATUS 0x8
|
||||||
#define MC_SMMU_PTB_ASID_0 MAKE_MC_REG(0x01C)
|
#define MC_ERR_ADR 0xc
|
||||||
#define MC_SMMU_PTB_DATA_0 MAKE_MC_REG(0x020)
|
#define MC_SMMU_CONFIG 0x10
|
||||||
#define MC_SMMU_TLB_FLUSH_0 MAKE_MC_REG(0x030)
|
#define MC_SMMU_TLB_CONFIG 0x14
|
||||||
#define MC_SMMU_PTC_FLUSH_0 MAKE_MC_REG(0x034)
|
#define MC_SMMU_PTC_CONFIG 0x18
|
||||||
#define MC_SMMU_AFI_ASID_0 MAKE_MC_REG(0x238)
|
#define MC_SMMU_PTB_ASID 0x1c
|
||||||
#define MC_SMMU_AVPC_ASID_0 MAKE_MC_REG(0x23C)
|
#define MC_SMMU_PTB_DATA 0x20
|
||||||
|
#define MC_SMMU_TLB_FLUSH 0x30
|
||||||
|
#define MC_SMMU_PTC_FLUSH 0x34
|
||||||
|
#define MC_SMMU_AFI_ASID 0x238
|
||||||
|
#define MC_SMMU_AVPC_ASID 0x23c
|
||||||
|
#define MC_SMMU_PPCS1_ASID 0x298
|
||||||
|
#define MC_SMMU_TRANSLATION_ENABLE_0 0x228
|
||||||
|
#define MC_SMMU_TRANSLATION_ENABLE_1 0x22c
|
||||||
|
#define MC_SMMU_TRANSLATION_ENABLE_2 0x230
|
||||||
|
#define MC_SMMU_TRANSLATION_ENABLE_3 0x234
|
||||||
|
#define MC_SMMU_TRANSLATION_ENABLE_4 0xb98
|
||||||
|
#define MC_PCFIFO_CLIENT_CONFIG0 0xdd0
|
||||||
|
#define MC_PCFIFO_CLIENT_CONFIG1 0xdd4
|
||||||
|
#define MC_PCFIFO_CLIENT_CONFIG2 0xdd8
|
||||||
|
#define MC_PCFIFO_CLIENT_CONFIG3 0xddc
|
||||||
|
#define MC_PCFIFO_CLIENT_CONFIG4 0xde0
|
||||||
|
#define MC_EMEM_CFG 0x50
|
||||||
|
#define MC_EMEM_ADR_CFG 0x54
|
||||||
|
#define MC_EMEM_ADR_CFG_DEV0 0x58
|
||||||
|
#define MC_EMEM_ADR_CFG_DEV1 0x5c
|
||||||
|
#define MC_EMEM_ADR_CFG_CHANNEL_MASK 0x60
|
||||||
|
#define MC_EMEM_ADR_CFG_BANK_MASK_0 0x64
|
||||||
|
#define MC_EMEM_ADR_CFG_BANK_MASK_1 0x68
|
||||||
|
#define MC_EMEM_ADR_CFG_BANK_MASK_2 0x6c
|
||||||
|
#define MC_SECURITY_CFG0 0x70
|
||||||
|
#define MC_SECURITY_CFG1 0x74
|
||||||
|
#define MC_SECURITY_CFG3 0x9bc
|
||||||
|
#define MC_SECURITY_RSV 0x7c
|
||||||
|
#define MC_EMEM_ARB_CFG 0x90
|
||||||
|
#define MC_EMEM_ARB_OUTSTANDING_REQ 0x94
|
||||||
|
#define MC_EMEM_ARB_TIMING_RCD 0x98
|
||||||
|
#define MC_EMEM_ARB_TIMING_RP 0x9c
|
||||||
|
#define MC_EMEM_ARB_TIMING_RC 0xa0
|
||||||
|
#define MC_EMEM_ARB_TIMING_RAS 0xa4
|
||||||
|
#define MC_EMEM_ARB_TIMING_FAW 0xa8
|
||||||
|
#define MC_EMEM_ARB_TIMING_RRD 0xac
|
||||||
|
#define MC_EMEM_ARB_TIMING_RAP2PRE 0xb0
|
||||||
|
#define MC_EMEM_ARB_TIMING_WAP2PRE 0xb4
|
||||||
|
#define MC_EMEM_ARB_TIMING_R2R 0xb8
|
||||||
|
#define MC_EMEM_ARB_TIMING_W2W 0xbc
|
||||||
|
#define MC_EMEM_ARB_TIMING_R2W 0xc0
|
||||||
|
#define MC_EMEM_ARB_TIMING_W2R 0xc4
|
||||||
|
#define MC_EMEM_ARB_TIMING_RFCPB 0x6c0
|
||||||
|
#define MC_EMEM_ARB_TIMING_CCDMW 0x6c4
|
||||||
|
#define MC_EMEM_ARB_REFPB_HP_CTRL 0x6f0
|
||||||
|
#define MC_EMEM_ARB_REFPB_BANK_CTRL 0x6f4
|
||||||
|
#define MC_EMEM_ARB_DA_TURNS 0xd0
|
||||||
|
#define MC_EMEM_ARB_DA_COVERS 0xd4
|
||||||
|
#define MC_EMEM_ARB_MISC0 0xd8
|
||||||
|
#define MC_EMEM_ARB_MISC1 0xdc
|
||||||
|
#define MC_EMEM_ARB_MISC2 0xc8
|
||||||
|
#define MC_EMEM_ARB_RING1_THROTTLE 0xe0
|
||||||
|
#define MC_EMEM_ARB_RING3_THROTTLE 0xe4
|
||||||
|
#define MC_EMEM_ARB_NISO_THROTTLE 0x6b0
|
||||||
|
#define MC_EMEM_ARB_OVERRIDE 0xe8
|
||||||
|
#define MC_EMEM_ARB_RSV 0xec
|
||||||
|
#define MC_CLKEN_OVERRIDE 0xf4
|
||||||
|
#define MC_TIMING_CONTROL_DBG 0xf8
|
||||||
|
#define MC_TIMING_CONTROL 0xfc
|
||||||
|
#define MC_STAT_CONTROL 0x100
|
||||||
|
#define MC_STAT_STATUS 0x104
|
||||||
|
#define MC_STAT_EMC_CLOCK_LIMIT 0x108
|
||||||
|
#define MC_STAT_EMC_CLOCK_LIMIT_MSBS 0x10c
|
||||||
|
#define MC_STAT_EMC_CLOCKS 0x110
|
||||||
|
#define MC_STAT_EMC_CLOCKS_MSBS 0x114
|
||||||
|
#define MC_STAT_EMC_FILTER_SET0_ADR_LIMIT_LO 0x118
|
||||||
|
#define MC_STAT_EMC_FILTER_SET1_ADR_LIMIT_LO 0x158
|
||||||
|
#define MC_STAT_EMC_FILTER_SET0_ADR_LIMIT_HI 0x11c
|
||||||
|
#define MC_STAT_EMC_FILTER_SET1_ADR_LIMIT_HI 0x15c
|
||||||
|
#define MC_STAT_EMC_FILTER_SET0_ADR_LIMIT_UPPER 0xa20
|
||||||
|
#define MC_STAT_EMC_FILTER_SET1_ADR_LIMIT_UPPER 0xa24
|
||||||
|
#define MC_STAT_EMC_FILTER_SET0_VIRTUAL_ADR_LIMIT_LO 0x198
|
||||||
|
#define MC_STAT_EMC_FILTER_SET1_VIRTUAL_ADR_LIMIT_LO 0x1a8
|
||||||
|
#define MC_STAT_EMC_FILTER_SET0_VIRTUAL_ADR_LIMIT_HI 0x19c
|
||||||
|
#define MC_STAT_EMC_FILTER_SET1_VIRTUAL_ADR_LIMIT_HI 0x1ac
|
||||||
|
#define MC_STAT_EMC_FILTER_SET0_VIRTUAL_ADR_LIMIT_UPPER 0xa28
|
||||||
|
#define MC_STAT_EMC_FILTER_SET1_VIRTUAL_ADR_LIMIT_UPPER 0xa2c
|
||||||
|
#define MC_STAT_EMC_FILTER_SET0_ASID 0x1a0
|
||||||
|
#define MC_STAT_EMC_FILTER_SET1_ASID 0x1b0
|
||||||
|
#define MC_STAT_EMC_FILTER_SET0_SLACK_LIMIT 0x120
|
||||||
|
#define MC_STAT_EMC_FILTER_SET1_SLACK_LIMIT 0x160
|
||||||
|
#define MC_STAT_EMC_FILTER_SET0_CLIENT_0 0x128
|
||||||
|
#define MC_STAT_EMC_FILTER_SET1_CLIENT_0 0x168
|
||||||
|
#define MC_STAT_EMC_FILTER_SET0_CLIENT_1 0x12c
|
||||||
|
#define MC_STAT_EMC_FILTER_SET1_CLIENT_1 0x16c
|
||||||
|
#define MC_STAT_EMC_FILTER_SET0_CLIENT_2 0x130
|
||||||
|
#define MC_STAT_EMC_FILTER_SET1_CLIENT_2 0x170
|
||||||
|
#define MC_STAT_EMC_FILTER_SET0_CLIENT_3 0x134
|
||||||
|
#define MC_STAT_EMC_FILTER_SET0_CLIENT_4 0xb88
|
||||||
|
#define MC_STAT_EMC_FILTER_SET1_CLIENT_3 0x174
|
||||||
|
#define MC_STAT_EMC_FILTER_SET1_CLIENT_4 0xb8c
|
||||||
|
#define MC_STAT_EMC_SET0_COUNT 0x138
|
||||||
|
#define MC_STAT_EMC_SET0_COUNT_MSBS 0x13c
|
||||||
|
#define MC_STAT_EMC_SET1_COUNT 0x178
|
||||||
|
#define MC_STAT_EMC_SET1_COUNT_MSBS 0x17c
|
||||||
|
#define MC_STAT_EMC_SET0_SLACK_ACCUM 0x140
|
||||||
|
#define MC_STAT_EMC_SET0_SLACK_ACCUM_MSBS 0x144
|
||||||
|
#define MC_STAT_EMC_SET1_SLACK_ACCUM 0x180
|
||||||
|
#define MC_STAT_EMC_SET1_SLACK_ACCUM_MSBS 0x184
|
||||||
|
#define MC_STAT_EMC_SET0_HISTO_COUNT 0x148
|
||||||
|
#define MC_STAT_EMC_SET0_HISTO_COUNT_MSBS 0x14c
|
||||||
|
#define MC_STAT_EMC_SET1_HISTO_COUNT 0x188
|
||||||
|
#define MC_STAT_EMC_SET1_HISTO_COUNT_MSBS 0x18c
|
||||||
|
#define MC_STAT_EMC_SET0_MINIMUM_SLACK_OBSERVED 0x150
|
||||||
|
#define MC_STAT_EMC_SET1_MINIMUM_SLACK_OBSERVED 0x190
|
||||||
|
#define MC_STAT_EMC_SET0_IDLE_CYCLE_COUNT 0x1b8
|
||||||
|
#define MC_STAT_EMC_SET0_IDLE_CYCL_COUNT_MSBS 0x1bc
|
||||||
|
#define MC_STAT_EMC_SET1_IDLE_CYCLE_COUNT 0x1c8
|
||||||
|
#define MC_STAT_EMC_SET1_IDLE_CYCL_COUNT_MSBS 0x1cc
|
||||||
|
#define MC_STAT_EMC_SET0_IDLE_CYCLE_PARTITION_SELECT 0x1c0
|
||||||
|
#define MC_STAT_EMC_SET1_IDLE_CYCLE_PARTITION_SELECT 0x1d0
|
||||||
|
#define MC_CLIENT_HOTRESET_CTRL 0x200
|
||||||
|
#define MC_CLIENT_HOTRESET_CTRL_1 0x970
|
||||||
|
#define MC_CLIENT_HOTRESET_STATUS 0x204
|
||||||
|
#define MC_CLIENT_HOTRESET_STATUS_1 0x974
|
||||||
|
#define MC_EMEM_ARB_ISOCHRONOUS_0 0x208
|
||||||
|
#define MC_EMEM_ARB_ISOCHRONOUS_1 0x20c
|
||||||
|
#define MC_EMEM_ARB_ISOCHRONOUS_2 0x210
|
||||||
|
#define MC_EMEM_ARB_ISOCHRONOUS_3 0x214
|
||||||
|
#define MC_EMEM_ARB_ISOCHRONOUS_4 0xb94
|
||||||
|
#define MC_EMEM_ARB_HYSTERESIS_0 0x218
|
||||||
|
#define MC_EMEM_ARB_HYSTERESIS_1 0x21c
|
||||||
|
#define MC_EMEM_ARB_HYSTERESIS_2 0x220
|
||||||
|
#define MC_EMEM_ARB_HYSTERESIS_3 0x224
|
||||||
|
#define MC_EMEM_ARB_HYSTERESIS_4 0xb84
|
||||||
|
#define MC_EMEM_ARB_DHYSTERESIS_0 0xbb0
|
||||||
|
#define MC_EMEM_ARB_DHYSTERESIS_1 0xbb4
|
||||||
|
#define MC_EMEM_ARB_DHYSTERESIS_2 0xbb8
|
||||||
|
#define MC_EMEM_ARB_DHYSTERESIS_3 0xbbc
|
||||||
|
#define MC_EMEM_ARB_DHYSTERESIS_4 0xbc0
|
||||||
|
#define MC_EMEM_ARB_DHYST_CTRL 0xbcc
|
||||||
|
#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0 0xbd0
|
||||||
|
#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1 0xbd4
|
||||||
|
#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2 0xbd8
|
||||||
|
#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3 0xbdc
|
||||||
|
#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4 0xbe0
|
||||||
|
#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5 0xbe4
|
||||||
|
#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6 0xbe8
|
||||||
|
#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7 0xbec
|
||||||
|
#define MC_RESERVED_RSV 0x3fc
|
||||||
|
#define MC_DISB_EXTRA_SNAP_LEVELS 0x408
|
||||||
|
#define MC_APB_EXTRA_SNAP_LEVELS 0x2a4
|
||||||
|
#define MC_AHB_EXTRA_SNAP_LEVELS 0x2a0
|
||||||
|
#define MC_USBD_EXTRA_SNAP_LEVELS 0xa18
|
||||||
|
#define MC_ISP_EXTRA_SNAP_LEVELS 0xa08
|
||||||
|
#define MC_AUD_EXTRA_SNAP_LEVELS 0xa10
|
||||||
|
#define MC_MSE_EXTRA_SNAP_LEVELS 0x40c
|
||||||
|
#define MC_GK2_EXTRA_SNAP_LEVELS 0xa40
|
||||||
|
#define MC_A9AVPPC_EXTRA_SNAP_LEVELS 0x414
|
||||||
|
#define MC_FTOP_EXTRA_SNAP_LEVELS 0x2bc
|
||||||
|
#define MC_JPG_EXTRA_SNAP_LEVELS 0xa3c
|
||||||
|
#define MC_HOST_EXTRA_SNAP_LEVELS 0xa14
|
||||||
|
#define MC_SAX_EXTRA_SNAP_LEVELS 0x2c0
|
||||||
|
#define MC_DIS_EXTRA_SNAP_LEVELS 0x2ac
|
||||||
|
#define MC_VICPC_EXTRA_SNAP_LEVELS 0xa1c
|
||||||
|
#define MC_HDAPC_EXTRA_SNAP_LEVELS 0xa48
|
||||||
|
#define MC_AVP_EXTRA_SNAP_LEVELS 0x2a8
|
||||||
|
#define MC_USBX_EXTRA_SNAP_LEVELS 0x404
|
||||||
|
#define MC_PCX_EXTRA_SNAP_LEVELS 0x2b8
|
||||||
|
#define MC_SD_EXTRA_SNAP_LEVELS 0xa04
|
||||||
|
#define MC_DFD_EXTRA_SNAP_LEVELS 0xa4c
|
||||||
|
#define MC_VE_EXTRA_SNAP_LEVELS 0x2d8
|
||||||
|
#define MC_GK_EXTRA_SNAP_LEVELS 0xa00
|
||||||
|
#define MC_VE2_EXTRA_SNAP_LEVELS 0x410
|
||||||
|
#define MC_SDM_EXTRA_SNAP_LEVELS 0xa44
|
||||||
|
#define MC_VIDEO_PROTECT_BOM 0x648
|
||||||
|
#define MC_VIDEO_PROTECT_SIZE_MB 0x64c
|
||||||
|
#define MC_VIDEO_PROTECT_BOM_ADR_HI 0x978
|
||||||
|
#define MC_VIDEO_PROTECT_REG_CTRL 0x650
|
||||||
|
#define MC_ERR_VPR_STATUS 0x654
|
||||||
|
#define MC_ERR_VPR_ADR 0x658
|
||||||
|
#define MC_VIDEO_PROTECT_VPR_OVERRIDE 0x418
|
||||||
|
#define MC_VIDEO_PROTECT_VPR_OVERRIDE1 0x590
|
||||||
|
#define MC_IRAM_BOM 0x65c
|
||||||
|
#define MC_IRAM_TOM 0x660
|
||||||
|
#define MC_IRAM_ADR_HI 0x980
|
||||||
|
#define MC_IRAM_REG_CTRL 0x964
|
||||||
|
#define MC_EMEM_CFG_ACCESS_CTRL 0x664
|
||||||
|
#define MC_TZ_SECURITY_CTRL 0x668
|
||||||
|
#define MC_EMEM_ARB_OUTSTANDING_REQ_RING3 0x66c
|
||||||
|
#define MC_EMEM_ARB_OUTSTANDING_REQ_NISO 0x6b4
|
||||||
|
#define MC_EMEM_ARB_RING0_THROTTLE_MASK 0x6bc
|
||||||
|
#define MC_EMEM_ARB_NISO_THROTTLE_MASK 0x6b8
|
||||||
|
#define MC_EMEM_ARB_NISO_THROTTLE_MASK_1 0xb80
|
||||||
|
#define MC_SEC_CARVEOUT_BOM 0x670
|
||||||
|
#define MC_SEC_CARVEOUT_SIZE_MB 0x674
|
||||||
|
#define MC_SEC_CARVEOUT_ADR_HI 0x9d4
|
||||||
|
#define MC_SEC_CARVEOUT_REG_CTRL 0x678
|
||||||
|
#define MC_ERR_SEC_STATUS 0x67c
|
||||||
|
#define MC_ERR_SEC_ADR 0x680
|
||||||
|
#define MC_PC_IDLE_CLOCK_GATE_CONFIG 0x684
|
||||||
|
#define MC_STUTTER_CONTROL 0x688
|
||||||
|
#define MC_RESERVED_RSV_1 0x958
|
||||||
|
#define MC_DVFS_PIPE_SELECT 0x95c
|
||||||
|
#define MC_AHB_PTSA_MIN 0x4e0
|
||||||
|
#define MC_AUD_PTSA_MIN 0x54c
|
||||||
|
#define MC_MLL_MPCORER_PTSA_RATE 0x44c
|
||||||
|
#define MC_RING2_PTSA_RATE 0x440
|
||||||
|
#define MC_USBD_PTSA_RATE 0x530
|
||||||
|
#define MC_USBX_PTSA_MIN 0x528
|
||||||
|
#define MC_USBD_PTSA_MIN 0x534
|
||||||
|
#define MC_APB_PTSA_MAX 0x4f0
|
||||||
|
#define MC_JPG_PTSA_RATE 0x584
|
||||||
|
#define MC_DIS_PTSA_MIN 0x420
|
||||||
|
#define MC_AVP_PTSA_MAX 0x4fc
|
||||||
|
#define MC_AVP_PTSA_RATE 0x4f4
|
||||||
|
#define MC_RING1_PTSA_MIN 0x480
|
||||||
|
#define MC_DIS_PTSA_MAX 0x424
|
||||||
|
#define MC_SD_PTSA_MAX 0x4d8
|
||||||
|
#define MC_MSE_PTSA_RATE 0x4c4
|
||||||
|
#define MC_VICPC_PTSA_MIN 0x558
|
||||||
|
#define MC_PCX_PTSA_MAX 0x4b4
|
||||||
|
#define MC_ISP_PTSA_RATE 0x4a0
|
||||||
|
#define MC_A9AVPPC_PTSA_MIN 0x48c
|
||||||
|
#define MC_RING2_PTSA_MAX 0x448
|
||||||
|
#define MC_AUD_PTSA_RATE 0x548
|
||||||
|
#define MC_HOST_PTSA_MIN 0x51c
|
||||||
|
#define MC_MLL_MPCORER_PTSA_MAX 0x454
|
||||||
|
#define MC_SD_PTSA_MIN 0x4d4
|
||||||
|
#define MC_RING1_PTSA_RATE 0x47c
|
||||||
|
#define MC_JPG_PTSA_MIN 0x588
|
||||||
|
#define MC_HDAPC_PTSA_MIN 0x62c
|
||||||
|
#define MC_AVP_PTSA_MIN 0x4f8
|
||||||
|
#define MC_JPG_PTSA_MAX 0x58c
|
||||||
|
#define MC_VE_PTSA_MAX 0x43c
|
||||||
|
#define MC_DFD_PTSA_MAX 0x63c
|
||||||
|
#define MC_VICPC_PTSA_RATE 0x554
|
||||||
|
#define MC_GK_PTSA_MAX 0x544
|
||||||
|
#define MC_VICPC_PTSA_MAX 0x55c
|
||||||
|
#define MC_SDM_PTSA_MAX 0x624
|
||||||
|
#define MC_SAX_PTSA_RATE 0x4b8
|
||||||
|
#define MC_PCX_PTSA_MIN 0x4b0
|
||||||
|
#define MC_APB_PTSA_MIN 0x4ec
|
||||||
|
#define MC_GK2_PTSA_MIN 0x614
|
||||||
|
#define MC_PCX_PTSA_RATE 0x4ac
|
||||||
|
#define MC_RING1_PTSA_MAX 0x484
|
||||||
|
#define MC_HDAPC_PTSA_RATE 0x628
|
||||||
|
#define MC_MLL_MPCORER_PTSA_MIN 0x450
|
||||||
|
#define MC_GK2_PTSA_MAX 0x618
|
||||||
|
#define MC_AUD_PTSA_MAX 0x550
|
||||||
|
#define MC_GK2_PTSA_RATE 0x610
|
||||||
|
#define MC_ISP_PTSA_MAX 0x4a8
|
||||||
|
#define MC_DISB_PTSA_RATE 0x428
|
||||||
|
#define MC_VE2_PTSA_MAX 0x49c
|
||||||
|
#define MC_DFD_PTSA_MIN 0x638
|
||||||
|
#define MC_FTOP_PTSA_RATE 0x50c
|
||||||
|
#define MC_A9AVPPC_PTSA_RATE 0x488
|
||||||
|
#define MC_VE2_PTSA_MIN 0x498
|
||||||
|
#define MC_USBX_PTSA_MAX 0x52c
|
||||||
|
#define MC_DIS_PTSA_RATE 0x41c
|
||||||
|
#define MC_USBD_PTSA_MAX 0x538
|
||||||
|
#define MC_A9AVPPC_PTSA_MAX 0x490
|
||||||
|
#define MC_USBX_PTSA_RATE 0x524
|
||||||
|
#define MC_FTOP_PTSA_MAX 0x514
|
||||||
|
#define MC_HDAPC_PTSA_MAX 0x630
|
||||||
|
#define MC_SD_PTSA_RATE 0x4d0
|
||||||
|
#define MC_DFD_PTSA_RATE 0x634
|
||||||
|
#define MC_FTOP_PTSA_MIN 0x510
|
||||||
|
#define MC_SDM_PTSA_RATE 0x61c
|
||||||
|
#define MC_AHB_PTSA_RATE 0x4dc
|
||||||
|
#define MC_SMMU_SMMU_PTSA_MAX 0x460
|
||||||
|
#define MC_RING2_PTSA_MIN 0x444
|
||||||
|
#define MC_SDM_PTSA_MIN 0x620
|
||||||
|
#define MC_APB_PTSA_RATE 0x4e8
|
||||||
|
#define MC_MSE_PTSA_MIN 0x4c8
|
||||||
|
#define MC_HOST_PTSA_RATE 0x518
|
||||||
|
#define MC_VE_PTSA_RATE 0x434
|
||||||
|
#define MC_AHB_PTSA_MAX 0x4e4
|
||||||
|
#define MC_SAX_PTSA_MIN 0x4bc
|
||||||
|
#define MC_SMMU_SMMU_PTSA_MIN 0x45c
|
||||||
|
#define MC_ISP_PTSA_MIN 0x4a4
|
||||||
|
#define MC_HOST_PTSA_MAX 0x520
|
||||||
|
#define MC_SAX_PTSA_MAX 0x4c0
|
||||||
|
#define MC_VE_PTSA_MIN 0x438
|
||||||
|
#define MC_GK_PTSA_MIN 0x540
|
||||||
|
#define MC_MSE_PTSA_MAX 0x4cc
|
||||||
|
#define MC_DISB_PTSA_MAX 0x430
|
||||||
|
#define MC_DISB_PTSA_MIN 0x42c
|
||||||
|
#define MC_SMMU_SMMU_PTSA_RATE 0x458
|
||||||
|
#define MC_VE2_PTSA_RATE 0x494
|
||||||
|
#define MC_GK_PTSA_RATE 0x53c
|
||||||
|
#define MC_PTSA_GRANT_DECREMENT 0x960
|
||||||
|
#define MC_LATENCY_ALLOWANCE_AVPC_0 0x2e4
|
||||||
|
#define MC_LATENCY_ALLOWANCE_AXIAP_0 0x3a0
|
||||||
|
#define MC_LATENCY_ALLOWANCE_XUSB_1 0x380
|
||||||
|
#define MC_LATENCY_ALLOWANCE_ISP2B_0 0x384
|
||||||
|
#define MC_LATENCY_ALLOWANCE_SDMMCAA_0 0x3bc
|
||||||
|
#define MC_LATENCY_ALLOWANCE_SDMMCA_0 0x3b8
|
||||||
|
#define MC_LATENCY_ALLOWANCE_ISP2_0 0x370
|
||||||
|
#define MC_LATENCY_ALLOWANCE_SE_0 0x3e0
|
||||||
|
#define MC_LATENCY_ALLOWANCE_ISP2_1 0x374
|
||||||
|
#define MC_LATENCY_ALLOWANCE_DC_0 0x2e8
|
||||||
|
#define MC_LATENCY_ALLOWANCE_VIC_0 0x394
|
||||||
|
#define MC_LATENCY_ALLOWANCE_DCB_1 0x2f8
|
||||||
|
#define MC_LATENCY_ALLOWANCE_NVDEC_0 0x3d8
|
||||||
|
#define MC_LATENCY_ALLOWANCE_DCB_2 0x2fc
|
||||||
|
#define MC_LATENCY_ALLOWANCE_TSEC_0 0x390
|
||||||
|
#define MC_LATENCY_ALLOWANCE_DC_2 0x2f0
|
||||||
|
#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB 0x694
|
||||||
|
#define MC_LATENCY_ALLOWANCE_PPCS_1 0x348
|
||||||
|
#define MC_LATENCY_ALLOWANCE_XUSB_0 0x37c
|
||||||
|
#define MC_LATENCY_ALLOWANCE_PPCS_0 0x344
|
||||||
|
#define MC_LATENCY_ALLOWANCE_TSECB_0 0x3f0
|
||||||
|
#define MC_LATENCY_ALLOWANCE_AFI_0 0x2e0
|
||||||
|
#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B 0x698
|
||||||
|
#define MC_LATENCY_ALLOWANCE_DC_1 0x2ec
|
||||||
|
#define MC_LATENCY_ALLOWANCE_APE_0 0x3dc
|
||||||
|
#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C 0x6a0
|
||||||
|
#define MC_LATENCY_ALLOWANCE_A9AVP_0 0x3a4
|
||||||
|
#define MC_LATENCY_ALLOWANCE_GPU2_0 0x3e8
|
||||||
|
#define MC_LATENCY_ALLOWANCE_DCB_0 0x2f4
|
||||||
|
#define MC_LATENCY_ALLOWANCE_HC_1 0x314
|
||||||
|
#define MC_LATENCY_ALLOWANCE_SDMMC_0 0x3c0
|
||||||
|
#define MC_LATENCY_ALLOWANCE_NVJPG_0 0x3e4
|
||||||
|
#define MC_LATENCY_ALLOWANCE_PTC_0 0x34c
|
||||||
|
#define MC_LATENCY_ALLOWANCE_ETR_0 0x3ec
|
||||||
|
#define MC_LATENCY_ALLOWANCE_MPCORE_0 0x320
|
||||||
|
#define MC_LATENCY_ALLOWANCE_VI2_0 0x398
|
||||||
|
#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB 0x69c
|
||||||
|
#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB 0x6a4
|
||||||
|
#define MC_LATENCY_ALLOWANCE_SATA_0 0x350
|
||||||
|
#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A 0x690
|
||||||
|
#define MC_LATENCY_ALLOWANCE_HC_0 0x310
|
||||||
|
#define MC_LATENCY_ALLOWANCE_DC_3 0x3c8
|
||||||
|
#define MC_LATENCY_ALLOWANCE_GPU_0 0x3ac
|
||||||
|
#define MC_LATENCY_ALLOWANCE_SDMMCAB_0 0x3c4
|
||||||
|
#define MC_LATENCY_ALLOWANCE_ISP2B_1 0x388
|
||||||
|
#define MC_LATENCY_ALLOWANCE_NVENC_0 0x328
|
||||||
|
#define MC_LATENCY_ALLOWANCE_HDA_0 0x318
|
||||||
|
#define MC_MIN_LENGTH_APE_0 0xb34
|
||||||
|
#define MC_MIN_LENGTH_DCB_2 0x8a8
|
||||||
|
#define MC_MIN_LENGTH_A9AVP_0 0x950
|
||||||
|
#define MC_MIN_LENGTH_TSEC_0 0x93c
|
||||||
|
#define MC_MIN_LENGTH_DC_1 0x898
|
||||||
|
#define MC_MIN_LENGTH_AXIAP_0 0x94c
|
||||||
|
#define MC_MIN_LENGTH_ISP2B_0 0x930
|
||||||
|
#define MC_MIN_LENGTH_VI2_0 0x944
|
||||||
|
#define MC_MIN_LENGTH_DCB_0 0x8a0
|
||||||
|
#define MC_MIN_LENGTH_DCB_1 0x8a4
|
||||||
|
#define MC_MIN_LENGTH_PPCS_1 0x8f4
|
||||||
|
#define MC_MIN_LENGTH_NVJPG_0 0xb3c
|
||||||
|
#define MC_MIN_LENGTH_HDA_0 0x8c4
|
||||||
|
#define MC_MIN_LENGTH_NVENC_0 0x8d4
|
||||||
|
#define MC_MIN_LENGTH_SDMMC_0 0xb18
|
||||||
|
#define MC_MIN_LENGTH_ISP2B_1 0x934
|
||||||
|
#define MC_MIN_LENGTH_HC_1 0x8c0
|
||||||
|
#define MC_MIN_LENGTH_DC_3 0xb20
|
||||||
|
#define MC_MIN_LENGTH_AVPC_0 0x890
|
||||||
|
#define MC_MIN_LENGTH_VIC_0 0x940
|
||||||
|
#define MC_MIN_LENGTH_ISP2_0 0x91c
|
||||||
|
#define MC_MIN_LENGTH_HC_0 0x8bc
|
||||||
|
#define MC_MIN_LENGTH_SE_0 0xb38
|
||||||
|
#define MC_MIN_LENGTH_NVDEC_0 0xb30
|
||||||
|
#define MC_MIN_LENGTH_SATA_0 0x8fc
|
||||||
|
#define MC_MIN_LENGTH_DC_0 0x894
|
||||||
|
#define MC_MIN_LENGTH_XUSB_1 0x92c
|
||||||
|
#define MC_MIN_LENGTH_DC_2 0x89c
|
||||||
|
#define MC_MIN_LENGTH_SDMMCAA_0 0xb14
|
||||||
|
#define MC_MIN_LENGTH_GPU_0 0xb04
|
||||||
|
#define MC_MIN_LENGTH_ETR_0 0xb44
|
||||||
|
#define MC_MIN_LENGTH_AFI_0 0x88c
|
||||||
|
#define MC_MIN_LENGTH_PPCS_0 0x8f0
|
||||||
|
#define MC_MIN_LENGTH_ISP2_1 0x920
|
||||||
|
#define MC_MIN_LENGTH_XUSB_0 0x928
|
||||||
|
#define MC_MIN_LENGTH_MPCORE_0 0x8cc
|
||||||
|
#define MC_MIN_LENGTH_TSECB_0 0xb48
|
||||||
|
#define MC_MIN_LENGTH_SDMMCA_0 0xb10
|
||||||
|
#define MC_MIN_LENGTH_GPU2_0 0xb40
|
||||||
|
#define MC_MIN_LENGTH_SDMMCAB_0 0xb1c
|
||||||
|
#define MC_MIN_LENGTH_PTC_0 0x8f8
|
||||||
|
#define MC_EMEM_ARB_OVERRIDE_1 0x968
|
||||||
|
#define MC_VIDEO_PROTECT_GPU_OVERRIDE_0 0x984
|
||||||
|
#define MC_VIDEO_PROTECT_GPU_OVERRIDE_1 0x988
|
||||||
|
#define MC_EMEM_ARB_STATS_0 0x990
|
||||||
|
#define MC_EMEM_ARB_STATS_1 0x994
|
||||||
|
#define MC_MTS_CARVEOUT_BOM 0x9a0
|
||||||
|
#define MC_MTS_CARVEOUT_SIZE_MB 0x9a4
|
||||||
|
#define MC_MTS_CARVEOUT_ADR_HI 0x9a8
|
||||||
|
#define MC_MTS_CARVEOUT_REG_CTRL 0x9ac
|
||||||
|
#define MC_ERR_MTS_STATUS 0x9b0
|
||||||
|
#define MC_ERR_MTS_ADR 0x9b4
|
||||||
|
#define MC_ERR_GENERALIZED_CARVEOUT_STATUS 0xc00
|
||||||
|
#define MC_ERR_GENERALIZED_CARVEOUT_ADR 0xc04
|
||||||
|
#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS2 0xd74
|
||||||
|
#define MC_SECURITY_CARVEOUT4_CFG0 0xcf8
|
||||||
|
#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS2 0xd10
|
||||||
|
#define MC_SECURITY_CARVEOUT4_SIZE_128KB 0xd04
|
||||||
|
#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS4 0xc28
|
||||||
|
#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS1 0xc30
|
||||||
|
#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS4 0xc8c
|
||||||
|
#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS0 0xd1c
|
||||||
|
#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS1 0xd70
|
||||||
|
#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS0 0xc2c
|
||||||
|
#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS4 0xd7c
|
||||||
|
#define MC_SECURITY_CARVEOUT3_SIZE_128KB 0xcb4
|
||||||
|
#define MC_SECURITY_CARVEOUT2_CFG0 0xc58
|
||||||
|
#define MC_SECURITY_CARVEOUT1_CFG0 0xc08
|
||||||
|
#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS2 0xc84
|
||||||
|
#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS0 0xc68
|
||||||
|
#define MC_SECURITY_CARVEOUT3_BOM 0xcac
|
||||||
|
#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS2 0xc70
|
||||||
|
#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS3 0xd78
|
||||||
|
#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS0 0xc7c
|
||||||
|
#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS4 0xd18
|
||||||
|
#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS1 0xcbc
|
||||||
|
#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS3 0xc38
|
||||||
|
#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS2 0xc34
|
||||||
|
#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS2 0xcc0
|
||||||
|
#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS2 0xd60
|
||||||
|
#define MC_SECURITY_CARVEOUT3_CFG0 0xca8
|
||||||
|
#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS0 0xcb8
|
||||||
|
#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS3 0xc88
|
||||||
|
#define MC_SECURITY_CARVEOUT2_SIZE_128KB 0xc64
|
||||||
|
#define MC_SECURITY_CARVEOUT5_BOM_HI 0xd50
|
||||||
|
#define MC_SECURITY_CARVEOUT1_SIZE_128KB 0xc14
|
||||||
|
#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS3 0xd14
|
||||||
|
#define MC_SECURITY_CARVEOUT1_BOM 0xc0c
|
||||||
|
#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS4 0xd2c
|
||||||
|
#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS4 0xd68
|
||||||
|
#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS4 0xcc8
|
||||||
|
#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS0 0xd58
|
||||||
|
#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS2 0xd24
|
||||||
|
#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS3 0xcc4
|
||||||
|
#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS4 0xc78
|
||||||
|
#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS1 0xc1c
|
||||||
|
#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS0 0xc18
|
||||||
|
#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS3 0xd28
|
||||||
|
#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS1 0xd5c
|
||||||
|
#define MC_SECURITY_CARVEOUT3_BOM_HI 0xcb0
|
||||||
|
#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS3 0xcd8
|
||||||
|
#define MC_SECURITY_CARVEOUT2_BOM_HI 0xc60
|
||||||
|
#define MC_SECURITY_CARVEOUT4_BOM_HI 0xd00
|
||||||
|
#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS3 0xd64
|
||||||
|
#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS4 0xcdc
|
||||||
|
#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS1 0xc80
|
||||||
|
#define MC_SECURITY_CARVEOUT5_SIZE_128KB 0xd54
|
||||||
|
#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS1 0xd20
|
||||||
|
#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS2 0xcd4
|
||||||
|
#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS1 0xd0c
|
||||||
|
#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS3 0xc74
|
||||||
|
#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS0 0xccc
|
||||||
|
#define MC_SECURITY_CARVEOUT4_BOM 0xcfc
|
||||||
|
#define MC_SECURITY_CARVEOUT5_CFG0 0xd48
|
||||||
|
#define MC_SECURITY_CARVEOUT2_BOM 0xc5c
|
||||||
|
#define MC_SECURITY_CARVEOUT5_BOM 0xd4c
|
||||||
|
#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS3 0xc24
|
||||||
|
#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS0 0xd6c
|
||||||
|
#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS1 0xcd0
|
||||||
|
#define MC_SECURITY_CARVEOUT1_BOM_HI 0xc10
|
||||||
|
#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS2 0xc20
|
||||||
|
#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS4 0xc3c
|
||||||
|
#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS1 0xc6c
|
||||||
|
#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS0 0xd08
|
||||||
|
#define MC_ERR_APB_ASID_UPDATE_STATUS 0x9d0
|
||||||
|
#define MC_DA_CONFIG0 0x9dc
|
||||||
|
|
||||||
#define MC_SMMU_TRANSLATION_ENABLE_0_0 MAKE_MC_REG(0x228)
|
/* Memory Controller clients */
|
||||||
#define MC_SMMU_TRANSLATION_ENABLE_1_0 MAKE_MC_REG(0x22C)
|
#define CLIENT_ACCESS_NUM_CLIENTS 32
|
||||||
#define MC_SMMU_TRANSLATION_ENABLE_2_0 MAKE_MC_REG(0x230)
|
typedef enum {
|
||||||
#define MC_SMMU_TRANSLATION_ENABLE_3_0 MAKE_MC_REG(0x234)
|
/* _ACCESS0 */
|
||||||
#define MC_SMMU_TRANSLATION_ENABLE_4_0 MAKE_MC_REG(0xB98)
|
CSR_PTCR = (0 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
|
||||||
|
CSR_DISPLAY0A = (1 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
|
||||||
|
CSR_DISPLAY0AB = (2 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
|
||||||
|
CSR_DISPLAY0B = (3 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
|
||||||
|
CSR_DISPLAY0BB = (4 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
|
||||||
|
CSR_DISPLAY0C = (5 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
|
||||||
|
CSR_DISPLAY0CB = (6 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
|
||||||
|
CSR_AFIR = (14 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
|
||||||
|
CSR_AVPCARM7R = (15 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
|
||||||
|
CSR_DISPLAYHC = (16 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
|
||||||
|
CSR_DISPLAYHCB = (17 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
|
||||||
|
CSR_HDAR = (21 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
|
||||||
|
CSR_HOST1XDMAR = (22 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
|
||||||
|
CSR_HOST1XR = (23 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
|
||||||
|
CSR_NVENCSRD = (28 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
|
||||||
|
CSR_PPCSAHBDMAR = (29 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
|
||||||
|
CSR_PPCSAHBSLVR = (30 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
|
||||||
|
CSR_SATAR = (31 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
|
||||||
|
|
||||||
#define MC_SMMU_PPCS1_ASID_0 MAKE_MC_REG(0x298)
|
/* _ACCESS1 */
|
||||||
|
CSR_VDEBSEVR = (34 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
|
||||||
|
CSR_VDEMBER = (35 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
|
||||||
|
CSR_VDEMCER = (36 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
|
||||||
|
CSR_VDETPER = (37 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
|
||||||
|
CSR_MPCORELPR = (38 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
|
||||||
|
CSR_MPCORER = (39 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
|
||||||
|
CSW_NVENCSWR = (43 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
|
||||||
|
CSW_AFIW = (49 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
|
||||||
|
CSW_AVPCARM7W = (50 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
|
||||||
|
CSW_HDAW = (53 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
|
||||||
|
CSW_HOST1XW = (54 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
|
||||||
|
CSW_MPCORELPW = (56 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
|
||||||
|
CSW_MPCOREW = (57 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
|
||||||
|
CSW_PPCSAHBDMAW = (59 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
|
||||||
|
CSW_PPCSAHBSLVW = (60 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
|
||||||
|
CSW_SATAW = (61 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
|
||||||
|
CSW_VDEBSEVW = (62 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
|
||||||
|
CSW_VDEDBGW = (63 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
|
||||||
|
|
||||||
#define MC_SECURITY_CFG0_0 MAKE_MC_REG(0x070)
|
/* _ACCESS2 */
|
||||||
#define MC_SECURITY_CFG1_0 MAKE_MC_REG(0x074)
|
CSW_VDEMBEW = (64 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||||
#define MC_SECURITY_CFG3_0 MAKE_MC_REG(0x9BC)
|
CSW_VDETPMW = (65 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||||
|
CSR_ISPRA = (68 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||||
|
CSW_ISPWA = (70 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||||
|
CSW_ISPWB = (71 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||||
|
CSR_XUSB_HOSTR = (74 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||||
|
CSW_XUSB_HOSTW = (75 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||||
|
CSR_XUSB_DEVR = (76 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||||
|
CSW_XUSB_DEVW = (77 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||||
|
CSR_ISPRAB = (78 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||||
|
CSW_ISPWAB = (80 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||||
|
CSW_ISPWBB = (81 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||||
|
CSR_TSECSRD = (84 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||||
|
CSW_TSECSWR = (85 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||||
|
CSR_A9AVPSCR = (86 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||||
|
CSW_A9AVPSCW = (87 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||||
|
CSR_GPUSRD = (88 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||||
|
CSW_GPUSWR = (89 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||||
|
CSR_DISPLAYT = (90 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||||
|
|
||||||
|
/* _ACCESS3 */
|
||||||
|
CSR_SDMMCRA = (96 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
|
||||||
|
CSR_SDMMCRAA = (97 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
|
||||||
|
CSR_SDMMCR = (98 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
|
||||||
|
CSR_SDMMCRAB = (99 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
|
||||||
|
CSW_SDMMCWA = (100 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
|
||||||
|
CSW_SDMMCWAA = (101 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
|
||||||
|
CSW_SDMMCW = (102 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
|
||||||
|
CSW_SDMMCWAB = (103 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
|
||||||
|
CSR_VICSRD = (108 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
|
||||||
|
CSW_VICSWR = (109 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
|
||||||
|
CSW_VIW = (114 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
|
||||||
|
CSR_DISPLAYD = (115 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
|
||||||
|
CSR_NVDECSRD = (120 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
|
||||||
|
CSW_NVDECSWR = (121 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
|
||||||
|
CSR_APER = (122 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
|
||||||
|
CSW_APEW = (123 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
|
||||||
|
CSR_NVJPGSRD = (126 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
|
||||||
|
CSW_NVJPGSWR = (127 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
|
||||||
|
|
||||||
|
/* _ACCESS4 */
|
||||||
|
CSR_SESRD = (128 - (CLIENT_ACCESS_NUM_CLIENTS * 4)),
|
||||||
|
CSW_SESWR = (129 - (CLIENT_ACCESS_NUM_CLIENTS * 4)),
|
||||||
|
CSR_AXIAPR = (130 - (CLIENT_ACCESS_NUM_CLIENTS * 4)),
|
||||||
|
CSW_AXIAPW = (131 - (CLIENT_ACCESS_NUM_CLIENTS * 4)),
|
||||||
|
CSR_ETRR = (132 - (CLIENT_ACCESS_NUM_CLIENTS * 4)),
|
||||||
|
CSW_ETRW = (133 - (CLIENT_ACCESS_NUM_CLIENTS * 4)),
|
||||||
|
CSR_TSECSRDB = (134 - (CLIENT_ACCESS_NUM_CLIENTS * 4)),
|
||||||
|
CSW_TSECSWRB = (135 - (CLIENT_ACCESS_NUM_CLIENTS * 4)),
|
||||||
|
CSR_GPUSRD2 = (136 - (CLIENT_ACCESS_NUM_CLIENTS * 4)),
|
||||||
|
CSW_GPUSWR2 = (137 - (CLIENT_ACCESS_NUM_CLIENTS * 4))
|
||||||
|
} McClient;
|
||||||
|
|
||||||
|
/* Memory Controller carveouts */
|
||||||
#define CARVEOUT_ID_MIN 1
|
#define CARVEOUT_ID_MIN 1
|
||||||
#define CARVEOUT_ID_MAX 5
|
#define CARVEOUT_ID_MAX 5
|
||||||
|
|
||||||
#define KERNEL_CARVEOUT_SIZE_MAX 0x1FFE0000
|
#define KERNEL_CARVEOUT_SIZE_MAX 0x1FFE0000
|
||||||
|
|
||||||
typedef struct {
|
typedef struct {
|
||||||
uint32_t allowed_clients;
|
uint32_t config;
|
||||||
uint32_t paddr_low;
|
uint32_t paddr_low;
|
||||||
uint32_t paddr_high;
|
uint32_t paddr_high;
|
||||||
uint32_t size_big_pages;
|
uint32_t size_big_pages;
|
||||||
uint32_t flags_0;
|
uint32_t client_access_0;
|
||||||
uint32_t flags_1;
|
uint32_t client_access_1;
|
||||||
uint32_t flags_2;
|
uint32_t client_access_2;
|
||||||
uint32_t flags_3;
|
uint32_t client_access_3;
|
||||||
uint32_t flags_4;
|
uint32_t client_access_4;
|
||||||
uint32_t flags_5;
|
uint32_t client_force_internal_access_0;
|
||||||
uint32_t flags_6;
|
uint32_t client_force_internal_access_1;
|
||||||
uint32_t flags_7;
|
uint32_t client_force_internal_access_2;
|
||||||
uint32_t flags_8;
|
uint32_t client_force_internal_access_3;
|
||||||
uint32_t flags_9;
|
uint32_t client_force_internal_access_4;
|
||||||
uint8_t padding[0x18];
|
uint8_t padding[0x18];
|
||||||
} security_carveout_t;
|
} security_carveout_t;
|
||||||
|
|
||||||
|
|
||||||
volatile security_carveout_t *get_carveout_by_id(unsigned int carveout);
|
volatile security_carveout_t *get_carveout_by_id(unsigned int carveout);
|
||||||
void configure_default_carveouts(void);
|
void configure_default_carveouts(void);
|
||||||
void configure_gpu_ucode_carveout(void);
|
void configure_gpu_ucode_carveout(void);
|
||||||
void configure_kernel_carveout(unsigned int carveout_id, uint64_t address, uint64_t size);
|
void configure_kernel_carveout(unsigned int carveout_id, uint64_t address, uint64_t size);
|
||||||
|
|
||||||
|
|
||||||
#endif
|
#endif
|
|
@ -27,10 +27,11 @@ static inline uintptr_t get_timers_base(void) {
|
||||||
}
|
}
|
||||||
|
|
||||||
#define TIMERS_BASE (get_timers_base())
|
#define TIMERS_BASE (get_timers_base())
|
||||||
|
|
||||||
#define MAKE_TIMERS_REG(n) MAKE_REG32(TIMERS_BASE + n)
|
#define MAKE_TIMERS_REG(n) MAKE_REG32(TIMERS_BASE + n)
|
||||||
|
|
||||||
#define TIMERUS_CNTR_1US_0 MAKE_REG32(TIMERS_BASE + 0x10)
|
#define TIMERUS_CNTR_1US_0 MAKE_TIMERS_REG(0x10)
|
||||||
|
#define SHARED_INTR_STATUS_0 MAKE_TIMERS_REG(0x1A0)
|
||||||
|
#define SHARED_TIMER_SECURE_CFG_0 MAKE_TIMERS_REG(0x1A4)
|
||||||
|
|
||||||
typedef struct {
|
typedef struct {
|
||||||
uint32_t CONFIG;
|
uint32_t CONFIG;
|
||||||
|
@ -41,7 +42,7 @@ typedef struct {
|
||||||
|
|
||||||
#define GET_WDT(n) ((volatile watchdog_timers_t *)(TIMERS_BASE + 0x100 + 0x20 * n))
|
#define GET_WDT(n) ((volatile watchdog_timers_t *)(TIMERS_BASE + 0x100 + 0x20 * n))
|
||||||
#define WDT_REBOOT_PATTERN 0xC45A
|
#define WDT_REBOOT_PATTERN 0xC45A
|
||||||
#define GET_WDT_REBOOT_CFG_REG(n) MAKE_REG32(TIMERS_BASE + 0x60 + 0x8*n)
|
#define GET_WDT_REBOOT_CFG_REG(n) MAKE_REG32(TIMERS_BASE + 0x60 + 0x8 * n)
|
||||||
|
|
||||||
void wait(uint32_t microseconds);
|
void wait(uint32_t microseconds);
|
||||||
|
|
||||||
|
|
|
@ -199,7 +199,7 @@ void warmboot_init(void) {
|
||||||
invalidate_icache_all();
|
invalidate_icache_all();
|
||||||
|
|
||||||
/* On warmboot (not cpu_on) only */
|
/* On warmboot (not cpu_on) only */
|
||||||
if (MC_SECURITY_CFG3_0 == 0) {
|
if (MC_SECURITY_CFG3 == 0) {
|
||||||
init_dma_controllers(g_exosphere_target_firmware_for_init);
|
init_dma_controllers(g_exosphere_target_firmware_for_init);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -54,7 +54,7 @@ void __attribute__((noreturn)) warmboot_main(void) {
|
||||||
identity_unmap_iram_cd_tzram();
|
identity_unmap_iram_cd_tzram();
|
||||||
|
|
||||||
/* On warmboot (not cpu_on) only */
|
/* On warmboot (not cpu_on) only */
|
||||||
if (MC_SECURITY_CFG3_0 == 0) {
|
if (MC_SECURITY_CFG3 == 0) {
|
||||||
if (!configitem_is_retail()) {
|
if (!configitem_is_retail()) {
|
||||||
/* TODO: uart_log("OHAYO"); */
|
/* TODO: uart_log("OHAYO"); */
|
||||||
}
|
}
|
||||||
|
|
|
@ -213,8 +213,8 @@ void nx_hwinit()
|
||||||
APB_MISC_PP_PINMUX_GLOBAL_0 = 0;
|
APB_MISC_PP_PINMUX_GLOBAL_0 = 0;
|
||||||
|
|
||||||
/* Configure GPIOs. */
|
/* Configure GPIOs. */
|
||||||
/* NOTE: In 3.x+ part of the GPIO configuration is skipped if the unit is SDEV. */
|
/* NOTE: [3.0.0+] Part of the GPIO configuration is skipped if the unit is SDEV. */
|
||||||
/* NOTE: In 6.x+ the GPIO configuration's order was changed a bit. */
|
/* NOTE: [6.0.0+] The GPIO configuration's order was changed a bit. */
|
||||||
config_gpios();
|
config_gpios();
|
||||||
|
|
||||||
/* Uncomment for UART debugging. */
|
/* Uncomment for UART debugging. */
|
||||||
|
@ -233,14 +233,14 @@ void nx_hwinit()
|
||||||
clkrst_reboot(CARDEVICE_I2C5);
|
clkrst_reboot(CARDEVICE_I2C5);
|
||||||
|
|
||||||
/* Reboot SE. */
|
/* Reboot SE. */
|
||||||
/* NOTE: In 4.x+ this was removed. */
|
/* NOTE: [4.0.0+] This was removed. */
|
||||||
clkrst_reboot(CARDEVICE_SE);
|
clkrst_reboot(CARDEVICE_SE);
|
||||||
|
|
||||||
/* Reboot unknown device. */
|
/* Reboot unknown device. */
|
||||||
clkrst_reboot(CARDEVICE_UNK);
|
clkrst_reboot(CARDEVICE_UNK);
|
||||||
|
|
||||||
/* Initialize I2C1. */
|
/* Initialize I2C1. */
|
||||||
/* NOTE: In 6.x+ this was moved to after the PMIC is configured. */
|
/* NOTE: [6.0.0+] This was moved to after the PMIC is configured. */
|
||||||
i2c_init(I2C_1);
|
i2c_init(I2C_1);
|
||||||
|
|
||||||
/* Initialize I2C5. */
|
/* Initialize I2C5. */
|
||||||
|
@ -268,11 +268,9 @@ void nx_hwinit()
|
||||||
val = 0x1B;
|
val = 0x1B;
|
||||||
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_FPS_SD3, &val, 1);
|
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_FPS_SD3, &val, 1);
|
||||||
|
|
||||||
/* TODO: In 3.x+ this was added. */
|
/* NOTE: [3.0.0+] This was added. */
|
||||||
/*
|
|
||||||
val = 0x22;
|
val = 0x22;
|
||||||
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_FPS_GPIO3, &val, 1);
|
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_FPS_GPIO3, &val, 1);
|
||||||
*/
|
|
||||||
|
|
||||||
/* TODO: In 3.x+, if the unit is SDEV, the MBLPD bit is set. */
|
/* TODO: In 3.x+, if the unit is SDEV, the MBLPD bit is set. */
|
||||||
/*
|
/*
|
||||||
|
@ -286,15 +284,15 @@ void nx_hwinit()
|
||||||
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_SD0, &val, 1);
|
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_SD0, &val, 1);
|
||||||
|
|
||||||
/* Configure and lock PMC scratch registers. */
|
/* Configure and lock PMC scratch registers. */
|
||||||
/* NOTE: In 4.x+ this was removed. */
|
/* NOTE: [4.0.0+] This was removed. */
|
||||||
config_pmc_scratch();
|
config_pmc_scratch();
|
||||||
|
|
||||||
/* Set super clock burst policy. */
|
/* Set super clock burst policy. */
|
||||||
car->sclk_brst_pol = ((car->sclk_brst_pol & 0xFFFF8888) | 0x3333);
|
car->sclk_brst_pol = ((car->sclk_brst_pol & 0xFFFF8888) | 0x3333);
|
||||||
|
|
||||||
/* Configure memory controller carveouts. */
|
/* Configure memory controller carveouts. */
|
||||||
/* NOTE: In 4.x+ this was removed. */
|
/* NOTE: [4.0.0+] This is now done in the Secure Monitor. */
|
||||||
mc_config_carveout();
|
/* mc_config_carveout(); */
|
||||||
|
|
||||||
/* Initialize SDRAM. */
|
/* Initialize SDRAM. */
|
||||||
sdram_init();
|
sdram_init();
|
||||||
|
|
|
@ -31,6 +31,7 @@ void mc_config_tsec_carveout(uint32_t bom, uint32_t size1mb, bool lock)
|
||||||
void mc_config_carveout()
|
void mc_config_carveout()
|
||||||
{
|
{
|
||||||
*(volatile uint32_t *)0x8005FFFC = 0xC0EDBBCC;
|
*(volatile uint32_t *)0x8005FFFC = 0xC0EDBBCC;
|
||||||
|
|
||||||
MAKE_MC_REG(MC_VIDEO_PROTECT_GPU_OVERRIDE_0) = 1;
|
MAKE_MC_REG(MC_VIDEO_PROTECT_GPU_OVERRIDE_0) = 1;
|
||||||
MAKE_MC_REG(MC_VIDEO_PROTECT_GPU_OVERRIDE_1) = 0;
|
MAKE_MC_REG(MC_VIDEO_PROTECT_GPU_OVERRIDE_1) = 0;
|
||||||
MAKE_MC_REG(MC_VIDEO_PROTECT_BOM) = 0;
|
MAKE_MC_REG(MC_VIDEO_PROTECT_BOM) = 0;
|
||||||
|
@ -43,6 +44,7 @@ void mc_config_carveout()
|
||||||
MAKE_MC_REG(MC_MTS_CARVEOUT_SIZE_MB) = 0;
|
MAKE_MC_REG(MC_MTS_CARVEOUT_SIZE_MB) = 0;
|
||||||
MAKE_MC_REG(MC_MTS_CARVEOUT_ADR_HI) = 0;
|
MAKE_MC_REG(MC_MTS_CARVEOUT_ADR_HI) = 0;
|
||||||
MAKE_MC_REG(MC_MTS_CARVEOUT_REG_CTRL) = 1;
|
MAKE_MC_REG(MC_MTS_CARVEOUT_REG_CTRL) = 1;
|
||||||
|
|
||||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT1_BOM) = 0;
|
MAKE_MC_REG(MC_SECURITY_CARVEOUT1_BOM) = 0;
|
||||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT1_BOM_HI) = 0;
|
MAKE_MC_REG(MC_SECURITY_CARVEOUT1_BOM_HI) = 0;
|
||||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT1_SIZE_128KB) = 0;
|
MAKE_MC_REG(MC_SECURITY_CARVEOUT1_SIZE_128KB) = 0;
|
||||||
|
@ -63,15 +65,16 @@ void mc_config_carveout()
|
||||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT3_SIZE_128KB) = 0;
|
MAKE_MC_REG(MC_SECURITY_CARVEOUT3_SIZE_128KB) = 0;
|
||||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS0) = 0;
|
MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS0) = 0;
|
||||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS1) = 0;
|
MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS1) = 0;
|
||||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS2) = 0x3000000;
|
MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS2) = (BIT(CSR_GPUSRD) | BIT(CSW_GPUSWR));
|
||||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS3) = 0;
|
MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS3) = 0;
|
||||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS4) = 0x300;
|
MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS4) = (BIT(CSR_GPUSRD2) | BIT(CSW_GPUSWR2));
|
||||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS0) = 0;
|
MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS0) = 0;
|
||||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS1) = 0;
|
MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS1) = 0;
|
||||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS2) = 0;
|
MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS2) = 0;
|
||||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS3) = 0;
|
MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS3) = 0;
|
||||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS4) = 0;
|
MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS4) = 0;
|
||||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CFG0) = 0x4401E7E;
|
MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CFG0) = 0x4401E7E;
|
||||||
|
|
||||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT4_BOM) = 0;
|
MAKE_MC_REG(MC_SECURITY_CARVEOUT4_BOM) = 0;
|
||||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT4_BOM_HI) = 0;
|
MAKE_MC_REG(MC_SECURITY_CARVEOUT4_BOM_HI) = 0;
|
||||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT4_SIZE_128KB) = 0;
|
MAKE_MC_REG(MC_SECURITY_CARVEOUT4_SIZE_128KB) = 0;
|
||||||
|
@ -86,6 +89,7 @@ void mc_config_carveout()
|
||||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS3) = 0;
|
MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS3) = 0;
|
||||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS4) = 0;
|
MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS4) = 0;
|
||||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CFG0) = 0x8F;
|
MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CFG0) = 0x8F;
|
||||||
|
|
||||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT5_BOM) = 0;
|
MAKE_MC_REG(MC_SECURITY_CARVEOUT5_BOM) = 0;
|
||||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT5_BOM_HI) = 0;
|
MAKE_MC_REG(MC_SECURITY_CARVEOUT5_BOM_HI) = 0;
|
||||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT5_SIZE_128KB) = 0;
|
MAKE_MC_REG(MC_SECURITY_CARVEOUT5_SIZE_128KB) = 0;
|
||||||
|
@ -109,9 +113,9 @@ void mc_config_carveout_finalize()
|
||||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT2_SIZE_128KB) = 2;
|
MAKE_MC_REG(MC_SECURITY_CARVEOUT2_SIZE_128KB) = 2;
|
||||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS0) = 0;
|
MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS0) = 0;
|
||||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS1) = 0;
|
MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS1) = 0;
|
||||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS2) = 0x3000000;
|
MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS2) = (BIT(CSR_GPUSRD) | BIT(CSW_GPUSWR));
|
||||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS3) = 0;
|
MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS3) = 0;
|
||||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS4) = 0x300;
|
MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS4) = (BIT(CSR_GPUSRD2) | BIT(CSW_GPUSWR2));
|
||||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS0) = 0;
|
MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS0) = 0;
|
||||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS1) = 0;
|
MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS1) = 0;
|
||||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS2) = 0;
|
MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS2) = 0;
|
||||||
|
|
|
@ -29,6 +29,21 @@
|
||||||
#define MC_INTMASK 0x4
|
#define MC_INTMASK 0x4
|
||||||
#define MC_ERR_STATUS 0x8
|
#define MC_ERR_STATUS 0x8
|
||||||
#define MC_ERR_ADR 0xc
|
#define MC_ERR_ADR 0xc
|
||||||
|
#define MC_SMMU_CONFIG 0x10
|
||||||
|
#define MC_SMMU_TLB_CONFIG 0x14
|
||||||
|
#define MC_SMMU_PTC_CONFIG 0x18
|
||||||
|
#define MC_SMMU_PTB_ASID 0x1c
|
||||||
|
#define MC_SMMU_PTB_DATA 0x20
|
||||||
|
#define MC_SMMU_TLB_FLUSH 0x30
|
||||||
|
#define MC_SMMU_PTC_FLUSH 0x34
|
||||||
|
#define MC_SMMU_AFI_ASID 0x238
|
||||||
|
#define MC_SMMU_AVPC_ASID 0x23c
|
||||||
|
#define MC_SMMU_PPCS1_ASID 0x298
|
||||||
|
#define MC_SMMU_TRANSLATION_ENABLE_0 0x228
|
||||||
|
#define MC_SMMU_TRANSLATION_ENABLE_1 0x22c
|
||||||
|
#define MC_SMMU_TRANSLATION_ENABLE_2 0x230
|
||||||
|
#define MC_SMMU_TRANSLATION_ENABLE_3 0x234
|
||||||
|
#define MC_SMMU_TRANSLATION_ENABLE_4 0xb98
|
||||||
#define MC_PCFIFO_CLIENT_CONFIG0 0xdd0
|
#define MC_PCFIFO_CLIENT_CONFIG0 0xdd0
|
||||||
#define MC_PCFIFO_CLIENT_CONFIG1 0xdd4
|
#define MC_PCFIFO_CLIENT_CONFIG1 0xdd4
|
||||||
#define MC_PCFIFO_CLIENT_CONFIG2 0xdd8
|
#define MC_PCFIFO_CLIENT_CONFIG2 0xdd8
|
||||||
|
@ -474,6 +489,103 @@
|
||||||
#define MC_ERR_APB_ASID_UPDATE_STATUS 0x9d0
|
#define MC_ERR_APB_ASID_UPDATE_STATUS 0x9d0
|
||||||
#define MC_DA_CONFIG0 0x9dc
|
#define MC_DA_CONFIG0 0x9dc
|
||||||
|
|
||||||
|
/* Memory Controller clients */
|
||||||
|
#define CLIENT_ACCESS_NUM_CLIENTS 32
|
||||||
|
typedef enum {
|
||||||
|
/* _ACCESS0 */
|
||||||
|
CSR_PTCR = (0 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
|
||||||
|
CSR_DISPLAY0A = (1 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
|
||||||
|
CSR_DISPLAY0AB = (2 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
|
||||||
|
CSR_DISPLAY0B = (3 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
|
||||||
|
CSR_DISPLAY0BB = (4 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
|
||||||
|
CSR_DISPLAY0C = (5 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
|
||||||
|
CSR_DISPLAY0CB = (6 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
|
||||||
|
CSR_AFIR = (14 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
|
||||||
|
CSR_AVPCARM7R = (15 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
|
||||||
|
CSR_DISPLAYHC = (16 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
|
||||||
|
CSR_DISPLAYHCB = (17 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
|
||||||
|
CSR_HDAR = (21 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
|
||||||
|
CSR_HOST1XDMAR = (22 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
|
||||||
|
CSR_HOST1XR = (23 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
|
||||||
|
CSR_NVENCSRD = (28 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
|
||||||
|
CSR_PPCSAHBDMAR = (29 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
|
||||||
|
CSR_PPCSAHBSLVR = (30 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
|
||||||
|
CSR_SATAR = (31 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
|
||||||
|
|
||||||
|
/* _ACCESS1 */
|
||||||
|
CSR_VDEBSEVR = (34 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
|
||||||
|
CSR_VDEMBER = (35 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
|
||||||
|
CSR_VDEMCER = (36 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
|
||||||
|
CSR_VDETPER = (37 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
|
||||||
|
CSR_MPCORELPR = (38 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
|
||||||
|
CSR_MPCORER = (39 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
|
||||||
|
CSW_NVENCSWR = (43 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
|
||||||
|
CSW_AFIW = (49 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
|
||||||
|
CSW_AVPCARM7W = (50 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
|
||||||
|
CSW_HDAW = (53 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
|
||||||
|
CSW_HOST1XW = (54 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
|
||||||
|
CSW_MPCORELPW = (56 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
|
||||||
|
CSW_MPCOREW = (57 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
|
||||||
|
CSW_PPCSAHBDMAW = (59 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
|
||||||
|
CSW_PPCSAHBSLVW = (60 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
|
||||||
|
CSW_SATAW = (61 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
|
||||||
|
CSW_VDEBSEVW = (62 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
|
||||||
|
CSW_VDEDBGW = (63 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
|
||||||
|
|
||||||
|
/* _ACCESS2 */
|
||||||
|
CSW_VDEMBEW = (64 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||||
|
CSW_VDETPMW = (65 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||||
|
CSR_ISPRA = (68 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||||
|
CSW_ISPWA = (70 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||||
|
CSW_ISPWB = (71 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||||
|
CSR_XUSB_HOSTR = (74 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||||
|
CSW_XUSB_HOSTW = (75 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||||
|
CSR_XUSB_DEVR = (76 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||||
|
CSW_XUSB_DEVW = (77 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||||
|
CSR_ISPRAB = (78 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||||
|
CSW_ISPWAB = (80 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||||
|
CSW_ISPWBB = (81 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||||
|
CSR_TSECSRD = (84 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||||
|
CSW_TSECSWR = (85 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||||
|
CSR_A9AVPSCR = (86 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||||
|
CSW_A9AVPSCW = (87 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||||
|
CSR_GPUSRD = (88 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||||
|
CSW_GPUSWR = (89 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||||
|
CSR_DISPLAYT = (90 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||||
|
|
||||||
|
/* _ACCESS3 */
|
||||||
|
CSR_SDMMCRA = (96 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
|
||||||
|
CSR_SDMMCRAA = (97 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
|
||||||
|
CSR_SDMMCR = (98 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
|
||||||
|
CSR_SDMMCRAB = (99 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
|
||||||
|
CSW_SDMMCWA = (100 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
|
||||||
|
CSW_SDMMCWAA = (101 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
|
||||||
|
CSW_SDMMCW = (102 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
|
||||||
|
CSW_SDMMCWAB = (103 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
|
||||||
|
CSR_VICSRD = (108 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
|
||||||
|
CSW_VICSWR = (109 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
|
||||||
|
CSW_VIW = (114 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
|
||||||
|
CSR_DISPLAYD = (115 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
|
||||||
|
CSR_NVDECSRD = (120 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
|
||||||
|
CSW_NVDECSWR = (121 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
|
||||||
|
CSR_APER = (122 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
|
||||||
|
CSW_APEW = (123 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
|
||||||
|
CSR_NVJPGSRD = (126 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
|
||||||
|
CSW_NVJPGSWR = (127 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
|
||||||
|
|
||||||
|
/* _ACCESS4 */
|
||||||
|
CSR_SESRD = (128 - (CLIENT_ACCESS_NUM_CLIENTS * 4)),
|
||||||
|
CSW_SESWR = (129 - (CLIENT_ACCESS_NUM_CLIENTS * 4)),
|
||||||
|
CSR_AXIAPR = (130 - (CLIENT_ACCESS_NUM_CLIENTS * 4)),
|
||||||
|
CSW_AXIAPW = (131 - (CLIENT_ACCESS_NUM_CLIENTS * 4)),
|
||||||
|
CSR_ETRR = (132 - (CLIENT_ACCESS_NUM_CLIENTS * 4)),
|
||||||
|
CSW_ETRW = (133 - (CLIENT_ACCESS_NUM_CLIENTS * 4)),
|
||||||
|
CSR_TSECSRDB = (134 - (CLIENT_ACCESS_NUM_CLIENTS * 4)),
|
||||||
|
CSW_TSECSWRB = (135 - (CLIENT_ACCESS_NUM_CLIENTS * 4)),
|
||||||
|
CSR_GPUSRD2 = (136 - (CLIENT_ACCESS_NUM_CLIENTS * 4)),
|
||||||
|
CSW_GPUSWR2 = (137 - (CLIENT_ACCESS_NUM_CLIENTS * 4))
|
||||||
|
} McClient;
|
||||||
|
|
||||||
void mc_config_tsec_carveout(uint32_t bom, uint32_t size1mb, bool lock);
|
void mc_config_tsec_carveout(uint32_t bom, uint32_t size1mb, bool lock);
|
||||||
void mc_config_carveout();
|
void mc_config_carveout();
|
||||||
void mc_config_carveout_finalize();
|
void mc_config_carveout_finalize();
|
||||||
|
|
|
@ -21,11 +21,15 @@
|
||||||
|
|
||||||
#define TIMERS_BASE 0x60005000
|
#define TIMERS_BASE 0x60005000
|
||||||
#define MAKE_TIMERS_REG(n) MAKE_REG32(TIMERS_BASE + n)
|
#define MAKE_TIMERS_REG(n) MAKE_REG32(TIMERS_BASE + n)
|
||||||
|
|
||||||
#define TIMERUS_CNTR_1US_0 MAKE_TIMERS_REG(0x10)
|
#define TIMERUS_CNTR_1US_0 MAKE_TIMERS_REG(0x10)
|
||||||
#define TIMERUS_USEC_CFG_0 MAKE_TIMERS_REG(0x14)
|
#define TIMERUS_USEC_CFG_0 MAKE_TIMERS_REG(0x14)
|
||||||
|
#define SHARED_INTR_STATUS_0 MAKE_TIMERS_REG(0x1A0)
|
||||||
|
#define SHARED_TIMER_SECURE_CFG_0 MAKE_TIMERS_REG(0x1A4)
|
||||||
|
|
||||||
#define RTC_BASE 0x7000E000
|
#define RTC_BASE 0x7000E000
|
||||||
#define MAKE_RTC_REG(n) MAKE_REG32(RTC_BASE + n)
|
#define MAKE_RTC_REG(n) MAKE_REG32(RTC_BASE + n)
|
||||||
|
|
||||||
#define RTC_SECONDS MAKE_RTC_REG(0x08)
|
#define RTC_SECONDS MAKE_RTC_REG(0x08)
|
||||||
#define RTC_SHADOW_SECONDS MAKE_RTC_REG(0x0C)
|
#define RTC_SHADOW_SECONDS MAKE_RTC_REG(0x0C)
|
||||||
#define RTC_MILLI_SECONDS MAKE_RTC_REG(0x10)
|
#define RTC_MILLI_SECONDS MAKE_RTC_REG(0x10)
|
||||||
|
@ -39,7 +43,7 @@ typedef struct {
|
||||||
|
|
||||||
#define GET_WDT(n) ((volatile watchdog_timers_t *)(TIMERS_BASE + 0x100 + 0x20 * n))
|
#define GET_WDT(n) ((volatile watchdog_timers_t *)(TIMERS_BASE + 0x100 + 0x20 * n))
|
||||||
#define WDT_REBOOT_PATTERN 0xC45A
|
#define WDT_REBOOT_PATTERN 0xC45A
|
||||||
#define GET_WDT_REBOOT_CFG_REG(n) MAKE_TIMERS_REG(0x60 + 0x8 * n)
|
#define GET_WDT_REBOOT_CFG_REG(n) MAKE_REG32(TIMERS_BASE + 0x60 + 0x8 * n)
|
||||||
|
|
||||||
void wait(uint32_t microseconds);
|
void wait(uint32_t microseconds);
|
||||||
|
|
||||||
|
|
|
@ -31,6 +31,7 @@ void mc_config_tsec_carveout(uint32_t bom, uint32_t size1mb, bool lock)
|
||||||
void mc_config_carveout()
|
void mc_config_carveout()
|
||||||
{
|
{
|
||||||
*(volatile uint32_t *)0x8005FFFC = 0xC0EDBBCC;
|
*(volatile uint32_t *)0x8005FFFC = 0xC0EDBBCC;
|
||||||
|
|
||||||
MAKE_MC_REG(MC_VIDEO_PROTECT_GPU_OVERRIDE_0) = 1;
|
MAKE_MC_REG(MC_VIDEO_PROTECT_GPU_OVERRIDE_0) = 1;
|
||||||
MAKE_MC_REG(MC_VIDEO_PROTECT_GPU_OVERRIDE_1) = 0;
|
MAKE_MC_REG(MC_VIDEO_PROTECT_GPU_OVERRIDE_1) = 0;
|
||||||
MAKE_MC_REG(MC_VIDEO_PROTECT_BOM) = 0;
|
MAKE_MC_REG(MC_VIDEO_PROTECT_BOM) = 0;
|
||||||
|
@ -43,6 +44,7 @@ void mc_config_carveout()
|
||||||
MAKE_MC_REG(MC_MTS_CARVEOUT_SIZE_MB) = 0;
|
MAKE_MC_REG(MC_MTS_CARVEOUT_SIZE_MB) = 0;
|
||||||
MAKE_MC_REG(MC_MTS_CARVEOUT_ADR_HI) = 0;
|
MAKE_MC_REG(MC_MTS_CARVEOUT_ADR_HI) = 0;
|
||||||
MAKE_MC_REG(MC_MTS_CARVEOUT_REG_CTRL) = 1;
|
MAKE_MC_REG(MC_MTS_CARVEOUT_REG_CTRL) = 1;
|
||||||
|
|
||||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT1_BOM) = 0;
|
MAKE_MC_REG(MC_SECURITY_CARVEOUT1_BOM) = 0;
|
||||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT1_BOM_HI) = 0;
|
MAKE_MC_REG(MC_SECURITY_CARVEOUT1_BOM_HI) = 0;
|
||||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT1_SIZE_128KB) = 0;
|
MAKE_MC_REG(MC_SECURITY_CARVEOUT1_SIZE_128KB) = 0;
|
||||||
|
@ -63,15 +65,16 @@ void mc_config_carveout()
|
||||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT3_SIZE_128KB) = 0;
|
MAKE_MC_REG(MC_SECURITY_CARVEOUT3_SIZE_128KB) = 0;
|
||||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS0) = 0;
|
MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS0) = 0;
|
||||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS1) = 0;
|
MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS1) = 0;
|
||||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS2) = 0x3000000;
|
MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS2) = (BIT(CSR_GPUSRD) | BIT(CSW_GPUSWR));
|
||||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS3) = 0;
|
MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS3) = 0;
|
||||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS4) = 0x300;
|
MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS4) = (BIT(CSR_GPUSRD2) | BIT(CSW_GPUSWR2));
|
||||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS0) = 0;
|
MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS0) = 0;
|
||||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS1) = 0;
|
MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS1) = 0;
|
||||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS2) = 0;
|
MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS2) = 0;
|
||||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS3) = 0;
|
MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS3) = 0;
|
||||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS4) = 0;
|
MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS4) = 0;
|
||||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CFG0) = 0x4401E7E;
|
MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CFG0) = 0x4401E7E;
|
||||||
|
|
||||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT4_BOM) = 0;
|
MAKE_MC_REG(MC_SECURITY_CARVEOUT4_BOM) = 0;
|
||||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT4_BOM_HI) = 0;
|
MAKE_MC_REG(MC_SECURITY_CARVEOUT4_BOM_HI) = 0;
|
||||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT4_SIZE_128KB) = 0;
|
MAKE_MC_REG(MC_SECURITY_CARVEOUT4_SIZE_128KB) = 0;
|
||||||
|
@ -86,6 +89,7 @@ void mc_config_carveout()
|
||||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS3) = 0;
|
MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS3) = 0;
|
||||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS4) = 0;
|
MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS4) = 0;
|
||||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CFG0) = 0x8F;
|
MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CFG0) = 0x8F;
|
||||||
|
|
||||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT5_BOM) = 0;
|
MAKE_MC_REG(MC_SECURITY_CARVEOUT5_BOM) = 0;
|
||||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT5_BOM_HI) = 0;
|
MAKE_MC_REG(MC_SECURITY_CARVEOUT5_BOM_HI) = 0;
|
||||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT5_SIZE_128KB) = 0;
|
MAKE_MC_REG(MC_SECURITY_CARVEOUT5_SIZE_128KB) = 0;
|
||||||
|
@ -109,9 +113,9 @@ void mc_config_carveout_finalize()
|
||||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT2_SIZE_128KB) = 2;
|
MAKE_MC_REG(MC_SECURITY_CARVEOUT2_SIZE_128KB) = 2;
|
||||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS0) = 0;
|
MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS0) = 0;
|
||||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS1) = 0;
|
MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS1) = 0;
|
||||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS2) = 0x3000000;
|
MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS2) = (BIT(CSR_GPUSRD) | BIT(CSW_GPUSWR));
|
||||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS3) = 0;
|
MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS3) = 0;
|
||||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS4) = 0x300;
|
MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS4) = (BIT(CSR_GPUSRD2) | BIT(CSW_GPUSWR2));
|
||||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS0) = 0;
|
MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS0) = 0;
|
||||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS1) = 0;
|
MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS1) = 0;
|
||||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS2) = 0;
|
MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS2) = 0;
|
||||||
|
|
|
@ -29,6 +29,21 @@
|
||||||
#define MC_INTMASK 0x4
|
#define MC_INTMASK 0x4
|
||||||
#define MC_ERR_STATUS 0x8
|
#define MC_ERR_STATUS 0x8
|
||||||
#define MC_ERR_ADR 0xc
|
#define MC_ERR_ADR 0xc
|
||||||
|
#define MC_SMMU_CONFIG 0x10
|
||||||
|
#define MC_SMMU_TLB_CONFIG 0x14
|
||||||
|
#define MC_SMMU_PTC_CONFIG 0x18
|
||||||
|
#define MC_SMMU_PTB_ASID 0x1c
|
||||||
|
#define MC_SMMU_PTB_DATA 0x20
|
||||||
|
#define MC_SMMU_TLB_FLUSH 0x30
|
||||||
|
#define MC_SMMU_PTC_FLUSH 0x34
|
||||||
|
#define MC_SMMU_AFI_ASID 0x238
|
||||||
|
#define MC_SMMU_AVPC_ASID 0x23c
|
||||||
|
#define MC_SMMU_PPCS1_ASID 0x298
|
||||||
|
#define MC_SMMU_TRANSLATION_ENABLE_0 0x228
|
||||||
|
#define MC_SMMU_TRANSLATION_ENABLE_1 0x22c
|
||||||
|
#define MC_SMMU_TRANSLATION_ENABLE_2 0x230
|
||||||
|
#define MC_SMMU_TRANSLATION_ENABLE_3 0x234
|
||||||
|
#define MC_SMMU_TRANSLATION_ENABLE_4 0xb98
|
||||||
#define MC_PCFIFO_CLIENT_CONFIG0 0xdd0
|
#define MC_PCFIFO_CLIENT_CONFIG0 0xdd0
|
||||||
#define MC_PCFIFO_CLIENT_CONFIG1 0xdd4
|
#define MC_PCFIFO_CLIENT_CONFIG1 0xdd4
|
||||||
#define MC_PCFIFO_CLIENT_CONFIG2 0xdd8
|
#define MC_PCFIFO_CLIENT_CONFIG2 0xdd8
|
||||||
|
@ -474,6 +489,103 @@
|
||||||
#define MC_ERR_APB_ASID_UPDATE_STATUS 0x9d0
|
#define MC_ERR_APB_ASID_UPDATE_STATUS 0x9d0
|
||||||
#define MC_DA_CONFIG0 0x9dc
|
#define MC_DA_CONFIG0 0x9dc
|
||||||
|
|
||||||
|
/* Memory Controller clients */
|
||||||
|
#define CLIENT_ACCESS_NUM_CLIENTS 32
|
||||||
|
typedef enum {
|
||||||
|
/* _ACCESS0 */
|
||||||
|
CSR_PTCR = (0 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
|
||||||
|
CSR_DISPLAY0A = (1 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
|
||||||
|
CSR_DISPLAY0AB = (2 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
|
||||||
|
CSR_DISPLAY0B = (3 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
|
||||||
|
CSR_DISPLAY0BB = (4 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
|
||||||
|
CSR_DISPLAY0C = (5 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
|
||||||
|
CSR_DISPLAY0CB = (6 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
|
||||||
|
CSR_AFIR = (14 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
|
||||||
|
CSR_AVPCARM7R = (15 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
|
||||||
|
CSR_DISPLAYHC = (16 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
|
||||||
|
CSR_DISPLAYHCB = (17 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
|
||||||
|
CSR_HDAR = (21 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
|
||||||
|
CSR_HOST1XDMAR = (22 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
|
||||||
|
CSR_HOST1XR = (23 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
|
||||||
|
CSR_NVENCSRD = (28 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
|
||||||
|
CSR_PPCSAHBDMAR = (29 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
|
||||||
|
CSR_PPCSAHBSLVR = (30 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
|
||||||
|
CSR_SATAR = (31 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
|
||||||
|
|
||||||
|
/* _ACCESS1 */
|
||||||
|
CSR_VDEBSEVR = (34 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
|
||||||
|
CSR_VDEMBER = (35 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
|
||||||
|
CSR_VDEMCER = (36 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
|
||||||
|
CSR_VDETPER = (37 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
|
||||||
|
CSR_MPCORELPR = (38 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
|
||||||
|
CSR_MPCORER = (39 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
|
||||||
|
CSW_NVENCSWR = (43 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
|
||||||
|
CSW_AFIW = (49 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
|
||||||
|
CSW_AVPCARM7W = (50 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
|
||||||
|
CSW_HDAW = (53 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
|
||||||
|
CSW_HOST1XW = (54 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
|
||||||
|
CSW_MPCORELPW = (56 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
|
||||||
|
CSW_MPCOREW = (57 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
|
||||||
|
CSW_PPCSAHBDMAW = (59 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
|
||||||
|
CSW_PPCSAHBSLVW = (60 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
|
||||||
|
CSW_SATAW = (61 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
|
||||||
|
CSW_VDEBSEVW = (62 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
|
||||||
|
CSW_VDEDBGW = (63 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
|
||||||
|
|
||||||
|
/* _ACCESS2 */
|
||||||
|
CSW_VDEMBEW = (64 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||||
|
CSW_VDETPMW = (65 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||||
|
CSR_ISPRA = (68 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||||
|
CSW_ISPWA = (70 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||||
|
CSW_ISPWB = (71 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||||
|
CSR_XUSB_HOSTR = (74 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||||
|
CSW_XUSB_HOSTW = (75 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||||
|
CSR_XUSB_DEVR = (76 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||||
|
CSW_XUSB_DEVW = (77 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||||
|
CSR_ISPRAB = (78 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||||
|
CSW_ISPWAB = (80 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||||
|
CSW_ISPWBB = (81 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||||
|
CSR_TSECSRD = (84 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||||
|
CSW_TSECSWR = (85 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||||
|
CSR_A9AVPSCR = (86 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||||
|
CSW_A9AVPSCW = (87 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||||
|
CSR_GPUSRD = (88 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||||
|
CSW_GPUSWR = (89 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||||
|
CSR_DISPLAYT = (90 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||||
|
|
||||||
|
/* _ACCESS3 */
|
||||||
|
CSR_SDMMCRA = (96 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
|
||||||
|
CSR_SDMMCRAA = (97 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
|
||||||
|
CSR_SDMMCR = (98 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
|
||||||
|
CSR_SDMMCRAB = (99 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
|
||||||
|
CSW_SDMMCWA = (100 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
|
||||||
|
CSW_SDMMCWAA = (101 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
|
||||||
|
CSW_SDMMCW = (102 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
|
||||||
|
CSW_SDMMCWAB = (103 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
|
||||||
|
CSR_VICSRD = (108 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
|
||||||
|
CSW_VICSWR = (109 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
|
||||||
|
CSW_VIW = (114 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
|
||||||
|
CSR_DISPLAYD = (115 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
|
||||||
|
CSR_NVDECSRD = (120 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
|
||||||
|
CSW_NVDECSWR = (121 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
|
||||||
|
CSR_APER = (122 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
|
||||||
|
CSW_APEW = (123 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
|
||||||
|
CSR_NVJPGSRD = (126 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
|
||||||
|
CSW_NVJPGSWR = (127 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
|
||||||
|
|
||||||
|
/* _ACCESS4 */
|
||||||
|
CSR_SESRD = (128 - (CLIENT_ACCESS_NUM_CLIENTS * 4)),
|
||||||
|
CSW_SESWR = (129 - (CLIENT_ACCESS_NUM_CLIENTS * 4)),
|
||||||
|
CSR_AXIAPR = (130 - (CLIENT_ACCESS_NUM_CLIENTS * 4)),
|
||||||
|
CSW_AXIAPW = (131 - (CLIENT_ACCESS_NUM_CLIENTS * 4)),
|
||||||
|
CSR_ETRR = (132 - (CLIENT_ACCESS_NUM_CLIENTS * 4)),
|
||||||
|
CSW_ETRW = (133 - (CLIENT_ACCESS_NUM_CLIENTS * 4)),
|
||||||
|
CSR_TSECSRDB = (134 - (CLIENT_ACCESS_NUM_CLIENTS * 4)),
|
||||||
|
CSW_TSECSWRB = (135 - (CLIENT_ACCESS_NUM_CLIENTS * 4)),
|
||||||
|
CSR_GPUSRD2 = (136 - (CLIENT_ACCESS_NUM_CLIENTS * 4)),
|
||||||
|
CSW_GPUSWR2 = (137 - (CLIENT_ACCESS_NUM_CLIENTS * 4))
|
||||||
|
} McClient;
|
||||||
|
|
||||||
void mc_config_tsec_carveout(uint32_t bom, uint32_t size1mb, bool lock);
|
void mc_config_tsec_carveout(uint32_t bom, uint32_t size1mb, bool lock);
|
||||||
void mc_config_carveout();
|
void mc_config_carveout();
|
||||||
void mc_config_carveout_finalize();
|
void mc_config_carveout_finalize();
|
||||||
|
|
|
@ -41,7 +41,8 @@ void nxboot_finish(uint32_t boot_memaddr) {
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Finalize the GPU UCODE carveout. */
|
/* Finalize the GPU UCODE carveout. */
|
||||||
mc_config_carveout_finalize();
|
/* NOTE: [4.0.0+] This is now done in the Secure Monitor. */
|
||||||
|
/* mc_config_carveout_finalize(); */
|
||||||
|
|
||||||
/* Lock AES keyslots. */
|
/* Lock AES keyslots. */
|
||||||
for (uint32_t i = 0; i < 16; i++)
|
for (uint32_t i = 0; i < 16; i++)
|
||||||
|
|
|
@ -21,11 +21,15 @@
|
||||||
|
|
||||||
#define TIMERS_BASE 0x60005000
|
#define TIMERS_BASE 0x60005000
|
||||||
#define MAKE_TIMERS_REG(n) MAKE_REG32(TIMERS_BASE + n)
|
#define MAKE_TIMERS_REG(n) MAKE_REG32(TIMERS_BASE + n)
|
||||||
|
|
||||||
#define TIMERUS_CNTR_1US_0 MAKE_TIMERS_REG(0x10)
|
#define TIMERUS_CNTR_1US_0 MAKE_TIMERS_REG(0x10)
|
||||||
#define TIMERUS_USEC_CFG_0 MAKE_TIMERS_REG(0x14)
|
#define TIMERUS_USEC_CFG_0 MAKE_TIMERS_REG(0x14)
|
||||||
|
#define SHARED_INTR_STATUS_0 MAKE_TIMERS_REG(0x1A0)
|
||||||
|
#define SHARED_TIMER_SECURE_CFG_0 MAKE_TIMERS_REG(0x1A4)
|
||||||
|
|
||||||
#define RTC_BASE 0x7000E000
|
#define RTC_BASE 0x7000E000
|
||||||
#define MAKE_RTC_REG(n) MAKE_REG32(RTC_BASE + n)
|
#define MAKE_RTC_REG(n) MAKE_REG32(RTC_BASE + n)
|
||||||
|
|
||||||
#define RTC_SECONDS MAKE_RTC_REG(0x08)
|
#define RTC_SECONDS MAKE_RTC_REG(0x08)
|
||||||
#define RTC_SHADOW_SECONDS MAKE_RTC_REG(0x0C)
|
#define RTC_SHADOW_SECONDS MAKE_RTC_REG(0x0C)
|
||||||
#define RTC_MILLI_SECONDS MAKE_RTC_REG(0x10)
|
#define RTC_MILLI_SECONDS MAKE_RTC_REG(0x10)
|
||||||
|
@ -39,7 +43,7 @@ typedef struct {
|
||||||
|
|
||||||
#define GET_WDT(n) ((volatile watchdog_timers_t *)(TIMERS_BASE + 0x100 + 0x20 * n))
|
#define GET_WDT(n) ((volatile watchdog_timers_t *)(TIMERS_BASE + 0x100 + 0x20 * n))
|
||||||
#define WDT_REBOOT_PATTERN 0xC45A
|
#define WDT_REBOOT_PATTERN 0xC45A
|
||||||
#define GET_WDT_REBOOT_CFG_REG(n) MAKE_TIMERS_REG(0x60 + 0x8 * n)
|
#define GET_WDT_REBOOT_CFG_REG(n) MAKE_REG32(TIMERS_BASE + 0x60 + 0x8 * n)
|
||||||
|
|
||||||
void wait(uint32_t microseconds);
|
void wait(uint32_t microseconds);
|
||||||
|
|
||||||
|
|
Loading…
Reference in a new issue