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thermosphere: don't trap memory register writes/don't migrate sw breakpoints

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Makes no sense on a system with ASLR
This commit is contained in:
TuxSH 2020-01-06 21:57:53 +00:00
parent 28552da099
commit d42d9e60b9
3 changed files with 0 additions and 22 deletions
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1
thermosphere/src/irq.c
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@ -181,7 +181,6 @@ void handleIrqException(ExceptionStackFrame *frame, bool isLowerEl, bool isA32)
// Deactivate the interrupt // Deactivate the interrupt
gicc->dir = iar; gicc->dir = iar;
} else { } else {
if (irqId == 30) g_irqManager.gic.gicd->ispendr[0x80/32] = 0xFFFFFFFF;
vgicEnqueuePhysicalIrq(irqId); vgicEnqueuePhysicalIrq(irqId);
} }

18
thermosphere/src/sysreg_traps.c
View file

@ -68,32 +68,14 @@ void doSystemRegisterWrite(ExceptionStackFrame *frame, u32 iss, u32 reg)
val = readFrameRegisterZ(frame, reg); val = readFrameRegisterZ(frame, reg);
bool reevalSoftwareBreakpoints = false;
// Hooks go here: // Hooks go here:
switch (iss) { switch (iss) {
case ENCODE_SYSREG_ISS(TTBR0_EL1):
case ENCODE_SYSREG_ISS(TTBR1_EL1):
case ENCODE_SYSREG_ISS(TCR_EL1):
case ENCODE_SYSREG_ISS(SCTLR_EL1):
reevalSoftwareBreakpoints = true;
break;
default: default:
break; break;
} }
if (reevalSoftwareBreakpoints) {
revertAllSoftwareBreakpoints();
}
doSystemRegisterRwImpl(&val, iss); doSystemRegisterRwImpl(&val, iss);
if (reevalSoftwareBreakpoints) {
__dsb_sy();
__isb();
applyAllSoftwareBreakpoints();
}
skipFaultingInstruction(frame, 4); skipFaultingInstruction(frame, 4);
} }

3
thermosphere/src/traps.c
View file

@ -34,9 +34,6 @@ void enableTraps(void)
{ {
u64 hcr = GET_SYSREG(hcr_el2); u64 hcr = GET_SYSREG(hcr_el2);
// Trap memory-related sysreg writes (note: not supported by QEMU yet)
hcr |= HCR_TVM;
// Trap SMC instructions // Trap SMC instructions
hcr |= HCR_TSC; hcr |= HCR_TSC;