dmnt: explicitly reserve double-extended width opcodes

This commit is contained in:
Michael Scire 2019-05-27 18:10:49 -07:00
parent 766097d0b7
commit cfa050cc8f
2 changed files with 8 additions and 0 deletions

View file

@ -260,6 +260,9 @@ bool DmntCheatVm::DecodeNextOpcode(CheatVmOpcode *out) {
if (opcode.opcode >= CheatVmOpcodeType_ExtendedWidth) { if (opcode.opcode >= CheatVmOpcodeType_ExtendedWidth) {
opcode.opcode = (CheatVmOpcodeType)((((u32)opcode.opcode) << 4) | ((first_dword >> 24) & 0xF)); opcode.opcode = (CheatVmOpcodeType)((((u32)opcode.opcode) << 4) | ((first_dword >> 24) & 0xF));
} }
if (opcode.opcode >= CheatVmOpcodeType_DoubleExtendedWidth) {
opcode.opcode = (CheatVmOpcodeType)((((u32)opcode.opcode) << 4) | ((first_dword >> 20) & 0xF));
}
/* detect condition start. */ /* detect condition start. */
switch (opcode.opcode) { switch (opcode.opcode) {
@ -501,6 +504,7 @@ bool DmntCheatVm::DecodeNextOpcode(CheatVmOpcode *out) {
} }
break; break;
case CheatVmOpcodeType_ExtendedWidth: case CheatVmOpcodeType_ExtendedWidth:
case CheatVmOpcodeType_DoubleExtendedWidth:
default: default:
/* Unrecognized instruction cannot be decoded. */ /* Unrecognized instruction cannot be decoded. */
valid = false; valid = false;

View file

@ -45,6 +45,10 @@ enum CheatVmOpcodeType : u32 {
CheatVmOpcodeType_BeginRegisterConditionalBlock = 0xC0, CheatVmOpcodeType_BeginRegisterConditionalBlock = 0xC0,
CheatVmOpcodeType_SaveRestoreRegister = 0xC1, CheatVmOpcodeType_SaveRestoreRegister = 0xC1,
CheatVmOpcodeType_SaveRestoreRegisterMask = 0xC2, CheatVmOpcodeType_SaveRestoreRegisterMask = 0xC2,
/* This is a meta entry, and not a real opcode. */
/* This is to facilitate multi-nybble instruction decoding. */
CheatVmOpcodeType_DoubleExtendedWidth = 0xF0,
}; };
enum MemoryAccessType : u32 { enum MemoryAccessType : u32 {