diff --git a/fusee_cpp/program/source/fusee_main.cpp b/fusee_cpp/program/source/fusee_main.cpp index 8e7c6d595..dd0ce3c68 100644 --- a/fusee_cpp/program/source/fusee_main.cpp +++ b/fusee_cpp/program/source/fusee_main.cpp @@ -20,7 +20,7 @@ namespace ams::nxboot { void Main() { /* Perform secure hardware initialization. */ - SecureInitialize(); + SecureInitialize(true); /* TODO */ AMS_INFINITE_LOOP(); diff --git a/fusee_cpp/program/source/fusee_secure_initialize.cpp b/fusee_cpp/program/source/fusee_secure_initialize.cpp index 24d12d372..90f556467 100644 --- a/fusee_cpp/program/source/fusee_secure_initialize.cpp +++ b/fusee_cpp/program/source/fusee_secure_initialize.cpp @@ -161,11 +161,22 @@ namespace ams::nxboot { reg::ReadWrite(CLKRST + CLK_RST_CONTROLLER_CLK_SOURCE_NVENC, CLK_RST_REG_BITS_ENUM(CLK_SOURCE_NVENC_NVENC_CLK_SRC, PLLP_OUT0)); } + void InitializeClock() { + /* TODO */ + } + + void InitializePinmux(fuse::HardwareType hw_type) { + /* TODO */ + } + + + } - void SecureInitialize() { - /* Get SoC type. */ + void SecureInitialize(bool enable_log) { + /* Get SoC type/hardware type. */ const auto soc_type = fuse::GetSocType(); + const auto hw_type = fuse::GetHardwareType(); /* If Erista, perform bootrom logic (to compensate for RCM exploit) and MBIST workaround. */ if (soc_type == fuse::SocType_Erista) { @@ -179,7 +190,45 @@ namespace ams::nxboot { DoMbistWorkaround(); } - /* TODO */ + /* Setup initial clocks. */ + InitializeClock(); + + /* Setup initial pinmux. */ + InitializePinmux(hw_type); + + /* Initialize logging. */ + if (enable_log) { + clkrst::EnableUartAClock(); + } + + /* Enable various clocks. */ + clkrst::EnableCldvfsClock(); + clkrst::EnableI2c1Clock(); + clkrst::EnableI2c5Clock(); + clkrst::EnableTzramClock(); + + /* Initialize I2C5. */ + i2c::Initialize(i2c::Port_5); + + /* Configure pmic system setting. */ + pmic::SetSystemSetting(); + + /* Enable VDD core */ + pmic::EnableVddCore(); + + /* On hoag, enable Ldo8 */ + if (hw_type == fuse::HardwareType_Hoag) { + pmic::EnableLdo8(); + } + + /* Initialize I2C1. */ + i2c::Initialize(i2c::Port_1); + + /* Configure SCLK_BURST_POLICY. */ + reg::ReadWrite(CLKRST + CLK_RST_CONTROLLER_SCLK_BURST_POLICY, CLK_RST_REG_BITS_ENUM(SCLK_BURST_POLICY_SWAKEUP_FIQ_SOURCE, PLLP_OUT0), + CLK_RST_REG_BITS_ENUM(SCLK_BURST_POLICY_SWAKEUP_IRQ_SOURCE, PLLP_OUT0), + CLK_RST_REG_BITS_ENUM(SCLK_BURST_POLICY_SWAKEUP_RUN_SOURCE, PLLP_OUT0), + CLK_RST_REG_BITS_ENUM(SCLK_BURST_POLICY_SWAKEUP_IDLE_SOURCE, PLLP_OUT0)); } } diff --git a/fusee_cpp/program/source/fusee_secure_initialize.hpp b/fusee_cpp/program/source/fusee_secure_initialize.hpp index 0c3563b87..ecea343b8 100644 --- a/fusee_cpp/program/source/fusee_secure_initialize.hpp +++ b/fusee_cpp/program/source/fusee_secure_initialize.hpp @@ -18,6 +18,6 @@ namespace ams::nxboot { - void SecureInitialize(); + void SecureInitialize(bool enable_log); } \ No newline at end of file diff --git a/libraries/libexosphere/include/exosphere/clkrst.hpp b/libraries/libexosphere/include/exosphere/clkrst.hpp index 2935eb2c1..3299197a0 100644 --- a/libraries/libexosphere/include/exosphere/clkrst.hpp +++ b/libraries/libexosphere/include/exosphere/clkrst.hpp @@ -29,6 +29,8 @@ namespace ams::clkrst { void EnableI2c1Clock(); void EnableI2c5Clock(); + void EnableCldvfsClock(); + void EnableTzramClock(); void EnableHost1xClock(); void EnableTsecClock(); diff --git a/libraries/libexosphere/include/exosphere/pmic.hpp b/libraries/libexosphere/include/exosphere/pmic.hpp index ea85f60a0..2fc92ff70 100644 --- a/libraries/libexosphere/include/exosphere/pmic.hpp +++ b/libraries/libexosphere/include/exosphere/pmic.hpp @@ -36,4 +36,8 @@ namespace ams::pmic { bool IsAcOk(); bool IsPowerButtonPressed(); + void SetSystemSetting(); + void EnableVddCore(); + void EnableLdo8(); + } \ No newline at end of file diff --git a/libraries/libexosphere/source/clkrst/clkrst_api.cpp b/libraries/libexosphere/source/clkrst/clkrst_api.cpp index b0f7f7820..3227a3210 100644 --- a/libraries/libexosphere/source/clkrst/clkrst_api.cpp +++ b/libraries/libexosphere/source/clkrst/clkrst_api.cpp @@ -88,6 +88,9 @@ namespace ams::clkrst { DEFINE_CLOCK_PARAMETERS(TsecClock, U, TSEC, PLLP_OUT0, 2); DEFINE_CLOCK_PARAMETERS(Sor1Clock, X, SOR1, PLLP_OUT0, 2); + DEFINE_CLOCK_PARAMETERS_WITHOUT_CLKDIV(CldvfsClock, W, DVFS); + DEFINE_CLOCK_PARAMETERS_WITHOUT_CLKDIV(TzramClock, V, TZRAM); + DEFINE_CLOCK_PARAMETERS_WITHOUT_CLKDIV(SorSafeClock, Y, SOR_SAFE); DEFINE_CLOCK_PARAMETERS_WITHOUT_CLKDIV(Sor0Clock, X, SOR0); DEFINE_CLOCK_PARAMETERS_WITHOUT_CLKDIV(KfuseClock, H, KFUSE); @@ -126,6 +129,14 @@ namespace ams::clkrst { EnableClock(I2c5Clock); } + void EnableCldvfsClock() { + EnableClock(CldvfsClock); + } + + void EnableTzramClock() { + EnableClock(TzramClock); + } + void EnableHost1xClock() { EnableClock(Host1xClock); } diff --git a/libraries/libexosphere/source/pmic/pmic_api.cpp b/libraries/libexosphere/source/pmic/pmic_api.cpp index 76ee8c683..84c8fbf64 100644 --- a/libraries/libexosphere/source/pmic/pmic_api.cpp +++ b/libraries/libexosphere/source/pmic/pmic_api.cpp @@ -215,4 +215,15 @@ namespace ams::pmic { return (GetPmicOnOffStat() & (1 << 2)) != 0; } + void SetSystemSetting() { + /* TODO */ + } + void EnableVddCore() { + /* TODO */ + } + + void EnableLdo8() { + /* TODO */ + } + } diff --git a/libraries/libvapours/include/vapours/tegra/tegra_clkrst.hpp b/libraries/libvapours/include/vapours/tegra/tegra_clkrst.hpp index 8287db38f..7f5fc29d2 100644 --- a/libraries/libvapours/include/vapours/tegra/tegra_clkrst.hpp +++ b/libraries/libvapours/include/vapours/tegra/tegra_clkrst.hpp @@ -36,6 +36,7 @@ #define CLK_RST_CONTROLLER_RST_SOURCE (0x000) +#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY (0x028) #define CLK_RST_CONTROLLER_MISC_CLK_ENB (0x048) #define CLK_RST_CONTROLLER_OSC_CTRL (0x050) #define CLK_RST_CONTROLLER_PLLD_BASE (0x0D0) @@ -57,6 +58,11 @@ #define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD (0x3A4) #define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRE (0x554) +DEFINE_CLK_RST_REG_THREE_BIT_ENUM(SCLK_BURST_POLICY_SWAKEUP_IDLE_SOURCE, 0, CLKM, PLLC_OUT1, PLLC4_OUT3PLLP_OUT4, PLLP_OUT0, PLLP_OUT2, PLLC4_OUT1PLLC_OUT0, CLK_SCLKS, PLLC4_OUT2); +DEFINE_CLK_RST_REG_THREE_BIT_ENUM(SCLK_BURST_POLICY_SWAKEUP_RUN_SOURCE, 4, CLKM, PLLC_OUT1, PLLC4_OUT3PLLP_OUT4, PLLP_OUT0, PLLP_OUT2, PLLC4_OUT1PLLC_OUT0, CLK_SCLKS, PLLC4_OUT2); +DEFINE_CLK_RST_REG_THREE_BIT_ENUM(SCLK_BURST_POLICY_SWAKEUP_IRQ_SOURCE, 8, CLKM, PLLC_OUT1, PLLC4_OUT3PLLP_OUT4, PLLP_OUT0, PLLP_OUT2, PLLC4_OUT1PLLC_OUT0, CLK_SCLKS, PLLC4_OUT2); +DEFINE_CLK_RST_REG_THREE_BIT_ENUM(SCLK_BURST_POLICY_SWAKEUP_FIQ_SOURCE, 12, CLKM, PLLC_OUT1, PLLC4_OUT3PLLP_OUT4, PLLP_OUT0, PLLP_OUT2, PLLC4_OUT1PLLC_OUT0, CLK_SCLKS, PLLC4_OUT2); + DEFINE_CLK_RST_REG(MISC_CLK_ENB_CFG_ALL_VISIBLE, 28, 1); DEFINE_CLK_RST_REG_BIT_ENUM(OSC_CTRL_XOE, 0, DISABLE, ENABLE); @@ -209,6 +215,10 @@ DEFINE_CLK_RST_REG_BIT_ENUM(PLLC4_BASE_PLLC4_ENABLE, 30, DISABLE, ENABLE); #define CLK_RST_CONTROLLER_CLK_ENB_ACTMON_INDEX (0x17) +#define CLK_RST_CONTROLLER_CLK_ENB_DVFS_INDEX (0x1B) + +#define CLK_RST_CONTROLLER_CLK_ENB_TZRAM_INDEX (0x1E) + #define CLK_RST_CONTROLLER_CLK_ENB_HOST1X_INDEX (0x1C) #define CLK_RST_CONTROLLER_CLK_ENB_TSEC_INDEX (0x13) #define CLK_RST_CONTROLLER_CLK_ENB_SOR0_INDEX (0x16)