mirror of
https://github.com/Atmosphere-NX/Atmosphere
synced 2024-12-22 20:31:14 +00:00
fusee_cpp: begin mariko mtc work
This commit is contained in:
Michael Scire
SciresM
parent
598edc0a46
commit
c4fee796ea
5 changed files with 292 additions and 14 deletions
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@ -18,12 +18,16 @@
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namespace ams::nxboot {
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void DoMemoryTrainingErista(int index, void *mtc_tables_buffer);
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void DoMemoryTrainingMariko(int index, void *mtc_tables_buffer);
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void DoMemoryTrainingMariko(bool *out_did_training, int index, void *mtc_tables_buffer);
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void RestoreMemoryClockRateMariko(void *mtc_tables_buffer);
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namespace {
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alignas(4) constinit u8 g_mtc_tables_buffer[0x26C0];
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constinit bool g_did_training_mariko = false;
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constexpr const u8 MemoryTrainingTableIndex_Invalid = std::numeric_limits<u8>::max();
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constexpr const u8 MemoryTrainingTableIndices[] = {
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@ -74,7 +78,14 @@ namespace ams::nxboot {
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if (fuse::GetSocType() == fuse::SocType_Erista) {
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DoMemoryTrainingErista(index, g_mtc_tables_buffer);
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} else {
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DoMemoryTrainingMariko(index, g_mtc_tables_buffer);
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DoMemoryTrainingMariko(std::addressof(g_did_training_mariko), index, g_mtc_tables_buffer);
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}
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}
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void RestoreMemoryClockRate() {
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/* NOTE: This resolves an off-by-one issue in PCV's detection of memory clock rate on Mariko. */
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if (fuse::GetSocType() == fuse::SocType_Mariko && g_did_training_mariko) {
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RestoreMemoryClockRateMariko(g_mtc_tables_buffer);
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}
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}
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@ -20,4 +20,6 @@ namespace ams::nxboot {
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void DoMemoryTraining();
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void RestoreMemoryClockRate();
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}
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@ -23,8 +23,53 @@ namespace ams::nxboot {
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namespace {
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constexpr inline const uintptr_t CLKRST = secmon::MemoryRegionPhysicalDeviceClkRst.GetAddress();
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constexpr inline const uintptr_t MC = MC_BASE;
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constexpr inline const uintptr_t EMC = EMC_BASE;
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constexpr inline const uintptr_t EMC0 = EMC0_BASE;
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constexpr inline const uintptr_t EMC1 = EMC1_BASE;
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static constinit bool g_next_pll = false;
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static constinit bool g_did_first_training = false;
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static constinit bool g_fsp_for_next_freq = false;
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#include "fusee_mtc_tables_mariko.inc"
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#define DECLARE_OFFSET_HANDLER(BASE, REG, NAME) REG,
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#define DECLARE_REGISTER_HANDLER(BASE, REG, NAME) BASE + REG,
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constexpr inline const u16 BurstRegistersOffsets[] = {
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FOREACH_BURST_REG(DECLARE_OFFSET_HANDLER)
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};
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constexpr inline const u32 TrimRegisters[] = {
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FOREACH_TRIM_REG(DECLARE_REGISTER_HANDLER)
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};
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constexpr inline const u32 BurstMcRegisters[] = {
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FOREACH_BURST_MC_REG(DECLARE_REGISTER_HANDLER)
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};
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constexpr inline const u32 LaScaleRegisters[] = {
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FOREACH_LA_SCALE_REG(DECLARE_REGISTER_HANDLER)
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};
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constexpr inline const u32 PerChannelTrimRegisters[] = {
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FOREACH_PER_CHANNEL_TRIM_REG(DECLARE_REGISTER_HANDLER)
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};
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constexpr inline const u32 PerChannelBurstRegisters[] = {
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FOREACH_PER_CHANNEL_BURST_REG(DECLARE_REGISTER_HANDLER)
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};
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constexpr inline const u32 PerChannelVrefRegisters[] = {
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FOREACH_PER_CHANNEL_VREF_REG(DECLARE_REGISTER_HANDLER)
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};
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constexpr inline const u32 PerChannelTrainingModRegisters[] = {
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FOREACH_PER_CHANNEL_TRAINING_MOD_REG(DECLARE_REGISTER_HANDLER)
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};
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using EmcDvfsTimingTable = mariko::EmcDvfsTimingTable;
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EmcDvfsTimingTable *GetEmcDvfsTimingTables(int index, void *mtc_tables_buffer) {
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@ -61,20 +106,228 @@ namespace ams::nxboot {
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return out_tables;
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}
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bool IsSamePll(u32 next_2x, u32 prev_2x) {
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if (next_2x == prev_2x) {
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return true;
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} else if ((next_2x == PLLM_OUT0 || next_2x == PLLM_UD) && (prev_2x == PLLM_OUT0 || prev_2x == PLLM_UD)) {
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return true;
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} else {
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return false;
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}
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}
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void DoMemoryTrainingMariko(int index, void *mtc_tables_buffer) {
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/* Get timing tables. */
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auto *timing_tables = GetEmcDvfsTimingTables(index, mtc_tables_buffer);
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auto *src_timing_tables = timing_tables + 0;
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auto *dst_timing_tables = timing_tables + 1;
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/* Check timing tables. */
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if (src_timing_tables->rate_khz != 204000 || dst_timing_tables->rate_khz != 1600000) {
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ShowFatalError("EmcDvfsTimingTables seem corrupted %" PRIu32 " %" PRIu32 "?\n", src_timing_tables->rate_khz, dst_timing_tables->rate_khz);
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bool PllReprogram(u32 next_rate_khz, u32 next_clk_src, u32 prev_rate_khz, u32 prev_clk_src) {
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/* Get current divp value. */
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u32 pll_p;
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switch (reg::GetValue(CLKRST + CLK_RST_CONTROLLER_CLK_SOURCE_EMC, CLK_RST_REG_BITS_MASK(CLK_SOURCE_EMC_EMC_2X_CLK_SRC))) {
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case PLLM_UD:
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case PLLM_OUT0:
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pll_p = reg::GetValue(CLKRST + CLK_RST_CONTROLLER_PLLM_BASE, CLK_RST_REG_BITS_MASK(PLLM_BASE_PLLM_DIVP_B01));
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break;
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case PLLMB_UD:
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case PLLMB_OUT0:
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pll_p = reg::GetValue(CLKRST + CLK_RST_CONTROLLER_PLLMB_BASE, CLK_RST_REG_BITS_MASK(PLLMB_BASE_PLLMB_DIVP_B01));
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break;
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default:
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pll_p = 0;
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break;
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}
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/* Get clk src/divisor. */
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const u32 next_2x = reg::GetField(next_clk_src, CLK_RST_REG_BITS_MASK(CLK_SOURCE_EMC_EMC_2X_CLK_SRC));
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const u32 prev_2x = reg::GetField(prev_clk_src, CLK_RST_REG_BITS_MASK(CLK_SOURCE_EMC_EMC_2X_CLK_SRC));
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u32 next_div = reg::GetField(next_clk_src, CLK_RST_REG_BITS_MASK(CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR));
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u32 prev_div = reg::GetField(prev_clk_src, CLK_RST_REG_BITS_MASK(CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR));
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/* Update divisor, if necessary. */
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if (next_2x == PLLM_UD || next_2x == PLLMB_UD) {
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next_div = 0;
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}
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if (prev_2x == PLLM_UD || prev_2x == PLLMB_UD) {
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prev_div = 0;
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}
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/* If the pll is different, reprogramming is necessary. */
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if (!IsSamePll(next_2x, prev_2x)) {
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return true;
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}
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/* Return whether the ratios are different. */
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const float next_freq = next_rate_khz * (1 + (next_div >> 1) + (0.5 * (next_div & 1))) * (pll_p + 1);
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const float prev_freq = prev_rate_khz * (1 + (prev_div >> 1) + (0.5 * (prev_div & 1))) * (pll_p + 1);
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const float ratio = prev_freq / next_freq;
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return ratio > 1.01 || ratio < 0.99;
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}
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u32 ProgramPllm(u32 next_rate_khz, u32 next_clk_src, u32 ret_clk_src, bool is_pllmb, EmcDvfsTimingTable *timing_tables) {
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u32 ret = ret_clk_src;
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const uint32_t base = ((timing_tables->pllmb_divm & 0xFF) | ((timing_tables->pllmb_divn & 0xFF) << 8) | ((timing_tables->pllmb_divp & 1) << 20));
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if (is_pllmb) {
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reg::Write(CLKRST + CLK_RST_CONTROLLER_PLLMB_BASE, base);
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reg::Read(CLKRST + CLK_RST_CONTROLLER_PLLMB_BASE);
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reg::SetBits(CLKRST + CLK_RST_CONTROLLER_PLLMB_MISC1, 0x10000000);
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if (timing_tables->pll_en_ssc & 1) {
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reg::Write(CLKRST + CLK_RST_CONTROLLER_PLLMB_SS_CFG, timing_tables->pllmb_ss_cfg);
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reg::Write(CLKRST + CLK_RST_CONTROLLER_PLLMB_SS_CTRL1, timing_tables->pllmb_ss_ctrl1);
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reg::Write(CLKRST + CLK_RST_CONTROLLER_PLLMB_SS_CTRL2, timing_tables->pllmb_ss_ctrl2);
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} else {
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reg::Write(CLKRST + CLK_RST_CONTROLLER_PLLMB_SS_CFG, timing_tables->pllmb_ss_cfg & 0xBFFFFFFF);
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reg::Write(CLKRST + CLK_RST_CONTROLLER_PLLMB_SS_CTRL2, timing_tables->pllmb_ss_ctrl2 & 0x0000FFFF);
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}
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reg::SetBits(CLKRST + CLK_RST_CONTROLLER_PLLMB_BASE, 0x40000000);
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switch (reg::GetField(ret, CLK_RST_REG_BITS_MASK(CLK_SOURCE_EMC_EMC_2X_CLK_SRC))) {
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case PLLM_OUT0:
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reg::SetField(ret, CLK_RST_REG_BITS_VALUE(CLK_SOURCE_EMC_EMC_2X_CLK_SRC, PLLMB_OUT0));
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break;
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case PLLM_UD:
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reg::SetField(ret, CLK_RST_REG_BITS_VALUE(CLK_SOURCE_EMC_EMC_2X_CLK_SRC, PLLMB_UD));
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break;
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}
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while ((reg::Read(CLKRST + CLK_RST_CONTROLLER_PLLMB_BASE) & 0x8000000) == 0) { /* ... */ }
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return ret;
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} else {
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reg::Write(CLKRST + CLK_RST_CONTROLLER_PLLM_BASE, base);
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reg::Read(CLKRST + CLK_RST_CONTROLLER_PLLM_BASE);
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reg::SetBits(CLKRST + CLK_RST_CONTROLLER_PLLM_MISC2, 0x10);
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if (timing_tables->pll_en_ssc & 1) {
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reg::Write(CLKRST + CLK_RST_CONTROLLER_PLLM_SS_CFG, timing_tables->pllm_ss_cfg);
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reg::Write(CLKRST + CLK_RST_CONTROLLER_PLLM_SS_CTRL1, timing_tables->pllm_ss_ctrl1);
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reg::Write(CLKRST + CLK_RST_CONTROLLER_PLLM_SS_CTRL2, timing_tables->pllm_ss_ctrl2);
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} else {
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reg::Write(CLKRST + CLK_RST_CONTROLLER_PLLM_SS_CFG, timing_tables->pllm_ss_cfg & 0xBFFFFFFF);
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reg::Write(CLKRST + CLK_RST_CONTROLLER_PLLM_SS_CTRL2, timing_tables->pllm_ss_ctrl2 & 0x0000FFFF);
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}
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reg::SetBits(CLKRST + CLK_RST_CONTROLLER_PLLM_BASE, 0x40000000);
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switch (reg::GetField(ret, CLK_RST_REG_BITS_MASK(CLK_SOURCE_EMC_EMC_2X_CLK_SRC))) {
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case PLLM_OUT0:
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reg::SetField(ret, CLK_RST_REG_BITS_VALUE(CLK_SOURCE_EMC_EMC_2X_CLK_SRC, PLLM_OUT0));
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break;
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case PLLM_UD:
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reg::SetField(ret, CLK_RST_REG_BITS_VALUE(CLK_SOURCE_EMC_EMC_2X_CLK_SRC, PLLM_UD));
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break;
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}
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while ((reg::Read(CLKRST + CLK_RST_CONTROLLER_PLLM_BASE) & 0x8000000) == 0) { /* ... */ }
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return ret;
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}
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}
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void FreqChange(EmcDvfsTimingTable *src_timing, EmcDvfsTimingTable *dst_timing, u32 training, u32 next_clk_src) {
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/* TODO */
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}
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void TrainFreq(EmcDvfsTimingTable *src_timing, EmcDvfsTimingTable *dst_timing, u32 next_clk_src) {
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/* TODO */
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}
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void Dvfs(EmcDvfsTimingTable *dst_timing, EmcDvfsTimingTable *src_timing, bool train) {
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/* Get the clock sources/rates. */
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u32 clk_src_emc_from = src_timing->clk_src_emc;
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u32 clk_src_emc_to = dst_timing->clk_src_emc;
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u32 rate_from = src_timing->rate_khz;
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u32 rate_to = dst_timing->rate_khz;
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/* Get channel enables. */
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const bool ch0_enable = reg::GetField(dst_timing->emc_fbio_cfg7, EMC_REG_BITS_MASK(FBIO_CFG7_CH0_ENABLE)) == EMC_FBIO_CFG7_CH0_ENABLE_ENABLE;
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const bool ch1_enable = reg::GetField(dst_timing->emc_fbio_cfg7, EMC_REG_BITS_MASK(FBIO_CFG7_CH1_ENABLE)) == EMC_FBIO_CFG7_CH1_ENABLE_ENABLE;
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/* Reprogram pll. */
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const u32 prev_2x_clk_src = reg::GetField(clk_src_emc_from, CLK_RST_REG_BITS_MASK(CLK_SOURCE_EMC_EMC_2X_CLK_SRC));
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const u32 next_2x_clk_src = reg::GetField(clk_src_emc_to, CLK_RST_REG_BITS_MASK(CLK_SOURCE_EMC_EMC_2X_CLK_SRC));
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if (next_2x_clk_src != PLLP_OUT0 && next_2x_clk_src != PLLP_UD) {
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if (ch0_enable || ch1_enable) {
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if (PllReprogram(rate_to, clk_src_emc_to, rate_from, clk_src_emc_from)) {
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if (prev_2x_clk_src == PLLMB_UD || prev_2x_clk_src == PLLMB_OUT0) {
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g_next_pll = 0;
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} else if (prev_2x_clk_src == PLLM_UD || prev_2x_clk_src == PLLM_OUT0) {
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g_next_pll = !g_next_pll;
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}
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clk_src_emc_to = ProgramPllm(rate_to, clk_src_emc_to, clk_src_emc_to, g_next_pll, dst_timing);
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} else {
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if (next_2x_clk_src == PLLM_UD || next_2x_clk_src == PLLMB_UD) {
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if (g_next_pll) {
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reg::SetField(clk_src_emc_to, CLK_RST_REG_BITS_VALUE(CLK_SOURCE_EMC_EMC_2X_CLK_SRC, PLLMB_UD));
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}
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} else if (next_2x_clk_src == PLLM_OUT0 || next_2x_clk_src == PLLMB_OUT0) {
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if (g_next_pll) {
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reg::SetField(clk_src_emc_to, CLK_RST_REG_BITS_VALUE(CLK_SOURCE_EMC_EMC_2X_CLK_SRC, PLLMB_OUT0));
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}
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}
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}
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}
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}
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if (train) {
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TrainFreq(src_timing, dst_timing, clk_src_emc_to);
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if (ch0_enable || ch1_enable) {
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if (PllReprogram(dst_timing->rate_khz, dst_timing->clk_src_emc, src_timing->rate_khz, src_timing->clk_src_emc)) {
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g_next_pll = !g_next_pll;
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}
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}
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} else {
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FreqChange(src_timing, dst_timing, 0, clk_src_emc_to);
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}
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}
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}
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void DoMemoryTrainingMariko(bool *out_did_training, int index, void *mtc_tables_buffer) {
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/* Get timing tables. */
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auto *timing_tables = GetEmcDvfsTimingTables(index, mtc_tables_buffer);
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auto *src_timing = timing_tables + 0;
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auto *dst_timing = timing_tables + 1;
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/* Check timing tables. */
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if (src_timing->rate_khz != 204000 || dst_timing->rate_khz != 1600000) {
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ShowFatalError("EmcDvfsTimingTables seem corrupted %" PRIu32 " %" PRIu32 "?\n", src_timing->rate_khz, dst_timing->rate_khz);
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}
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/* Check that we should do training. */
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if (src_timing->clk_src_emc != reg::Read(CLKRST + CLK_RST_CONTROLLER_CLK_SOURCE_EMC)) {
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/* Our clock source isn't what's expected, so presumably training has already been done? */
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/* Either way, the safe bet is to skip it. */
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*out_did_training = false;
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return;
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}
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/* Train 1600MHz. */
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Dvfs(dst_timing, src_timing, true);
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/* Switch to 1600MHz. */
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Dvfs(dst_timing, src_timing, false);
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/* Set ourselves as having done training */
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*out_did_training = true;
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}
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void RestoreMemoryClockRateMariko(void *mtc_tables_buffer) {
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/* Get timing tables. */
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auto *timing_tables = reinterpret_cast<EmcDvfsTimingTable *>(mtc_tables_buffer);
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auto *src_timing = timing_tables + 0;
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auto *dst_timing = timing_tables + 1;
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/* Check timing tables. */
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if (src_timing->rate_khz != 204000 || dst_timing->rate_khz != 1600000) {
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ShowFatalError("EmcDvfsTimingTables seem corrupted %" PRIu32 " %" PRIu32 "?\n", src_timing->rate_khz, dst_timing->rate_khz);
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}
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/* Switch to 204MHz */
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Dvfs(src_timing, dst_timing, false);
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}
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}
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@ -67,6 +67,15 @@
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#define CLK_RST_CONTROLLER_PLLC4_BASE (0x5A4)
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#define CLK_RST_CONTROLLER_PLLC_MISC2 (0x5D0)
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#define CLK_RST_CONTROLLER_PLLMB_BASE (0x5E8)
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#define CLK_RST_CONTROLLER_PLLMB_MISC1 (0x5EC)
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/* Mariko. */
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#define CLK_RST_CONTROLLER_PLLM_SS_CFG (0x774)
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#define CLK_RST_CONTROLLER_PLLM_SS_CTRL1 (0x778)
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#define CLK_RST_CONTROLLER_PLLM_SS_CTRL2 (0x77C)
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#define CLK_RST_CONTROLLER_PLLMB_SS_CFG (0x780)
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#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL1 (0x784)
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#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL2 (0x788)
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#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA (0x0F8)
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#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB (0x0FC)
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@ -118,6 +127,7 @@ DEFINE_CLK_RST_REG_BIT_ENUM(PLLC_OUT_PLLC_OUT1_DIV_BYP, 16, DISABLE, ENABLE);
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DEFINE_CLK_RST_REG(PLLM_BASE_PLLM_DIVM, 0, 8);
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DEFINE_CLK_RST_REG(PLLM_BASE_PLLM_DIVN, 8, 8);
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DEFINE_CLK_RST_REG(PLLM_BASE_PLLM_DIVP, 20, 5);
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DEFINE_CLK_RST_REG(PLLM_BASE_PLLM_DIVP_B01, 20, 1);
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DEFINE_CLK_RST_REG_BIT_ENUM(PLLM_BASE_PLLM_LOCK, 27, NOT_LOCK, LOCK);
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DEFINE_CLK_RST_REG_BIT_ENUM(PLLM_BASE_PLLM_REF_DIS, 29, REF_ENABLE, REF_DISABLE);
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DEFINE_CLK_RST_REG_BIT_ENUM(PLLM_BASE_PLLM_ENABLE, 30, DISABLE, ENABLE);
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@ -167,6 +177,7 @@ DEFINE_CLK_RST_REG_BIT_ENUM(PLLC4_BASE_PLLC4_ENABLE, 30, DISABLE, ENABLE);
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DEFINE_CLK_RST_REG(PLLMB_BASE_PLLMB_DIVM, 0, 8);
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DEFINE_CLK_RST_REG(PLLMB_BASE_PLLMB_DIVN, 8, 8);
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DEFINE_CLK_RST_REG(PLLMB_BASE_PLLMB_DIVP, 20, 5);
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DEFINE_CLK_RST_REG(PLLMB_BASE_PLLMB_DIVP_B01, 20, 1);
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DEFINE_CLK_RST_REG_BIT_ENUM(PLLMB_BASE_PLLMB_LOCK, 27, NOT_LOCK, LOCK);
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DEFINE_CLK_RST_REG_BIT_ENUM(PLLMB_BASE_PLLMB_ENABLE, 30, DISABLE, ENABLE);
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@ -242,6 +242,7 @@
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/* Mariko */
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#define EMC_PMACRO_DLL_CFG_0 (0x5E4)
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#define EMC_PMACRO_DLL_CFG_1 (0x5E8)
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#define EMC_PMACRO_DLL_CFG_2 (0x5F8)
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||||
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#define EMC_CONFIG_SAMPLE_DELAY (0x5F0)
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#define EMC_CFG_UPDATE (0x5F4)
|
||||
|
|
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Loading…
Reference in a new issue