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ENUMs for APB Slave Security Enable registers (#67)

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Exosphere: add enums for the APB_MISC_SECURE registers.
This commit is contained in:
Resaec 2018-04-25 18:46:17 +02:00 committed by SciresM
parent dba0d62ef7
commit b6b8ca0eac
2 changed files with 88 additions and 9 deletions
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18
exosphere/src/bootup.c
View file

@ -85,22 +85,22 @@ void bootup_misc_mmio(void) {
/* Mark registers secure world only. */ /* Mark registers secure world only. */
/* Mark SATA_AUX, DTV, QSPI, SE, SATA, LA secure only. */ /* Mark SATA_AUX, DTV, QSPI, SE, SATA, LA secure only. */
APB_MISC_SECURE_REGS_APB_SLAVE_SECURITY_ENABLE_REG0_0 = 0x504244; APB_MISC_SECURE_REGS_APB_SLAVE_SECURITY_ENABLE_REG0_0 = APB_SSER0_SATA_AUX | APB_SSER0_DTV | APB_SSER0_QSPI | APB_SSER0_SE | APB_SSER0_SATA | APB_SSER0_LA;
/* By default, mark SPI1, SPI2, SPI3, SPI5, SPI6, I2C6 secure only. */ /* By default, mark SPI1, SPI2, SPI3, SPI5, SPI6, I2C6 secure only. */
uint32_t sec_disable_1 = 0x83700000; uint32_t sec_disable_1 = APB_SSER1_SPI1 | APB_SSER1_SPI2 | APB_SSER1_SPI3 | APB_SSER1_SPI5 | APB_SSER1_SPI6 | APB_SSER1_I2C6;
/* By default, mark SDMMC3, DDS, DP2 secure only. */ /* By default, mark SDMMC3, DDS, DP2 secure only. */
uint32_t sec_disable_2 = 0x304; uint32_t sec_disable_2 = APB_SSER2_SDMMC3 | APB_SSER2_DDS | APB_SSER2_DP2;
uint64_t hardware_type = configitem_get_hardware_type(); uint64_t hardware_type = configitem_get_hardware_type();
if (hardware_type != 1) { if (hardware_type != 1) {
/* Also mark I2C5 secure only, */ /* Also mark I2C4 secure only, */
sec_disable_1 |= 0x20000000; sec_disable_1 |= APB_SSER1_I2C4;
} }
if (hardware_type != 0 && exosphere_get_target_firmware() >= EXOSPHERE_TARGET_FIRMWARE_400) { if (hardware_type != 0 && exosphere_get_target_firmware() >= EXOSPHERE_TARGET_FIRMWARE_400) {
/* Starting on 4.x on non-dev units, mark UARTB, UARTC, SPI4, I2C3 secure only. */ /* Starting on 4.x on non-dev units, mark UARTB, UARTC, SPI4, I2C3 secure only. */
sec_disable_1 |= 0x10806000; sec_disable_1 |= APB_SSER1_UART_B | APB_SSER1_UART_C | APB_SSER1_SPI4 | APB_SSER1_I2C3;
/* Starting on 4.x on non-dev units, mark SDMMC1 secure only. */ /* Starting on 4.x on non-dev units, mark SDMMC1 secure only. */
sec_disable_2 |= 1; sec_disable_2 |= APB_SSER2_SDMMC1;
} }
APB_MISC_SECURE_REGS_APB_SLAVE_SECURITY_ENABLE_REG1_0 = sec_disable_1; APB_MISC_SECURE_REGS_APB_SLAVE_SECURITY_ENABLE_REG1_0 = sec_disable_1;
APB_MISC_SECURE_REGS_APB_SLAVE_SECURITY_ENABLE_REG2_0 = sec_disable_2; APB_MISC_SECURE_REGS_APB_SLAVE_SECURITY_ENABLE_REG2_0 = sec_disable_2;
@ -283,8 +283,8 @@ void identity_unmap_iram_cd_tzram(void) {
void secure_additional_devices(void) { void secure_additional_devices(void) {
if (exosphere_get_target_firmware() >= EXOSPHERE_TARGET_FIRMWARE_400) { if (exosphere_get_target_firmware() >= EXOSPHERE_TARGET_FIRMWARE_400) {
APB_MISC_SECURE_REGS_APB_SLAVE_SECURITY_ENABLE_REG0_0 |= 0x2000; /* make PMC secure-only (2.x+ but see note below) */ APB_MISC_SECURE_REGS_APB_SLAVE_SECURITY_ENABLE_REG0_0 |= APB_SSER0_PMC; /* make PMC secure-only (2.x+ but see note below) */
APB_MISC_SECURE_REGS_APB_SLAVE_SECURITY_ENABLE_REG1_0 |= 0X510; /* make MC0, MC1, MCB secure-only (4.x+) */ APB_MISC_SECURE_REGS_APB_SLAVE_SECURITY_ENABLE_REG1_0 |= APB_SSER1_MC0 | APB_SSER1_MC1 | APB_SSER1_MCB; /* make MC0, MC1, MCB secure-only (4.x+) */
} else { } else {
/* TODO: Detect 1.x */ /* TODO: Detect 1.x */
} }

79
exosphere/src/bootup.h
View file

@ -3,6 +3,85 @@
#include <stdint.h> #include <stdint.h>
/* 21.1.7 AP Control Registers */
/* 21.1.7.1 APB_MISC_SECURE_REGS_APB_SLAVE_SECURITY_ENABLE_REG0_0 slaves */
typedef enum {
APB_SSER0_MISC_REGS = 1 << 1, /* PP, SC1x pads and GP registers */
APB_SSER0_SATA_AUX = 1 << 2,
APB_SSER0_PINMUX_AUX = 1 << 3,
APB_SSER0_APE = 1 << 4,
APB_SSER0_DTV = 1 << 6,
APB_SSER0_PWM = 1 << 8, /* PWFM */
APB_SSER0_QSPI = 1 << 9,
APB_SSER0_CSITE = 1 << 10, /* Core Site */
APB_SSER0_RTC = 1 << 11,
APB_SSER0_PMC = 1 << 13,
APB_SSER0_SE = 1 << 14, /* Security Engine */
APB_SSER0_FUSE = 1 << 15,
APB_SSER0_KFUSE = 1 << 16,
APB_SSER0_UNUSED = 1 << 18, /* reserved, unused but listed as accessible */
APB_SSER0_SATA = 1 << 20,
APB_SSER0_HDA = 1 << 21,
APB_SSER0_LA = 1 << 22,
APB_SSER0_ATOMICS = 1 << 23,
APB_SSER0_CEC = 1 << 24,
STM = 1 << 29
} APB_SSER0;
/* 21.1.7.2 APB_MISC_SECURE_REGS_APB_SLAVE_SECURITY_ENABLE_REG1_0 slaves */
typedef enum {
APB_SSER1_MC0 = 1 << 4,
APB_SSER1_EMC0 = 1 << 5,
APB_SSER1_MC1 = 1 << 8,
APB_SSER1_EMC1 = 1 << 9,
APB_SSER1_MCB = 1 << 10,
APB_SSER1_EMBC = 1 << 11,
APB_SSER1_UART_A = 1 << 12,
APB_SSER1_UART_B = 1 << 13,
APB_SSER1_UART_C = 1 << 14,
APB_SSER1_UART_D = 1 << 15,
APB_SSER1_SPI1 = 1 << 20,
APB_SSER1_SPI2 = 1 << 21,
APB_SSER1_SPI3 = 1 << 22,
APB_SSER1_SPI4 = 1 << 23,
APB_SSER1_SPI5 = 1 << 24,
APB_SSER1_SPI6 = 1 << 25,
APB_SSER1_I2C1 = 1 << 26,
APB_SSER1_I2C2 = 1 << 27,
APB_SSER1_I2C3 = 1 << 28,
APB_SSER1_I2C4 = 1 << 29,
APB_SSER1_DVC = 1 << 30,
APB_SSER1_I2C5 = 1 << 30,
APB_SSER1_I2C6 = 1 << 31 /* this will show as negative because of the 32bit sign bit being set */
} APB_SSER1;
/* 21.1.7.3 APB_MISC_SECURE_REGS_APB_SLAVE_SECURITY_ENABLE_REG2_0 slaves */
typedef enum {
APB_SSER2_SDMMC1 = 1 << 0,
APB_SSER2_SDMMC2 = 1 << 1,
APB_SSER2_SDMMC3 = 1 << 2,
APB_SSER2_SDMMC4 = 1 << 3,
APB_SSER2_MIPIBIF = 1 << 7, /* reserved */
APB_SSER2_DDS = 1 << 8,
APB_SSER2_DP2 = 1 << 9,
APB_SSER2_SOC_THERM = 1 << 10,
APB_SSER2_APB2JTAG = 1 << 11,
APB_SSER2_XUSB_HOST = 1 << 12,
APB_SSER2_XUSB_DEV = 1 << 13,
APB_SSER2_XUSB_PADCTL = 1 << 14,
APB_SSER2_MIPI_CAL = 1 << 15,
APB_SSER2_DVFS = 1 << 16
} APB_SSER2;
void bootup_misc_mmio(void); void bootup_misc_mmio(void);
void setup_4x_mmio(void); void setup_4x_mmio(void);