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https://github.com/Atmosphere-NX/Atmosphere
synced 2024-12-22 20:31:14 +00:00
kern: fix multicore instruction cache invalidation
This commit is contained in:
parent
f058536b59
commit
b5f2698bf0
3 changed files with 72 additions and 35 deletions
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@ -59,11 +59,6 @@ namespace ams::kern::arch::arm64::cpu {
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InstructionMemoryBarrier();
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InstructionMemoryBarrier();
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}
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}
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ALWAYS_INLINE void InvalidateEntireInstructionCache() {
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__asm__ __volatile__("ic iallu" ::: "memory");
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EnsureInstructionConsistency();
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}
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ALWAYS_INLINE void Yield() {
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ALWAYS_INLINE void Yield() {
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__asm__ __volatile__("yield" ::: "memory");
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__asm__ __volatile__("yield" ::: "memory");
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}
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}
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@ -179,6 +174,7 @@ namespace ams::kern::arch::arm64::cpu {
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void ClearPageToZeroImpl(void *);
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void ClearPageToZeroImpl(void *);
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void FlushEntireDataCacheSharedForInit();
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void FlushEntireDataCacheSharedForInit();
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void FlushEntireDataCacheLocalForInit();
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void FlushEntireDataCacheLocalForInit();
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void InvalidateEntireInstructionCacheForInit();
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void StoreEntireCacheForInit();
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void StoreEntireCacheForInit();
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void FlushEntireDataCache();
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void FlushEntireDataCache();
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@ -188,6 +184,8 @@ namespace ams::kern::arch::arm64::cpu {
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Result FlushDataCache(const void *addr, size_t size);
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Result FlushDataCache(const void *addr, size_t size);
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Result InvalidateInstructionCache(void *addr, size_t size);
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Result InvalidateInstructionCache(void *addr, size_t size);
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void InvalidateEntireInstructionCache();
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ALWAYS_INLINE void ClearPageToZero(void *page) {
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ALWAYS_INLINE void ClearPageToZero(void *page) {
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MESOSPHERE_ASSERT(util::IsAligned(reinterpret_cast<uintptr_t>(page), PageSize));
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MESOSPHERE_ASSERT(util::IsAligned(reinterpret_cast<uintptr_t>(page), PageSize));
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MESOSPHERE_ASSERT(page != nullptr);
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MESOSPHERE_ASSERT(page != nullptr);
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@ -155,43 +155,56 @@ namespace ams::kern::arch::arm64::cpu {
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void RequestOperation(Operation op) {
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void RequestOperation(Operation op) {
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KScopedLightLock lk(this->lock);
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KScopedLightLock lk(this->lock);
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MESOSPHERE_ABORT_UNLESS(this->operation == Operation::Idle);
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/* Send and wait for acknowledgement of request. */
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/* Create core masks for us to use. */
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{
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constexpr u64 AllCoresMask = (1ul << cpu::NumCores) - 1ul;
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KScopedLightLock cv_lk(this->cv_lock);
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const u64 other_cores_mask = AllCoresMask & ~(1ul << GetCurrentCoreId());
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if ((op == Operation::InvalidateInstructionCache) || (Kernel::GetState() == Kernel::State::Initializing)) {
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/* Check that there's no on-going operation. */
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MESOSPHERE_ABORT_UNLESS(this->operation == Operation::Idle);
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MESOSPHERE_ABORT_UNLESS(this->target_cores == 0);
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MESOSPHERE_ABORT_UNLESS(this->target_cores == 0);
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/* Set operation. */
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/* Set operation. */
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this->operation = op;
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this->operation = op;
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/* Create core masks for us to use. */
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/* For certain operations, we want to send an interrupt. */
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constexpr u64 AllCoresMask = (1ul << cpu::NumCores) - 1ul;
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this->target_cores = other_cores_mask;
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const u64 other_cores_mask = AllCoresMask & ~(1ul << GetCurrentCoreId());
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if ((op == Operation::InvalidateInstructionCache) || (Kernel::GetState() == Kernel::State::Initializing)) {
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const u64 target_mask = this->target_cores;
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/* For certain operations, we want to send an interrupt. */
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DataSynchronizationBarrier();
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this->target_cores = other_cores_mask;
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Kernel::GetInterruptManager().SendInterProcessorInterrupt(KInterruptName_CacheOperation, target_mask);
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DataSynchronizationBarrier();
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const u64 target_mask = this->target_cores;
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DataSynchronizationBarrier();
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Kernel::GetInterruptManager().SendInterProcessorInterrupt(KInterruptName_CacheOperation, target_mask);
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this->ProcessOperation();
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while (this->target_cores != 0) {
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cpu::Yield();
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}
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} else {
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/* Request all cores. */
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this->target_cores = AllCoresMask;
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/* Use the condvar. */
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this->ProcessOperation();
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this->cv.Broadcast();
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while (this->target_cores != 0) {
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while (this->target_cores != 0) {
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cpu::Yield();
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this->cv.Wait(std::addressof(this->cv_lock));
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}
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}
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}
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/* Go idle again. */
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this->operation = Operation::Idle;
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} else {
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/* Lock condvar so that we can send and wait for acknowledgement of request. */
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KScopedLightLock cv_lk(this->cv_lock);
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/* Check that there's no on-going operation. */
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MESOSPHERE_ABORT_UNLESS(this->operation == Operation::Idle);
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MESOSPHERE_ABORT_UNLESS(this->target_cores == 0);
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/* Set operation. */
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this->operation = op;
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/* Request all cores. */
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this->target_cores = AllCoresMask;
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/* Use the condvar. */
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this->cv.Broadcast();
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while (this->target_cores != 0) {
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this->cv.Wait(std::addressof(this->cv_lock));
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}
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/* Go idle again. */
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this->operation = Operation::Idle;
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}
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}
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/* Go idle again. */
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this->operation = Operation::Idle;
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}
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}
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};
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};
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@ -285,6 +298,8 @@ namespace ams::kern::arch::arm64::cpu {
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DataSynchronizationBarrier();
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DataSynchronizationBarrier();
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break;
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break;
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}
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}
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this->target_cores &= ~(1ul << GetCurrentCoreId());
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}
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}
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ALWAYS_INLINE void SetEventLocally() {
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ALWAYS_INLINE void SetEventLocally() {
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@ -327,6 +342,14 @@ namespace ams::kern::arch::arm64::cpu {
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return ResultSuccess();
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return ResultSuccess();
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}
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}
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ALWAYS_INLINE void InvalidateEntireInstructionCacheLocalImpl() {
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__asm__ __volatile__("ic iallu" ::: "memory");
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}
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ALWAYS_INLINE void InvalidateEntireInstructionCacheGlobalImpl() {
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__asm__ __volatile__("ic ialluis" ::: "memory");
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}
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}
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}
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void FlushEntireDataCacheSharedForInit() {
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void FlushEntireDataCacheSharedForInit() {
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@ -337,11 +360,16 @@ namespace ams::kern::arch::arm64::cpu {
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return PerformCacheOperationBySetWayLocal<true>(FlushDataCacheLineBySetWayImpl);
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return PerformCacheOperationBySetWayLocal<true>(FlushDataCacheLineBySetWayImpl);
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}
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}
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void InvalidateEntireInstructionCacheForInit() {
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InvalidateEntireInstructionCacheLocalImpl();
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EnsureInstructionConsistency();
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}
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void StoreEntireCacheForInit() {
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void StoreEntireCacheForInit() {
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PerformCacheOperationBySetWayLocal<true>(StoreDataCacheLineBySetWayImpl);
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PerformCacheOperationBySetWayLocal<true>(StoreDataCacheLineBySetWayImpl);
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PerformCacheOperationBySetWayShared<true>(StoreDataCacheLineBySetWayImpl);
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PerformCacheOperationBySetWayShared<true>(StoreDataCacheLineBySetWayImpl);
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DataSynchronizationBarrierInnerShareable();
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DataSynchronizationBarrierInnerShareable();
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InvalidateEntireInstructionCache();
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InvalidateEntireInstructionCacheForInit();
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}
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}
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void FlushEntireDataCache() {
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void FlushEntireDataCache() {
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@ -401,6 +429,17 @@ namespace ams::kern::arch::arm64::cpu {
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return ResultSuccess();
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return ResultSuccess();
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}
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}
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void InvalidateEntireInstructionCache() {
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KScopedCoreMigrationDisable dm;
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/* Invalidate the instruction cache on all cores. */
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InvalidateEntireInstructionCacheGlobalImpl();
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EnsureInstructionConsistency();
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/* Request the interrupt helper to invalidate, too. */
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g_cache_operation_handler.RequestOperation(KCacheHelperInterruptHandler::Operation::InvalidateInstructionCache);
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}
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void InitializeInterruptThreads(s32 core_id) {
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void InitializeInterruptThreads(s32 core_id) {
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/* Initialize the cache operation handler. */
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/* Initialize the cache operation handler. */
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g_cache_operation_handler.Initialize(core_id);
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g_cache_operation_handler.Initialize(core_id);
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@ -81,7 +81,7 @@ namespace ams::kern::init::loader {
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cpu::DataSynchronizationBarrier();
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cpu::DataSynchronizationBarrier();
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/* Invalidate entire instruction cache. */
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/* Invalidate entire instruction cache. */
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cpu::InvalidateEntireInstructionCache();
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cpu::InvalidateEntireInstructionCacheForInit();
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/* Invalidate entire TLB. */
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/* Invalidate entire TLB. */
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cpu::InvalidateEntireTlb();
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cpu::InvalidateEntireTlb();
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