mirror of
https://github.com/Atmosphere-NX/Atmosphere
synced 2024-11-09 22:56:35 +00:00
exo: cleanup + (theoretical) 1.0.0 support in smcCpuSuspend
This commit is contained in:
SciresM
GitHub
parent
e5bfb95c22
commit
b5234e9efb
1 changed files with 167 additions and 100 deletions
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@ -27,8 +27,122 @@
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#undef u8
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#undef u8
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#undef u32
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#undef u32
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/* Save security engine, and go to sleep. */
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static void configure_battery_hi_z_mode(void) {
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void save_se_and_power_down_cpu(void) {
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clkrst_reboot(CARDEVICE_I2C1);
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if (configitem_should_profile_battery() && !i2c_query_ti_charger_bit_7()) {
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/* Profile the battery. */
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i2c_set_ti_charger_bit_7();
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uint32_t start_time = get_time();
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bool should_wait = true;
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/* TODO: This is GPIO-6 GPIO_IN_1 */
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while (MAKE_REG32(MMIO_GET_DEVICE_ADDRESS(MMIO_DEVID_GPIO) + 0x634) & 1) {
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if (get_time() - start_time > 50000) {
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should_wait = false;
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break;
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}
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}
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if (should_wait) {
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wait(0x100);
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}
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}
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clkrst_disable(CARDEVICE_I2C1);
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}
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static void enable_lp0_wake_events(void) {
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wait(75);
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APBDEV_PMC_CNTRL2_0 |= 0x200; /* Set WAKE_DET_EN. */
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wait(75);
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APBDEV_PM_0 = 0xFFFFFFFF; /* Set all wake events. */
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APBDEV_PMC_WAKE2_STATUS_0 = 0xFFFFFFFF; /* Set all wake events. */
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wait(75);
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}
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static void notify_pmic_shutdown(void) {
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clkrst_reboot(CARDEVICE_I2C5);
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if (fuse_get_bootrom_patch_version() >= 0x7F) {
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i2c_send_pmic_cpu_shutdown_cmd();
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}
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}
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static void mitigate_jamais_vu(void) {
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/* Jamais Vu mitigation #1: Ensure all other cores are off. */
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if (APBDEV_PMC_PWRGATE_STATUS_0 & 0xE00) {
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generic_panic();
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}
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/* For debugging, make this check always pass. */
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if ((exosphere_get_target_firmware() < EXOSPHERE_TARGET_FIRMWARE_400 || (get_debug_authentication_status() & 3) == 3)) {
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FLOW_CTLR_HALT_COP_EVENTS_0 = 0x50000000;
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} else {
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FLOW_CTLR_HALT_COP_EVENTS_0 = 0x40000000;
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}
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/* Jamais Vu mitigation #2: Ensure the BPMP is halted. */
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if (exosphere_get_target_firmware() < EXOSPHERE_TARGET_FIRMWARE_400 || (get_debug_authentication_status() & 3) == 3) {
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/* BPMP should just be plainly halted, in debugging conditions. */
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if (FLOW_CTLR_HALT_COP_EVENTS_0 != 0x50000000) {
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generic_panic();
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}
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} else {
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/* BPMP must be in never-woken-up halt mode, under normal conditions. */
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if (FLOW_CTLR_HALT_COP_EVENTS_0 != 0x40000000) {
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generic_panic();
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}
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}
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/* Jamais Vu mitigation #3: Ensure all relevant DMA controllers are held in reset. */
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if ((CLK_RST_CONTROLLER_RST_DEVICES_H_0 & 0x4000004) != 0x4000004) {
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generic_panic();
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}
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}
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static void configure_pmc_for_deep_powerdown(void) {
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APBDEV_PMC_SCRATCH0_0 = 1;
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APBDEV_PMC_DPD_ENABLE_0 |= 2;
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}
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static void setup_bpmp_sc7_firmware(void) {
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/* Mark PMC registers as not secure-world only, so BPMP can access them. */
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APB_MISC_SECURE_REGS_APB_SLAVE_SECURITY_ENABLE_REG0_0 &= 0xFFFFDFFF;
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/* Setup BPMP vectors. */
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BPMP_VECTOR_RESET = 0x40003000; /* lp0_entry_firmware_crt0 */
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BPMP_VECTOR_UNDEF = 0x40003004; /* Reboot. */
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BPMP_VECTOR_SWI = 0x40003004; /* Reboot. */
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BPMP_VECTOR_PREFETCH_ABORT = 0x40003004; /* Reboot. */
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BPMP_VECTOR_DATA_ABORT = 0x40003004; /* Reboot. */
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BPMP_VECTOR_UNK = 0x40003004; /* Reboot. */
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BPMP_VECTOR_IRQ = 0x40003004; /* Reboot. */
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BPMP_VECTOR_FIQ = 0x40003004; /* Reboot. */
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/* Hold the BPMP in reset. */
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MAKE_CAR_REG(0x300) = 2;
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/* Copy BPMP firmware. */
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uint8_t *lp0_entry_code = (uint8_t *)(LP0_ENTRY_GET_RAM_SEGMENT_ADDRESS(LP0_ENTRY_RAM_SEGMENT_ID_LP0_ENTRY_CODE));
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for (unsigned int i = 0; i < bpmpfw_bin_size; i += 4) {
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write32le(lp0_entry_code, i, read32le(bpmpfw_bin, i));
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}
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flush_dcache_range(lp0_entry_code, lp0_entry_code + bpmpfw_bin_size);
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/* Take the BPMP out of reset. */
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MAKE_CAR_REG(0x304) = 2;
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/* Start executing BPMP firmware. */
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FLOW_CTLR_HALT_COP_EVENTS_0 = 0;
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}
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static void configure_flow_regs_for_sleep(void) {
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unsigned int current_core = get_core_id();
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flow_set_cc4_ctrl(current_core, 0);
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flow_set_halt_events(current_core, false);
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FLOW_CTLR_L2FLUSH_CONTROL_0 = 0;
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flow_set_csr(current_core, 2);
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}
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static void save_tzram_state(void) {
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/* TODO: Remove set suspend call once exo warmboots fully */
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/* TODO: Remove set suspend call once exo warmboots fully */
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set_suspend_for_debug();
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set_suspend_for_debug();
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uint32_t tzram_cmac[0x4] = {0};
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uint32_t tzram_cmac[0x4] = {0};
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@ -71,6 +185,28 @@ void save_se_and_power_down_cpu(void) {
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APBDEV_PMC_SECURE_SCRATCH115_0 = tzram_cmac[3];
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APBDEV_PMC_SECURE_SCRATCH115_0 = tzram_cmac[3];
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APBDEV_PMC_SEC_DISABLE8_0 = 0x550000;
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APBDEV_PMC_SEC_DISABLE8_0 = 0x550000;
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/* Perform pre-2.0.0 PMC writes. */
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if (exosphere_get_target_firmware() < EXOSPHERE_TARGET_FIRMWARE_200) {
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/* TODO: Give these writes appropriate defines in pmc.h */
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/* Save Encrypted context location + lock scratch register. */
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MAKE_REG32(PMC_BASE + 0x360) = WARMBOOT_GET_RAM_SEGMENT_PA(WARMBOOT_RAM_SEGMENT_ID_TZRAM);
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MAKE_REG32(PMC_BASE + 0x2D8) = 0x10000;
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/* Save Encryption parameters (where to copy TZRAM to, source, destination, size) */
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MAKE_REG32(PMC_BASE + 0x340) = LP0_ENTRY_GET_RAM_SEGMENT_PA(LP0_ENTRY_RAM_SEGMENT_ID_CURRENT_TZRAM);
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MAKE_REG32(PMC_BASE + 0x344) = 0;
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MAKE_REG32(PMC_BASE + 0x348) = LP0_ENTRY_GET_RAM_SEGMENT_PA(LP0_ENTRY_RAM_SEGMENT_ID_CURRENT_TZRAM);
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MAKE_REG32(PMC_BASE + 0x34C) = 0;
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MAKE_REG32(PMC_BASE + 0x350) = LP0_ENTRY_GET_RAM_SEGMENT_PA(LP0_ENTRY_RAM_SEGMENT_ID_CURRENT_TZRAM);
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MAKE_REG32(PMC_BASE + 0x354) = LP0_TZRAM_SAVE_SIZE;
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/* Lock scratch registers. */
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MAKE_REG32(PMC_BASE + 0x2D8) = 0x555;
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}
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}
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static void save_se_state(void) {
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/* Save security engine state. */
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/* Save security engine state. */
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uint8_t *se_state_dst = (uint8_t *)(WARMBOOT_GET_RAM_SEGMENT_ADDRESS(WARMBOOT_RAM_SEGMENT_ID_SE_STATE));
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uint8_t *se_state_dst = (uint8_t *)(WARMBOOT_GET_RAM_SEGMENT_ADDRESS(WARMBOOT_RAM_SEGMENT_ID_SE_STATE));
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se_check_error_status_reg();
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se_check_error_status_reg();
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@ -80,6 +216,13 @@ void save_se_and_power_down_cpu(void) {
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APBDEV_PMC_SCRATCH43_0 = (uint32_t)(WARMBOOT_GET_RAM_SEGMENT_PA(WARMBOOT_RAM_SEGMENT_ID_SE_STATE));
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APBDEV_PMC_SCRATCH43_0 = (uint32_t)(WARMBOOT_GET_RAM_SEGMENT_PA(WARMBOOT_RAM_SEGMENT_ID_SE_STATE));
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se_set_in_context_save_mode(false);
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se_set_in_context_save_mode(false);
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se_check_error_status_reg();
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se_check_error_status_reg();
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}
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/* Save security engine, and go to sleep. */
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void save_se_and_power_down_cpu(void) {
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/* Save context for warmboot to restore. */
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save_tzram_state();
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save_se_state();
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if (!configitem_is_retail()) {
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if (!configitem_is_retail()) {
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/* TODO: uart_log("OYASUMI"); */
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/* TODO: uart_log("OYASUMI"); */
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@ -96,120 +239,44 @@ uint32_t cpu_suspend(uint64_t power_state, uint64_t entrypoint, uint64_t argumen
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return 0xFFFFFFFD;
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return 0xFFFFFFFD;
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}
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}
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/* Perform I2C comms with TI charger if required. */
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unsigned int current_core = get_core_id();
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configure_battery_hi_z_mode();
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clkrst_reboot(CARDEVICE_I2C1);
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if (configitem_should_profile_battery() && !i2c_query_ti_charger_bit_7()) {
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/* Profile the battery. */
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i2c_set_ti_charger_bit_7();
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uint32_t start_time = get_time();
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bool should_wait = true;
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/* TODO: This is GPIO-6 GPIO_IN_1 */
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while (MAKE_REG32(MMIO_GET_DEVICE_ADDRESS(MMIO_DEVID_GPIO) + 0x634) & 1) {
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if (get_time() - start_time > 50000) {
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should_wait = false;
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break;
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}
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}
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if (should_wait) {
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wait(0x100);
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}
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}
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clkrst_disable(CARDEVICE_I2C1);
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/* Enable LP0 Wake Event Detection. */
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/* Enable LP0 Wake Event Detection. */
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wait(75);
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enable_lp0_wake_events();
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APBDEV_PMC_CNTRL2_0 |= 0x200; /* Set WAKE_DET_EN. */
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wait(75);
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APBDEV_PM_0 = 0xFFFFFFFF; /* Set all wake events. */
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APBDEV_PMC_WAKE2_STATUS_0 = 0xFFFFFFFF; /* Set all wake events. */
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wait(75);
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clkrst_reboot(CARDEVICE_I2C5);
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/* Alert the PMC of an iminent shutdown. */
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if (fuse_get_bootrom_patch_version() >= 0x7F) {
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notify_pmic_shutdown();
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i2c_send_pmic_cpu_shutdown_cmd();
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}
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/* Jamais Vu mitigation #1: Ensure all other cores are off. */
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/* Validate that the shutdown has correct context. */
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if (APBDEV_PMC_PWRGATE_STATUS_0 & 0xE00) {
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if (exosphere_get_target_firmware() >= EXOSPHERE_TARGET_FIRMWARE_200) {
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generic_panic();
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mitigate_jamais_vu();
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}
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/* For debugging, make this check always pass. */
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if ((exosphere_get_target_firmware() < EXOSPHERE_TARGET_FIRMWARE_400 || (get_debug_authentication_status() & 3) == 3)) {
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FLOW_CTLR_HALT_COP_EVENTS_0 = 0x50000000;
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} else {
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FLOW_CTLR_HALT_COP_EVENTS_0 = 0x40000000;
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}
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/* Jamais Vu mitigation #2: Ensure the BPMP is halted. */
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if (exosphere_get_target_firmware() < EXOSPHERE_TARGET_FIRMWARE_400 || (get_debug_authentication_status() & 3) == 3) {
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/* BPMP should just be plainly halted, in debugging conditions. */
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if (FLOW_CTLR_HALT_COP_EVENTS_0 != 0x50000000) {
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generic_panic();
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}
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} else {
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/* BPMP must be in never-woken-up halt mode, under normal conditions. */
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if (FLOW_CTLR_HALT_COP_EVENTS_0 != 0x40000000) {
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generic_panic();
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}
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}
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/* Jamais Vu mitigation #3: Ensure all relevant DMA controllers are held in reset. */
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if ((CLK_RST_CONTROLLER_RST_DEVICES_H_0 & 0x4000004) != 0x4000004) {
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generic_panic();
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}
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}
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/* Signal to bootrom the next reset should be a warmboot. */
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/* Signal to bootrom the next reset should be a warmboot. */
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APBDEV_PMC_SCRATCH0_0 = 1;
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configure_pmc_for_deep_powerdown();
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APBDEV_PMC_DPD_ENABLE_0 |= 2;
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/* Prepare to boot the BPMP running our deep sleep firmware. */
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/* Ensure that BPMP SC7 firmware is active. */
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if (exosphere_get_target_firmware() >= EXOSPHERE_TARGET_FIRMWARE_200) {
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/* Mark PMC registers as not secure-world only, so BPMP can access them. */
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setup_bpmp_sc7_firmware();
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APB_MISC_SECURE_REGS_APB_SLAVE_SECURITY_ENABLE_REG0_0 &= 0xFFFFDFFF;
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/* Setup BPMP vectors. */
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BPMP_VECTOR_RESET = 0x40003000; /* lp0_entry_firmware_crt0 */
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BPMP_VECTOR_UNDEF = 0x40003004; /* Reboot. */
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BPMP_VECTOR_SWI = 0x40003004; /* Reboot. */
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BPMP_VECTOR_PREFETCH_ABORT = 0x40003004; /* Reboot. */
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BPMP_VECTOR_DATA_ABORT = 0x40003004; /* Reboot. */
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BPMP_VECTOR_UNK = 0x40003004; /* Reboot. */
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BPMP_VECTOR_IRQ = 0x40003004; /* Reboot. */
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BPMP_VECTOR_FIQ = 0x40003004; /* Reboot. */
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/* Hold the BPMP in reset. */
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MAKE_CAR_REG(0x300) = 2;
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/* Copy BPMP firmware. */
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uint8_t *lp0_entry_code = (uint8_t *)(LP0_ENTRY_GET_RAM_SEGMENT_ADDRESS(LP0_ENTRY_RAM_SEGMENT_ID_LP0_ENTRY_CODE));
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for (unsigned int i = 0; i < bpmpfw_bin_size; i += 4) {
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write32le(lp0_entry_code, i, read32le(bpmpfw_bin, i));
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}
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}
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flush_dcache_range(lp0_entry_code, lp0_entry_code + bpmpfw_bin_size);
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/* Take the BPMP out of reset. */
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MAKE_CAR_REG(0x304) = 2;
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/* Start executing BPMP firmware. */
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FLOW_CTLR_HALT_COP_EVENTS_0 = 0;
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/* Prepare the current core for sleep. */
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/* Prepare the current core for sleep. */
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flow_set_cc4_ctrl(current_core, 0);
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configure_flow_regs_for_sleep();
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flow_set_halt_events(current_core, false);
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FLOW_CTLR_L2FLUSH_CONTROL_0 = 0;
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flow_set_csr(current_core, 2);
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/* Save core context. */
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/* Save core context. */
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set_core_entrypoint_and_argument(current_core, entrypoint, argument);
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set_core_entrypoint_and_argument(get_core_id(), entrypoint, argument);
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save_current_core_context();
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save_current_core_context();
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set_current_core_inactive();
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set_current_core_inactive();
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/* Ensure that other cores are already asleep. */
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call_with_stack_pointer(get_smc_core012_stack_address(), save_se_and_power_down_cpu);
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if (!(APBDEV_PMC_PWRGATE_STATUS_0 & 0xE00)) {
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if (exosphere_get_target_firmware() >= EXOSPHERE_TARGET_FIRMWARE_200) {
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call_with_stack_pointer(get_smc_core012_stack_address(), save_se_and_power_down_cpu);
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} else {
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save_se_and_power_down_cpu();
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}
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}
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generic_panic();
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generic_panic();
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}
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}
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||||||
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Reference in a new issue