fusee: Implement DRAM training:

- Based on reverse engineered code and Peter De Schrijver's patches;
- Complemented with CTCaer's minerva_tc project.
This commit is contained in:
hexkyz 2018-11-12 01:55:16 +00:00
parent a520481168
commit b19e50e720
6 changed files with 12880 additions and 671 deletions

View file

@ -24,15 +24,74 @@
#define FUSEE_EMC_H_ #define FUSEE_EMC_H_
#define EMC_BASE 0x7001B000 #define EMC_BASE 0x7001B000
#define EMC0_BASE 0x7001E000
#define EMC1_BASE 0x7001F000
#define MAKE_EMC_REG(n) MAKE_REG32(EMC_BASE + n) #define MAKE_EMC_REG(n) MAKE_REG32(EMC_BASE + n)
#define MAKE_EMC0_REG(n) MAKE_REG32(EMC0_BASE + n)
#define MAKE_EMC1_REG(n) MAKE_REG32(EMC1_BASE + n)
#define EMC_INTSTATUS 0x0
#define EMC_INTSTATUS_MRR_DIVLD (0x1 << 5)
#define EMC_INTSTATUS_CLKCHANGE_COMPLETE (0x1 << 4)
#define EMC_INTMASK 0x4
#define EMC_DBG 0x8 #define EMC_DBG 0x8
#define EMC_CFG 0xC #define EMC_DBG_WRITE_MUX_ACTIVE (1 << 1)
#define EMC_DBG_CFG_SWAP_SHIFT 26
#define EMC_DBG_CFG_SWAP_MASK \
(0x3 << EMC_DBG_CFG_SWAP_SHIFT)
#define EMC_DBG_WRITE_ACTIVE_ONLY (1 << 30)
#define EMC_CONFIG_SAMPLE_DELAY 0x5f0 #define EMC_CONFIG_SAMPLE_DELAY 0x5f0
#define EMC_CFG_UPDATE 0x5f4 #define EMC_CFG_UPDATE 0x5f4
#define EMC_CFG_UPDATE_UPDATE_DLL_IN_UPDATE_SHIFT 9
#define EMC_CFG_UPDATE_UPDATE_DLL_IN_UPDATE_MASK \
(0x3 << EMC_CFG_UPDATE_UPDATE_DLL_IN_UPDATE_SHIFT)
#define EMC_CFG 0xc
#define EMC_CFG_DRAM_CLKSTOP_PD (1 << 31)
#define EMC_CFG_DRAM_CLKSTOP_SR (1 << 30)
#define EMC_CFG_DRAM_ACPD (1 << 29)
#define EMC_CFG_DYN_SELF_REF (1 << 28)
#define EMC_CFG_REQACT_ASYNC (1 << 26)
#define EMC_CFG_AUTO_PRE_WR (1 << 25)
#define EMC_CFG_AUTO_PRE_RD (1 << 24)
#define EMC_CFG_MAM_PRE_WR (1 << 23)
#define EMC_CFG_MAN_PRE_RD (1 << 22)
#define EMC_CFG_PERIODIC_QRST (1 << 21)
#define EMC_CFG_PERIODIC_QRST_SHIFT (21)
#define EMC_CFG_EN_DYNAMIC_PUTERM (1 << 20)
#define EMC_CFG_DLY_WR_DQ_HALF_CLOCK (1 << 19)
#define EMC_CFG_DSR_VTTGEN_DRV_EN (1 << 18)
#define EMC_CFG_EMC2MC_CLK_RATIO (3 << 16)
#define EMC_CFG_WAIT_FOR_ISP2B_READY_B4_CC (1 << 9)
#define EMC_CFG_WAIT_FOR_VI2_READY_B4_CC (1 << 8)
#define EMC_CFG_WAIT_FOR_ISP2_READY_B4_CC (1 << 7)
#define EMC_CFG_INVERT_DQM (1 << 6)
#define EMC_CFG_WAIT_FOR_DISPLAYB_READY_B4_CC (1 << 5)
#define EMC_CFG_WAIT_FOR_DISPLAY_READY_B4_CC (1 << 4)
#define EMC_CFG_EMC2PMACRO_CFG_BYPASS_DATAPIPE2 (1 << 3)
#define EMC_CFG_EMC2PMACRO_CFG_BYPASS_DATAPIPE1 (1 << 2)
#define EMC_CFG_EMC2PMACRO_CFG_BYPASS_ADDRPIPE (1 << 1)
#define EMC_ADR_CFG 0x10 #define EMC_ADR_CFG 0x10
#define EMC_REFCTRL 0x20 #define EMC_REFCTRL 0x20
#define EMC_REFCTRL_DEV_SEL_SHIFT 0
#define EMC_REFCTRL_DEV_SEL_MASK \
(0x3 << EMC_REFCTRL_DEV_SEL_SHIFT)
#define EMC_REFCTRL_ENABLE (0x1 << 31)
#define EMC_REFCTRL_ENABLE_ALL(num) \
(((((num) > 1) ? 0 : 2) << EMC_REFCTRL_DEV_SEL_SHIFT) \
| EMC_REFCTRL_ENABLE)
#define EMC_REFCTRL_DISABLE_ALL(num) \
((((num) > 1) ? 0 : 2) << EMC_REFCTRL_DEV_SEL_SHIFT)
#define EMC_PIN 0x24 #define EMC_PIN 0x24
#define EMC_PIN_PIN_CKE_PER_DEV (1 << 2)
#define EMC_PIN_PIN_CKEB (1 << 1)
#define EMC_PIN_PIN_CKE (1 << 0)
#define EMC_CLK_FORCE_CC_TRIGGER (1 << 27)
#define EMC_TIMING_CONTROL 0x28 #define EMC_TIMING_CONTROL 0x28
#define EMC_RC 0x2c #define EMC_RC 0x2c
#define EMC_RFC 0x30 #define EMC_RFC 0x30
@ -77,24 +136,88 @@
#define EMC_WEXT 0xb8 #define EMC_WEXT 0xb8
#define EMC_RFC_SLR 0xc0 #define EMC_RFC_SLR 0xc0
#define EMC_MRS_WAIT_CNT2 0xc4 #define EMC_MRS_WAIT_CNT2 0xc4
#define EMC_MRS_WAIT_CNT2_MRS_EXT2_WAIT_CNT_SHIFT 16
#define EMC_MRS_WAIT_CNT2_MRS_EXT2_WAIT_CNT_MASK \
(0x7ff << EMC_MRS_WAIT_CNT2_MRS_EXT2_WAIT_CNT_SHIFT)
#define EMC_MRS_WAIT_CNT2_MRS_EXT1_WAIT_CNT_SHIFT 0
#define EMC_MRS_WAIT_CNT2_MRS_EXT1_WAIT_CNT_MASK \
(0x3ff << EMC_MRS_WAIT_CNT2_MRS_EXT1_WAIT_CNT_SHIFT)
#define EMC_MRS_WAIT_CNT 0xc8 #define EMC_MRS_WAIT_CNT 0xc8
#define EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT 0
#define EMC_MRS_WAIT_CNT_SHORT_WAIT_MASK \
(0x3FF << EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT)
#define EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT 16
#define EMC_MRS_WAIT_CNT_LONG_WAIT_MASK \
(0x3FF << EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT)
#define EMC_MRS 0xcc #define EMC_MRS 0xcc
#define EMC_MODE_SET_DLL_RESET (1 << 8)
#define EMC_MRS_USE_MRS_LONG_CNT (1 << 26)
#define EMC_EMRS 0xd0 #define EMC_EMRS 0xd0
#define EMC_EMRS_USE_EMRS_LONG_CNT (1 << 26)
#define EMC_REF 0xd4 #define EMC_REF 0xd4
#define EMC_REF_FORCE_CMD 1
#define EMC_PRE 0xd8 #define EMC_PRE 0xd8
#define EMC_NOP 0xdc #define EMC_NOP 0xdc
#define EMC_SELF_REF 0xe0 #define EMC_SELF_REF 0xe0
#define EMC_SELF_REF_CMD_ENABLED (1 << 0)
#define EMC_SELF_REF_ACTIVE_SELF_REF (1 << 8)
#define EMC_SELF_REF_DEV_SEL_SHIFT 30
#define EMC_SELF_REF_DEV_SEL_MASK \
(0x3 << EMC_SELF_REF_DEV_SEL_SHIFT)
#define EMC_DPD 0xe4 #define EMC_DPD 0xe4
#define EMC_MRW 0xe8 #define EMC_MRW 0xe8
#define EMC_MRW_MRW_OP_SHIFT 0
#define EMC_MRW_MRW_OP_MASK \
(0xff << EMC_MRW_MRW_OP_SHIFT)
#define EMC_MRW_MRW_MA_SHIFT 16
#define EMC_MRW_MRW_MA_MASK \
(0xff << EMC_MRW_MRW_MA_SHIFT)
#define EMC_MRW_USE_MRW_LONG_CNT 26
#define EMC_MRW_USE_MRW_EXT_CNT 27
#define EMC_MRW_MRW_DEV_SELECTN_SHIFT 30
#define EMC_MRW_MRW_DEV_SELECTN_MASK \
(0x3 << EMC_MRW_MRW_DEV_SELECTN_SHIFT)
#define EMC_MRR 0xec #define EMC_MRR 0xec
#define EMC_MRR_DEV_SEL_SHIFT 30
#define EMC_MRR_DEV_SEL_MASK \
(0x3 << EMC_SELF_REF_DEV_SEL_SHIFT)
#define EMC_MRR_MA_SHIFT 16
#define EMC_MRR_MA_MASK \
(0xff << EMC_MRR_MA_SHIFT)
#define EMC_MRR_DATA_SHIFT 0
#define EMC_MRR_DATA_MASK \
(0xffff << EMC_MRR_DATA_SHIFT)
#define LPDDR2_MR4_TEMP_SHIFT 0
#define LPDDR2_MR4_TEMP_MASK \
(0x7 << LPDDR2_MR4_TEMP_SHIFT)
#define EMC_CMDQ 0xf0 #define EMC_CMDQ 0xf0
#define EMC_MC2EMCQ 0xf4 #define EMC_MC2EMCQ 0xf4
#define EMC_FBIO_SPARE 0x100 #define EMC_FBIO_SPARE 0x100
#define EMC_FBIO_CFG5 0x104 #define EMC_FBIO_CFG5 0x104
#define EMC_FBIO_CFG5_DRAM_TYPE_SHIFT 0
#define EMC_FBIO_CFG5_DRAM_TYPE_MASK \
(0x3 << EMC_FBIO_CFG5_DRAM_TYPE_SHIFT)
#define EMC_FBIO_CFG5_CMD_TX_DIS (1 << 8)
#define EMC_FBIO_CFG5_CMD_BUS_RETURN_TO_ZERO (1 << 27)
#define EMC_CFG5_QUSE_MODE_SHIFT 13
#define EMC_CFG5_QUSE_MODE_MASK \
(0x7 << EMC_CFG5_QUSE_MODE_SHIFT)
#define EMC_CFG_RSV 0x120 #define EMC_CFG_RSV 0x120
#define EMC_ACPD_CONTROL 0x124 #define EMC_ACPD_CONTROL 0x124
#define EMC_MPC 0x128 #define EMC_MPC 0x128
#define EMC_EMRS2 0x12c #define EMC_EMRS2 0x12c
#define EMC_EMRS2_USE_EMRS2_LONG_CNT (1 << 26)
#define EMC_EMRS3 0x130 #define EMC_EMRS3 0x130
#define EMC_MRW2 0x134 #define EMC_MRW2 0x134
#define EMC_MRW3 0x138 #define EMC_MRW3 0x138
@ -207,6 +330,12 @@
#define EMC_STAT_DRAM_IO_SR_CKE_EQ0_CLKS_HI 0xcd0 #define EMC_STAT_DRAM_IO_SR_CKE_EQ0_CLKS_HI 0xcd0
#define EMC_STAT_DRAM_IO_DSR 0xcd4 #define EMC_STAT_DRAM_IO_DSR 0xcd4
#define EMC_AUTO_CAL_CONFIG 0x2a4 #define EMC_AUTO_CAL_CONFIG 0x2a4
#define EMC_AUTO_CAL_CONFIG_AUTO_CAL_COMPUTE_START (1 << 0)
#define EMC_AUTO_CAL_CONFIG_AUTO_CAL_MEASURE_STALL (1 << 9)
#define EMC_AUTO_CAL_CONFIG_AUTO_CAL_UPDATE_STALL (1 << 10)
#define EMC_AUTO_CAL_CONFIG_AUTO_CAL_ENABLE (1 << 29)
#define EMC_AUTO_CAL_CONFIG_AUTO_CAL_START (1 << 31)
#define EMC_AUTO_CAL_CONFIG2 0x458 #define EMC_AUTO_CAL_CONFIG2 0x458
#define EMC_AUTO_CAL_CONFIG3 0x45c #define EMC_AUTO_CAL_CONFIG3 0x45c
#define EMC_AUTO_CAL_CONFIG4 0x5b0 #define EMC_AUTO_CAL_CONFIG4 0x5b0
@ -228,17 +357,47 @@
#define EMC_PMACRO_AUTOCAL_CFG_1 0x704 #define EMC_PMACRO_AUTOCAL_CFG_1 0x704
#define EMC_PMACRO_AUTOCAL_CFG_2 0x708 #define EMC_PMACRO_AUTOCAL_CFG_2 0x708
#define EMC_PMACRO_AUTOCAL_CFG_COMMON 0xc78 #define EMC_PMACRO_AUTOCAL_CFG_COMMON 0xc78
#define EMC_PMACRO_AUTOCAL_CFG_COMMON_E_CAL_BYPASS_DVFS (1 << 16)
#define EMC_PMACRO_ZCTRL 0xc44 #define EMC_PMACRO_ZCTRL 0xc44
#define EMC_XM2COMPPADCTRL 0x30c #define EMC_XM2COMPPADCTRL 0x30c
#define EMC_XM2COMPPADCTRL_VREF_CAL_ENABLE (1 << 10)
#define EMC_XM2COMPPADCTRL2 0x578 #define EMC_XM2COMPPADCTRL2 0x578
#define EMC_XM2COMPPADCTRL3 0x2f4 #define EMC_XM2COMPPADCTRL3 0x2f4
#define EMC_COMP_PAD_SW_CTRL 0x57c #define EMC_COMP_PAD_SW_CTRL 0x57c
#define EMC_REQ_CTRL 0x2b0 #define EMC_REQ_CTRL 0x2b0
#define EMC_EMC_STATUS 0x2b4 #define EMC_EMC_STATUS 0x2b4
#define EMC_EMC_STATUS_MRR_DIVLD (1 << 20)
#define EMC_EMC_STATUS_TIMING_UPDATE_STALLED (1 << 23)
#define EMC_EMC_STATUS_DRAM_IN_POWERDOWN_SHIFT 4
#define EMC_EMC_STATUS_DRAM_IN_POWERDOWN_MASK \
(0x3 << EMC_EMC_STATUS_DRAM_IN_POWERDOWN_SHIFT)
#define EMC_EMC_STATUS_DRAM_IN_SELF_REFRESH_SHIFT 8
#define EMC_EMC_STATUS_DRAM_IN_SELF_REFRESH_MASK \
(0x3 << EMC_EMC_STATUS_DRAM_IN_SELF_REFRESH_SHIFT)
#define EMC_CFG_2 0x2b8 #define EMC_CFG_2 0x2b8
#define EMC_CFG_DIG_DLL 0x2bc #define EMC_CFG_DIG_DLL 0x2bc
#define EMC_CFG_DIG_DLL_CFG_DLL_EN (1 << 0)
#define EMC_CFG_DIG_DLL_CFG_DLL_STALL_ALL_UNTIL_LOCK (1 << 1)
#define EMC_CFG_DIG_DLL_CFG_DLL_STALL_ALL_TRAFFIC (1 << 3)
#define EMC_CFG_DIG_DLL_CFG_DLL_STALL_RW_UNTIL_LOCK (1 << 4)
#define EMC_CFG_DIG_DLL_CFG_DLL_MODE_SHIFT 6
#define EMC_CFG_DIG_DLL_CFG_DLL_MODE_MASK \
(0x3 << EMC_CFG_DIG_DLL_CFG_DLL_MODE_SHIFT)
#define EMC_CFG_DIG_DLL_CFG_DLL_LOCK_LIMIT_SHIFT 8
#define EMC_CFG_DIG_DLL_CFG_DLL_LOCK_LIMIT_MASK \
(0x7 << EMC_CFG_DIG_DLL_CFG_DLL_LOCK_LIMIT_SHIFT)
#define EMC_CFG_DIG_DLL_PERIOD 0x2c0 #define EMC_CFG_DIG_DLL_PERIOD 0x2c0
#define EMC_DIG_DLL_STATUS 0x2c4 #define EMC_DIG_DLL_STATUS 0x2c4
#define EMC_DIG_DLL_STATUS_DLL_LOCK (1 << 15)
#define EMC_DIG_DLL_STATUS_DLL_PRIV_UPDATED (1 << 17)
#define EMC_DIG_DLL_STATUS_DLL_OUT_SHIFT 0
#define EMC_DIG_DLL_STATUS_DLL_OUT_MASK \
(0x7ff << EMC_DIG_DLL_STATUS_DLL_OUT_SHIFT)
#define EMC_CFG_DIG_DLL_1 0x2c8 #define EMC_CFG_DIG_DLL_1 0x2c8
#define EMC_RDV_MASK 0x2cc #define EMC_RDV_MASK 0x2cc
#define EMC_WDV_MASK 0x2d0 #define EMC_WDV_MASK 0x2d0
@ -247,21 +406,100 @@
#define EMC_WDV_CHK 0x4e0 #define EMC_WDV_CHK 0x4e0
#define EMC_ZCAL_INTERVAL 0x2e0 #define EMC_ZCAL_INTERVAL 0x2e0
#define EMC_ZCAL_WAIT_CNT 0x2e4 #define EMC_ZCAL_WAIT_CNT 0x2e4
#define EMC_ZCAL_WAIT_CNT_ZCAL_WAIT_CNT_MASK 0x7ff
#define EMC_ZCAL_WAIT_CNT_ZCAL_WAIT_CNT_SHIFT 0
#define EMC_ZCAL_MRW_CMD 0x2e8 #define EMC_ZCAL_MRW_CMD 0x2e8
#define EMC_ZQ_CAL 0x2ec #define EMC_ZQ_CAL 0x2ec
#define EMC_ZQ_CAL_DEV_SEL_SHIFT 30
#define EMC_ZQ_CAL_DEV_SEL_MASK \
(0x3 << EMC_SELF_REF_DEV_SEL_SHIFT)
#define EMC_ZQ_CAL_LONG (1 << 4)
#define EMC_ZQ_CAL_ZQ_LATCH_CMD (1 << 1)
#define EMC_ZQ_CAL_ZQ_CAL_CMD (1 << 0)
#define EMC_ZQ_CAL_LONG_CMD_DEV0 \
(DRAM_DEV_SEL_0 | EMC_ZQ_CAL_LONG | EMC_ZQ_CAL_CMD)
#define EMC_ZQ_CAL_LONG_CMD_DEV1 \
(DRAM_DEV_SEL_1 | EMC_ZQ_CAL_LONG | EMC_ZQ_CAL_CMD)
#define EMC_SCRATCH0 0x324 #define EMC_SCRATCH0 0x324
#define EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE 0x3c8 #define EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE 0x3c8
#define EMC_STALL_THEN_EXE_AFTER_CLKCHANGE 0x3cc #define EMC_STALL_THEN_EXE_AFTER_CLKCHANGE 0x3cc
#define EMC_UNSTALL_RW_AFTER_CLKCHANGE 0x3d0 #define EMC_UNSTALL_RW_AFTER_CLKCHANGE 0x3d0
#define EMC_FDPD_CTRL_CMD_NO_RAMP 0x4d8 #define EMC_FDPD_CTRL_CMD_NO_RAMP 0x4d8
#define EMC_FDPD_CTRL_CMD_NO_RAMP_CMD_DPD_NO_RAMP_ENABLE (1 << 0)
#define EMC_SEL_DPD_CTRL 0x3d8 #define EMC_SEL_DPD_CTRL 0x3d8
#define EMC_SEL_DPD_CTRL_DATA_SEL_DPD_EN (1 << 8)
#define EMC_SEL_DPD_CTRL_ODT_SEL_DPD_EN (1 << 5)
#define EMC_SEL_DPD_CTRL_RESET_SEL_DPD_EN (1 << 4)
#define EMC_SEL_DPD_CTRL_CA_SEL_DPD_EN (1 << 3)
#define EMC_SEL_DPD_CTRL_CLK_SEL_DPD_EN (1 << 2)
#define EMC_SEL_DPD_CTRL_DDR3_MASK \
((0xf << 2) | (0x1 << 8))
#define EMC_SEL_DPD_CTRL_MAS \
((0x3 << 2) | (0x1 << 5) | (0x1 << 8))
#define EMC_FDPD_CTRL_DQ 0x310 #define EMC_FDPD_CTRL_DQ 0x310
#define EMC_FDPD_CTRL_CMD 0x314 #define EMC_FDPD_CTRL_CMD 0x314
#define EMC_PRE_REFRESH_REQ_CNT 0x3dc #define EMC_PRE_REFRESH_REQ_CNT 0x3dc
#define EMC_REFCTRL2 0x580 #define EMC_REFCTRL2 0x580
#define EMC_FBIO_CFG7 0x584 #define EMC_FBIO_CFG7 0x584
#define EMC_FBIO_CFG7_CH0_ENABLE (1 << 1)
#define EMC_FBIO_CFG7_CH1_ENABLE (1 << 2)
#define EMC_DATA_BRLSHFT_0 0x588 #define EMC_DATA_BRLSHFT_0 0x588
#define EMC_DATA_BRLSHFT_0_RANK0_BYTE7_DATA_BRLSHFT_SHIFT 21
#define EMC_DATA_BRLSHFT_0_RANK0_BYTE7_DATA_BRLSHFT_MASK \
(0x7 << EMC_DATA_BRLSHFT_0_RANK0_BYTE7_DATA_BRLSHFT_SHIFT)
#define EMC_DATA_BRLSHFT_0_RANK0_BYTE6_DATA_BRLSHFT_SHIFT 18
#define EMC_DATA_BRLSHFT_0_RANK0_BYTE6_DATA_BRLSHFT_MASK \
(0x7 << EMC_DATA_BRLSHFT_0_RANK0_BYTE6_DATA_BRLSHFT_SHIFT)
#define EMC_DATA_BRLSHFT_0_RANK0_BYTE5_DATA_BRLSHFT_SHIFT 15
#define EMC_DATA_BRLSHFT_0_RANK0_BYTE5_DATA_BRLSHFT_MASK \
(0x7 << EMC_DATA_BRLSHFT_0_RANK0_BYTE5_DATA_BRLSHFT_SHIFT)
#define EMC_DATA_BRLSHFT_0_RANK0_BYTE4_DATA_BRLSHFT_SHIFT 12
#define EMC_DATA_BRLSHFT_0_RANK0_BYTE4_DATA_BRLSHFT_MASK \
(0x7 << EMC_DATA_BRLSHFT_0_RANK0_BYTE4_DATA_BRLSHFT_SHIFT)
#define EMC_DATA_BRLSHFT_0_RANK0_BYTE3_DATA_BRLSHFT_SHIFT 9
#define EMC_DATA_BRLSHFT_0_RANK0_BYTE3_DATA_BRLSHFT_MASK \
(0x7 << EMC_DATA_BRLSHFT_0_RANK0_BYTE3_DATA_BRLSHFT_SHIFT)
#define EMC_DATA_BRLSHFT_0_RANK0_BYTE2_DATA_BRLSHFT_SHIFT 6
#define EMC_DATA_BRLSHFT_0_RANK0_BYTE2_DATA_BRLSHFT_MASK \
(0x7 << EMC_DATA_BRLSHFT_0_RANK0_BYTE2_DATA_BRLSHFT_SHIFT)
#define EMC_DATA_BRLSHFT_0_RANK0_BYTE1_DATA_BRLSHFT_SHIFT 3
#define EMC_DATA_BRLSHFT_0_RANK0_BYTE1_DATA_BRLSHFT_MASK \
(0x7 << EMC_DATA_BRLSHFT_0_RANK0_BYTE1_DATA_BRLSHFT_SHIFT)
#define EMC_DATA_BRLSHFT_0_RANK0_BYTE0_DATA_BRLSHFT_SHIFT 0
#define EMC_DATA_BRLSHFT_0_RANK0_BYTE0_DATA_BRLSHFT_MASK \
(0x7 << EMC_DATA_BRLSHFT_0_RANK0_BYTE0_DATA_BRLSHFT_SHIFT)
#define EMC_DATA_BRLSHFT_1 0x58c #define EMC_DATA_BRLSHFT_1 0x58c
#define EMC_DATA_BRLSHFT_1_RANK1_BYTE7_DATA_BRLSHFT_SHIFT 21
#define EMC_DATA_BRLSHFT_1_RANK1_BYTE7_DATA_BRLSHFT_MASK \
(0x7 << EMC_DATA_BRLSHFT_1_RANK1_BYTE7_DATA_BRLSHFT_SHIFT)
#define EMC_DATA_BRLSHFT_1_RANK1_BYTE6_DATA_BRLSHFT_SHIFT 18
#define EMC_DATA_BRLSHFT_1_RANK1_BYTE6_DATA_BRLSHFT_MASK \
(0x7 << EMC_DATA_BRLSHFT_1_RANK1_BYTE6_DATA_BRLSHFT_SHIFT)
#define EMC_DATA_BRLSHFT_1_RANK1_BYTE5_DATA_BRLSHFT_SHIFT 15
#define EMC_DATA_BRLSHFT_1_RANK1_BYTE5_DATA_BRLSHFT_MASK \
(0x7 << EMC_DATA_BRLSHFT_1_RANK1_BYTE5_DATA_BRLSHFT_SHIFT)
#define EMC_DATA_BRLSHFT_1_RANK1_BYTE4_DATA_BRLSHFT_SHIFT 12
#define EMC_DATA_BRLSHFT_1_RANK1_BYTE4_DATA_BRLSHFT_MASK \
(0x7 << EMC_DATA_BRLSHFT_1_RANK1_BYTE4_DATA_BRLSHFT_SHIFT)
#define EMC_DATA_BRLSHFT_1_RANK1_BYTE3_DATA_BRLSHFT_SHIFT 9
#define EMC_DATA_BRLSHFT_1_RANK1_BYTE3_DATA_BRLSHFT_MASK \
(0x7 << EMC_DATA_BRLSHFT_1_RANK1_BYTE3_DATA_BRLSHFT_SHIFT)
#define EMC_DATA_BRLSHFT_1_RANK1_BYTE2_DATA_BRLSHFT_SHIFT 6
#define EMC_DATA_BRLSHFT_1_RANK1_BYTE2_DATA_BRLSHFT_MASK \
(0x7 << EMC_DATA_BRLSHFT_1_RANK1_BYTE2_DATA_BRLSHFT_SHIFT)
#define EMC_DATA_BRLSHFT_1_RANK1_BYTE1_DATA_BRLSHFT_SHIFT 3
#define EMC_DATA_BRLSHFT_1_RANK1_BYTE1_DATA_BRLSHFT_MASK \
(0x7 << EMC_DATA_BRLSHFT_1_RANK1_BYTE1_DATA_BRLSHFT_SHIFT)
#define EMC_DATA_BRLSHFT_1_RANK1_BYTE0_DATA_BRLSHFT_SHIFT 0
#define EMC_DATA_BRLSHFT_1_RANK1_BYTE0_DATA_BRLSHFT_MASK \
(0x7 << EMC_DATA_BRLSHFT_1_RANK1_BYTE0_DATA_BRLSHFT_SHIFT)
#define EMC_DQS_BRLSHFT_0 0x594 #define EMC_DQS_BRLSHFT_0 0x594
#define EMC_DQS_BRLSHFT_1 0x598 #define EMC_DQS_BRLSHFT_1 0x598
#define EMC_CMD_BRLSHFT_0 0x59c #define EMC_CMD_BRLSHFT_0 0x59c
@ -303,6 +541,8 @@
#define EMC_TR_CTRL_0 0x3b8 #define EMC_TR_CTRL_0 0x3b8
#define EMC_TR_CTRL_1 0x3bc #define EMC_TR_CTRL_1 0x3bc
#define EMC_TR_DVFS 0x460 #define EMC_TR_DVFS 0x460
#define EMC_TR_DVFS_TRAINING_DVFS (1 << 0)
#define EMC_SWITCH_BACK_CTRL 0x3c0 #define EMC_SWITCH_BACK_CTRL 0x3c0
#define EMC_TR_RDV 0x3c4 #define EMC_TR_RDV 0x3c4
#define EMC_TR_QPOP 0x3f4 #define EMC_TR_QPOP 0x3f4
@ -319,6 +559,8 @@
#define EMC_CFG_3 0x49c #define EMC_CFG_3 0x49c
#define EMC_CFG_PIPE_2 0x554 #define EMC_CFG_PIPE_2 0x554
#define EMC_CFG_PIPE_CLK 0x558 #define EMC_CFG_PIPE_CLK 0x558
#define EMC_CFG_PIPE_CLK_CLK_ALWAYS_ON (1 << 0)
#define EMC_CFG_PIPE_1 0x55c #define EMC_CFG_PIPE_1 0x55c
#define EMC_CFG_PIPE 0x560 #define EMC_CFG_PIPE 0x560
#define EMC_QPOP 0x564 #define EMC_QPOP 0x564
@ -331,9 +573,47 @@
#define EMC_PROTOBIST_WDATA_UPPER 0x5e0 #define EMC_PROTOBIST_WDATA_UPPER 0x5e0
#define EMC_PROTOBIST_RDATA 0x5ec #define EMC_PROTOBIST_RDATA 0x5ec
#define EMC_DLL_CFG_0 0x5e4 #define EMC_DLL_CFG_0 0x5e4
#define EMC_DLL_CFG_0_DDLLCAL_CTRL_IGNORE_START (1 << 29)
#define EMC_DLL_CFG_0_DDLLCAL_CTRL_DUAL_PASS_LOCK (1 << 28)
#define EMC_DLL_CFG_0_DDLLCAL_CTRL_STEP_SIZE_SHIFT 24
#define EMC_DLL_CFG_0_DDLLCAL_CTRL_STEP_SIZE_MASK \
(0xf << EMC_DLL_CFG_0_DDLLCAL_CTRL_STEP_SIZE_SHIFT)
#define EMC_DLL_CFG_0_DDLLCAL_CTRL_END_COUNT_SHIFT 20
#define EMC_DLL_CFG_0_DDLLCAL_CTRL_END_COUNT_MASK \
(0xf << EMC_DLL_CFG_0_DDLLCAL_CTRL_END_COUNT_SHIFT)
#define EMC_DLL_CFG_0_DDLLCAL_CTRL_FILTER_BITS_SHIFT 16
#define EMC_DLL_CFG_0_DDLLCAL_CTRL_FILTER_BITS_MASK \
(0xf << EMC_DLL_CFG_0_DDLLCAL_CTRL_FILTER_BITS_SHIFT)
#define EMC_DLL_CFG_0_DDLLCAL_CTRL_SAMPLE_COUNT_SHIFT 12
#define EMC_DLL_CFG_0_DDLLCAL_CTRL_SAMPLE_COUNT_MASK \
(0xf << EMC_DLL_CFG_0_DDLLCAL_CTRL_SAMPLE_COUNT_SHIFT)
#define EMC_DLL_CFG_0_DDLLCAL_CTRL_SAMPLE_DELAY_SHIFT 4
#define EMC_DLL_CFG_0_DDLLCAL_CTRL_SAMPLE_DELAY_MASK \
(0xff << EMC_DLL_CFG_0_DDLLCAL_CTRL_SAMPLE_DELAY_SHIFT)
#define EMC_DLL_CFG_0_DDLLCAL_UPDATE_CNT_LIMIT_SHIFT 0
#define EMC_DLL_CFG_0_DDLLCAL_UPDATE_CNT_LIMIT_MASK \
(0xf << EMC_DLL_CFG_0_DDLLCAL_UPDATE_CNT_LIMIT_SHIFT)
#define EMC_DLL_CFG_1 0x5e8 #define EMC_DLL_CFG_1 0x5e8
#define EMC_DLL_CFG_1_DDLLCAL_CTRL_START_TRIM_SHIFT 10
#define EMC_DLL_CFG_1_DDLLCAL_CTRL_START_TRIM_MASK \
(0x7ff << EMC_DLL_CFG_1_DDLLCAL_CTRL_START_TRIM_SHIFT)
#define EMC_TRAINING_CMD 0xe00 #define EMC_TRAINING_CMD 0xe00
#define EMC_TRAINING_CMD_PRIME (1 << 0)
#define EMC_TRAINING_CMD_CA (1 << 1)
#define EMC_TRAINING_CMD_RD (1 << 2)
#define EMC_TRAINING_CMD_WR (1 << 3)
#define EMC_TRAINING_CMD_QUSE (1 << 4)
#define EMC_TRAINING_CMD_CA_VREF (1 << 5)
#define EMC_TRAINING_CMD_RD_VREF (1 << 6)
#define EMC_TRAINING_CMD_WR_VREF (1 << 7)
#define EMC_TRAINING_CMD_QUSE_VREF (1 << 8)
#define EMC_TRAINING_CMD_GO (1 << 31)
#define EMC_TRAINING_CTRL 0xe04 #define EMC_TRAINING_CTRL 0xe04
#define EMC_TRAINING_CTRL_SWAP_RANK (1 << 14)
#define EMC_TRAINING_STATUS 0xe08 #define EMC_TRAINING_STATUS 0xe08
#define EMC_TRAINING_QUSE_CORS_CTRL 0xe0c #define EMC_TRAINING_QUSE_CORS_CTRL 0xe0c
#define EMC_TRAINING_QUSE_FINE_CTRL 0xe10 #define EMC_TRAINING_QUSE_FINE_CTRL 0xe10
@ -401,15 +681,104 @@
#define EMC_PMACRO_QUSE_DDLL_RANK1_4 0x630 #define EMC_PMACRO_QUSE_DDLL_RANK1_4 0x630
#define EMC_PMACRO_QUSE_DDLL_RANK1_5 0x634 #define EMC_PMACRO_QUSE_DDLL_RANK1_5 0x634
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0 0x640 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0 0x640
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_OB_DDLL_LONG_DQ_RANK0_BYTE1_SHIFT \
16
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_OB_DDLL_LONG_DQ_RANK0_BYTE1_MASK \
0x3ff << \
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_OB_DDLL_LONG_DQ_RANK0_BYTE1_SHIFT
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_OB_DDLL_LONG_DQ_RANK0_BYTE0_SHIFT \
0
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_OB_DDLL_LONG_DQ_RANK0_BYTE0_MASK \
0x3ff << \
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_OB_DDLL_LONG_DQ_RANK0_BYTE0_SHIFT
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1 0x644 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1 0x644
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_OB_DDLL_LONG_DQ_RANK0_BYTE3_SHIFT \
16
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_OB_DDLL_LONG_DQ_RANK0_BYTE3_MASK \
0x3ff << \
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_OB_DDLL_LONG_DQ_RANK0_BYTE3_SHIFT
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_OB_DDLL_LONG_DQ_RANK0_BYTE2_SHIFT \
0
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_OB_DDLL_LONG_DQ_RANK0_BYTE2_MASK \
0x3ff << \
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_OB_DDLL_LONG_DQ_RANK0_BYTE2_SHIFT
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2 0x648 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2 0x648
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_OB_DDLL_LONG_DQ_RANK0_BYTE5_SHIFT \
16
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_OB_DDLL_LONG_DQ_RANK0_BYTE5_MASK \
0x3ff << \
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_OB_DDLL_LONG_DQ_RANK0_BYTE5_SHIFT
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_OB_DDLL_LONG_DQ_RANK0_BYTE4_SHIFT \
0
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_OB_DDLL_LONG_DQ_RANK0_BYTE4_MASK \
0x3ff << \
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_OB_DDLL_LONG_DQ_RANK0_BYTE4_SHIFT
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3 0x64c #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3 0x64c
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_OB_DDLL_LONG_DQ_RANK0_BYTE7_SHIFT \
16
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_OB_DDLL_LONG_DQ_RANK0_BYTE7_MASK \
0x3ff << \
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_OB_DDLL_LONG_DQ_RANK0_BYTE7_SHIFT
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_OB_DDLL_LONG_DQ_RANK0_BYTE6_SHIFT \
0
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_OB_DDLL_LONG_DQ_RANK0_BYTE6_MASK \
0x3ff << \
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_OB_DDLL_LONG_DQ_RANK0_BYTE6_SHIFT
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4 0x650 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4 0x650
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5 0x654 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5 0x654
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0 0x660 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0 0x660
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_OB_DDLL_LONG_DQ_RANK1_BYTE1_SHIFT \
16
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_OB_DDLL_LONG_DQ_RANK1_BYTE1_MASK \
0x3ff << \
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_OB_DDLL_LONG_DQ_RANK1_BYTE1_SHIFT
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_OB_DDLL_LONG_DQ_RANK1_BYTE0_SHIFT \
0
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_OB_DDLL_LONG_DQ_RANK1_BYTE0_MASK \
0x3ff << \
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_OB_DDLL_LONG_DQ_RANK1_BYTE0_SHIFT
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1 0x664 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1 0x664
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_OB_DDLL_LONG_DQ_RANK1_BYTE3_SHIFT \
16
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_OB_DDLL_LONG_DQ_RANK1_BYTE3_MASK \
0x3ff << \
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_OB_DDLL_LONG_DQ_RANK1_BYTE3_SHIFT
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_OB_DDLL_LONG_DQ_RANK1_BYTE2_SHIFT \
0
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_OB_DDLL_LONG_DQ_RANK1_BYTE2_MASK \
0x3ff << \
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_OB_DDLL_LONG_DQ_RANK1_BYTE2_SHIFT
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2 0x668 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2 0x668
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_OB_DDLL_LONG_DQ_RANK1_BYTE5_SHIFT \
16
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_OB_DDLL_LONG_DQ_RANK1_BYTE5_MASK \
0x3ff << \
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_OB_DDLL_LONG_DQ_RANK1_BYTE5_SHIFT
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_OB_DDLL_LONG_DQ_RANK1_BYTE4_SHIFT \
0
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_OB_DDLL_LONG_DQ_RANK1_BYTE4_MASK \
0x3ff << \
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_OB_DDLL_LONG_DQ_RANK1_BYTE4_SHIFT
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3 0x66c #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3 0x66c
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_OB_DDLL_LONG_DQ_RANK1_BYTE7_SHIFT \
16
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_OB_DDLL_LONG_DQ_RANK1_BYTE7_MASK \
0x3ff << \
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_OB_DDLL_LONG_DQ_RANK1_BYTE7_SHIFT
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_OB_DDLL_LONG_DQ_RANK1_BYTE6_SHIFT \
0
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_OB_DDLL_LONG_DQ_RANK1_BYTE6_MASK \
0x3ff << \
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_OB_DDLL_LONG_DQ_RANK1_BYTE6_SHIFT
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4 0x670 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4 0x670
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5 0x674 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5 0x674
#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0 0x680 #define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0 0x680
@ -640,17 +1009,62 @@
#define EMC_PMACRO_DDLL_SHORT_CMD_1 0xc24 #define EMC_PMACRO_DDLL_SHORT_CMD_1 0xc24
#define EMC_PMACRO_DDLL_SHORT_CMD_2 0xc28 #define EMC_PMACRO_DDLL_SHORT_CMD_2 0xc28
#define EMC_PMACRO_CFG_PM_GLOBAL_0 0xc30 #define EMC_PMACRO_CFG_PM_GLOBAL_0 0xc30
#define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE0 (1 << 16)
#define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE1 (1 << 17)
#define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE2 (1 << 18)
#define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE3 (1 << 19)
#define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE4 (1 << 20)
#define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE5 (1 << 21)
#define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE6 (1 << 22)
#define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE7 (1 << 23)
#define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_CMD0 (1 << 24)
#define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_CMD1 (1 << 25)
#define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_CMD2 (1 << 26)
#define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_CMD3 (1 << 27)
#define EMC_PMACRO_VTTGEN_CTRL_0 0xc34 #define EMC_PMACRO_VTTGEN_CTRL_0 0xc34
#define EMC_PMACRO_VTTGEN_CTRL_1 0xc38 #define EMC_PMACRO_VTTGEN_CTRL_1 0xc38
#define EMC_PMACRO_VTTGEN_CTRL_2 0xcf0 #define EMC_PMACRO_VTTGEN_CTRL_2 0xcf0
#define EMC_PMACRO_BG_BIAS_CTRL_0 0xc3c #define EMC_PMACRO_BG_BIAS_CTRL_0 0xc3c
#define EMC_PMACRO_BG_BIAS_CTRL_0_BG_E_PWRD (1 << 0)
#define EMC_PMACRO_BG_BIAS_CTRL_0_BG_MODE (1 << 1)
#define EMC_PMACRO_BG_BIAS_CTRL_0_BGLP_E_PWRD (1 << 2)
#define EMC_PMACRO_PAD_CFG_CTRL 0xc40 #define EMC_PMACRO_PAD_CFG_CTRL 0xc40
#define EMC_PMACRO_CMD_PAD_RX_CTRL 0xc50 #define EMC_PMACRO_CMD_PAD_RX_CTRL 0xc50
#define EMC_PMACRO_DATA_PAD_RX_CTRL 0xc54 #define EMC_PMACRO_DATA_PAD_RX_CTRL 0xc54
#define EMC_PMACRO_CMD_RX_TERM_MODE 0xc58 #define EMC_PMACRO_CMD_RX_TERM_MODE 0xc58
#define EMC_PMACRO_DATA_RX_TERM_MODE 0xc5c #define EMC_PMACRO_DATA_RX_TERM_MODE 0xc5c
#define EMC_PMACRO_DATA_RX_TERM_MODE_DATA_DQSN_RX_TERM_MODE_SHIFT 8
#define EMC_PMACRO_DATA_RX_TERM_MODE_DATA_DQSN_RX_TERM_MODE_MASK (0x3 << \
EMC_PMACRO_DATA_RX_TERM_MODE_DATA_DQSN_RX_TERM_MODE_SHIFT)
#define EMC_PMACRO_DATA_RX_TERM_MODE_DATA_DQSP_RX_TERM_MODE_SHIFT 4
#define EMC_PMACRO_DATA_RX_TERM_MODE_DATA_DQSP_RX_TERM_MODE_MASK (0x3 << \
EMC_PMACRO_DATA_RX_TERM_MODE_DATA_DQSP_RX_TERM_MODE_SHIFT)
#define EMC_PMACRO_DATA_RX_TERM_MODE_DATA_DQ_RX_TERM_MODE_SHIFT 0
#define EMC_PMACRO_DATA_RX_TERM_MODE_DATA_DQ_RX_TERM_MODE_MASK (0x3 << \
EMC_PMACRO_DATA_RX_TERM_MODE_DATA_DQ_RX_TERM_MODE_SHIFT)
#define RX_TERM_MODE \
~(EMC_PMACRO_DATA_RX_TERM_MODE_DATA_DQSN_RX_TERM_MODE_MASK | \
EMC_PMACRO_DATA_RX_TERM_MODE_DATA_DQSP_RX_TERM_MODE_MASK | \
EMC_PMACRO_DATA_RX_TERM_MODE_DATA_DQ_RX_TERM_MODE_MASK)
#define EMC_PMACRO_CMD_PAD_TX_CTRL 0xc60 #define EMC_PMACRO_CMD_PAD_TX_CTRL 0xc60
#define EMC_PMACRO_CMD_PAD_TX_CTRL_CMD_DQ_TX_E_DCC (1 << 1)
#define EMC_PMACRO_CMD_PAD_TX_CTRL_CMD_DQSP_TX_E_DCC (1 << 9)
#define EMC_PMACRO_CMD_PAD_TX_CTRL_CMD_DQSN_TX_E_DCC (1 << 16)
#define EMC_PMACRO_CMD_PAD_TX_CTRL_CMD_CMD_TX_E_DCC (1 << 24)
#define EMC_PMACRO_CMD_PAD_TX_CTRL_CMD_DQ_TX_DRVFORCEON (1 << 26)
#define EMC_PMACRO_DATA_PAD_TX_CTRL 0xc64 #define EMC_PMACRO_DATA_PAD_TX_CTRL 0xc64
#define EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQ_E_IVREF (1 << 0)
#define EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQ_TX_E_DCC (1 << 1)
#define EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQS_E_IVREF (1 << 8)
#define EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQSP_TX_E_DCC (1 << 9)
#define EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQSN_TX_E_DCC (1 << 16)
#define EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_CMD_TX_E_DCC (1 << 24)
#define EMC_PMACRO_COMMON_PAD_TX_CTRL 0xc68 #define EMC_PMACRO_COMMON_PAD_TX_CTRL 0xc68
#define EMC_PMACRO_BRICK_MAPPING_0 0xc80 #define EMC_PMACRO_BRICK_MAPPING_0 0xc80
#define EMC_PMACRO_BRICK_MAPPING_1 0xc84 #define EMC_PMACRO_BRICK_MAPPING_1 0xc84
@ -663,7 +1077,11 @@
#define EMC_PMACRO_CMD_BRICK_CTRL_FDPD 0x318 #define EMC_PMACRO_CMD_BRICK_CTRL_FDPD 0x318
#define EMC_PMACRO_DATA_BRICK_CTRL_FDPD 0x31c #define EMC_PMACRO_DATA_BRICK_CTRL_FDPD 0x31c
#define EMC_PMACRO_TRAINING_CTRL_0 0xcf8 #define EMC_PMACRO_TRAINING_CTRL_0 0xcf8
#define EMC_PMACRO_TRAINING_CTRL_0_CH0_TRAINING_E_WRPTR (1 << 3)
#define EMC_PMACRO_TRAINING_CTRL_1 0xcfc #define EMC_PMACRO_TRAINING_CTRL_1 0xcfc
#define EMC_PMACRO_TRAINING_CTRL_1_CH1_TRAINING_E_WRPTR (1 << 3)
#define EMC_PMC_SCRATCH1 0x440 #define EMC_PMC_SCRATCH1 0x440
#define EMC_PMC_SCRATCH2 0x444 #define EMC_PMC_SCRATCH2 0x444
#define EMC_PMC_SCRATCH3 0x448 #define EMC_PMC_SCRATCH3 0x448

File diff suppressed because it is too large Load diff

View file

@ -26,6 +26,7 @@
#include "loader.h" #include "loader.h"
#include "chainloader.h" #include "chainloader.h"
#include "stage2.h" #include "stage2.h"
#include "mtc.h"
#include "nxboot.h" #include "nxboot.h"
#include "console.h" #include "console.h"
#include "fs_utils.h" #include "fs_utils.h"
@ -52,6 +53,9 @@ static void setup_env(void) {
if (nxfs_mount_all() < 0) { if (nxfs_mount_all() < 0) {
fatal_error("Failed to mount at least one parition: %s\n", strerror(errno)); fatal_error("Failed to mount at least one parition: %s\n", strerror(errno));
} }
/* Train DRAM. */
train_dram();
} }
static void cleanup_env(void) { static void cleanup_env(void) {

File diff suppressed because it is too large Load diff

View file

@ -0,0 +1,759 @@
/*
* Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2018 CTCaer <ctcaer@gmail.com>
* Copyright (c) 2018 Atmosphère-NX
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef FUSEE_MTC_H_
#define FUSEE_MTC_H_
#include <stdint.h>
#include <stdbool.h>
#include "emc.h"
#include "mc.h"
#define MTC_TABLES_MAX_ENTRIES 10
#define MAX_PLL_CFGS 14
#define DVFS_FGCG_HIGH_SPEED_THRESHOLD 1000
#define IOBRICK_DCC_THRESHOLD 2400
#define DVFS_FGCG_MID_SPEED_THRESHOLD 600
#define TEGRA21_MAX_TABLE_ID_LEN 50
#define TEGRA_EMC_ISO_USE_FREQ_MAX_NUM 12
#define PLL_C_DIRECT_FLOOR 333500000
#define EMC_STATUS_UPDATE_TIMEOUT 1000
#define TEGRA_EMC_DEFAULT_CLK_LATENCY_US 2000
#define TEGRA_EMC_MODE_REG_17 0x00110000
#define TEGRA_EMC_MRW_DEV_SHIFT 30
#define TEGRA_EMC_MRW_DEV1 2
#define TEGRA_EMC_MRW_DEV2 1
#define EMC_CLK_EMC_2X_CLK_SRC_SHIFT 29
#define EMC_CLK_EMC_2X_CLK_SRC_MASK \
(0x7 << EMC_CLK_EMC_2X_CLK_SRC_SHIFT)
#define EMC_CLK_EMC_2X_CLK_DIVISOR_SHIFT 0
#define EMC_CLK_EMC_2X_CLK_DIVISOR_MASK \
(0xff << EMC_CLK_EMC_2X_CLK_DIVISOR_SHIFT)
enum {
REG_MC,
REG_EMC,
REG_EMC0,
REG_EMC1,
};
#define BURST_REGS_PER_CH_LIST \
{ \
DEFINE_REG(REG_EMC0, EMC_MRW10), \
DEFINE_REG(REG_EMC1, EMC_MRW10), \
DEFINE_REG(REG_EMC0, EMC_MRW11), \
DEFINE_REG(REG_EMC1, EMC_MRW11), \
DEFINE_REG(REG_EMC0, EMC_MRW12), \
DEFINE_REG(REG_EMC1, EMC_MRW12), \
DEFINE_REG(REG_EMC0, EMC_MRW13), \
DEFINE_REG(REG_EMC1, EMC_MRW13), \
}
#define BURST_REGS_LIST \
{ \
DEFINE_REG(REG_EMC, EMC_RC), \
DEFINE_REG(REG_EMC, EMC_RFC), \
DEFINE_REG(REG_EMC, EMC_RFCPB), \
DEFINE_REG(REG_EMC, EMC_REFCTRL2), \
DEFINE_REG(REG_EMC, EMC_RFC_SLR), \
DEFINE_REG(REG_EMC, EMC_RAS), \
DEFINE_REG(REG_EMC, EMC_RP), \
DEFINE_REG(REG_EMC, EMC_R2W), \
DEFINE_REG(REG_EMC, EMC_W2R), \
DEFINE_REG(REG_EMC, EMC_R2P), \
DEFINE_REG(REG_EMC, EMC_W2P), \
DEFINE_REG(REG_EMC, EMC_R2R), \
DEFINE_REG(REG_EMC, EMC_TPPD), \
DEFINE_REG(REG_EMC, EMC_CCDMW), \
DEFINE_REG(REG_EMC, EMC_RD_RCD), \
DEFINE_REG(REG_EMC, EMC_WR_RCD), \
DEFINE_REG(REG_EMC, EMC_RRD), \
DEFINE_REG(REG_EMC, EMC_REXT), \
DEFINE_REG(REG_EMC, EMC_WEXT), \
DEFINE_REG(REG_EMC, EMC_WDV_CHK), \
DEFINE_REG(REG_EMC, EMC_WDV), \
DEFINE_REG(REG_EMC, EMC_WSV), \
DEFINE_REG(REG_EMC, EMC_WEV), \
DEFINE_REG(REG_EMC, EMC_WDV_MASK), \
DEFINE_REG(REG_EMC, EMC_WS_DURATION), \
DEFINE_REG(REG_EMC, EMC_WE_DURATION), \
DEFINE_REG(REG_EMC, EMC_QUSE), \
DEFINE_REG(REG_EMC, EMC_QUSE_WIDTH), \
DEFINE_REG(REG_EMC, EMC_IBDLY), \
DEFINE_REG(REG_EMC, EMC_OBDLY), \
DEFINE_REG(REG_EMC, EMC_EINPUT), \
DEFINE_REG(REG_EMC, EMC_MRW6), \
DEFINE_REG(REG_EMC, EMC_EINPUT_DURATION), \
DEFINE_REG(REG_EMC, EMC_PUTERM_EXTRA), \
DEFINE_REG(REG_EMC, EMC_PUTERM_WIDTH), \
DEFINE_REG(REG_EMC, EMC_QRST), \
DEFINE_REG(REG_EMC, EMC_QSAFE), \
DEFINE_REG(REG_EMC, EMC_RDV), \
DEFINE_REG(REG_EMC, EMC_RDV_MASK), \
DEFINE_REG(REG_EMC, EMC_RDV_EARLY), \
DEFINE_REG(REG_EMC, EMC_RDV_EARLY_MASK), \
DEFINE_REG(REG_EMC, EMC_REFRESH), \
DEFINE_REG(REG_EMC, EMC_BURST_REFRESH_NUM), \
DEFINE_REG(REG_EMC, EMC_PRE_REFRESH_REQ_CNT), \
DEFINE_REG(REG_EMC, EMC_PDEX2WR), \
DEFINE_REG(REG_EMC, EMC_PDEX2RD), \
DEFINE_REG(REG_EMC, EMC_PCHG2PDEN), \
DEFINE_REG(REG_EMC, EMC_ACT2PDEN), \
DEFINE_REG(REG_EMC, EMC_AR2PDEN), \
DEFINE_REG(REG_EMC, EMC_RW2PDEN), \
DEFINE_REG(REG_EMC, EMC_CKE2PDEN), \
DEFINE_REG(REG_EMC, EMC_PDEX2CKE), \
DEFINE_REG(REG_EMC, EMC_PDEX2MRR), \
DEFINE_REG(REG_EMC, EMC_TXSR), \
DEFINE_REG(REG_EMC, EMC_TXSRDLL), \
DEFINE_REG(REG_EMC, EMC_TCKE), \
DEFINE_REG(REG_EMC, EMC_TCKESR), \
DEFINE_REG(REG_EMC, EMC_TPD), \
DEFINE_REG(REG_EMC, EMC_TFAW), \
DEFINE_REG(REG_EMC, EMC_TRPAB), \
DEFINE_REG(REG_EMC, EMC_TCLKSTABLE), \
DEFINE_REG(REG_EMC, EMC_TCLKSTOP), \
DEFINE_REG(REG_EMC, EMC_MRW7), \
DEFINE_REG(REG_EMC, EMC_TREFBW), \
DEFINE_REG(REG_EMC, EMC_ODT_WRITE), \
DEFINE_REG(REG_EMC, EMC_FBIO_CFG5), \
DEFINE_REG(REG_EMC, EMC_FBIO_CFG7), \
DEFINE_REG(REG_EMC, EMC_CFG_DIG_DLL), \
DEFINE_REG(REG_EMC, EMC_CFG_DIG_DLL_PERIOD), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_RXRT), \
DEFINE_REG(REG_EMC, EMC_CFG_PIPE_1), \
DEFINE_REG(REG_EMC, EMC_CFG_PIPE_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_QUSE_DDLL_RANK0_4), \
DEFINE_REG(REG_EMC, EMC_PMACRO_QUSE_DDLL_RANK0_5), \
DEFINE_REG(REG_EMC, EMC_PMACRO_QUSE_DDLL_RANK1_4), \
DEFINE_REG(REG_EMC, EMC_PMACRO_QUSE_DDLL_RANK1_5), \
DEFINE_REG(REG_EMC, EMC_MRW8), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5), \
DEFINE_REG(REG_EMC, EMC_PMACRO_DDLL_LONG_CMD_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_DDLL_LONG_CMD_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_DDLL_LONG_CMD_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_DDLL_LONG_CMD_3), \
DEFINE_REG(REG_EMC, EMC_PMACRO_DDLL_LONG_CMD_4), \
DEFINE_REG(REG_EMC, EMC_PMACRO_DDLL_SHORT_CMD_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_DDLL_SHORT_CMD_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_DDLL_SHORT_CMD_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3), \
DEFINE_REG(REG_EMC, EMC_TXDSRVTTGEN), \
DEFINE_REG(REG_EMC, EMC_FDPD_CTRL_DQ), \
DEFINE_REG(REG_EMC, EMC_FDPD_CTRL_CMD), \
DEFINE_REG(REG_EMC, EMC_FBIO_SPARE), \
DEFINE_REG(REG_EMC, EMC_ZCAL_INTERVAL), \
DEFINE_REG(REG_EMC, EMC_ZCAL_WAIT_CNT), \
DEFINE_REG(REG_EMC, EMC_MRS_WAIT_CNT), \
DEFINE_REG(REG_EMC, EMC_MRS_WAIT_CNT2), \
DEFINE_REG(REG_EMC, EMC_AUTO_CAL_CHANNEL), \
DEFINE_REG(REG_EMC, EMC_DLL_CFG_0), \
DEFINE_REG(REG_EMC, EMC_DLL_CFG_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_AUTOCAL_CFG_COMMON), \
DEFINE_REG(REG_EMC, EMC_PMACRO_ZCTRL), \
DEFINE_REG(REG_EMC, EMC_CFG), \
DEFINE_REG(REG_EMC, EMC_CFG_PIPE), \
DEFINE_REG(REG_EMC, EMC_DYN_SELF_REF_CONTROL), \
DEFINE_REG(REG_EMC, EMC_QPOP), \
DEFINE_REG(REG_EMC, EMC_DQS_BRLSHFT_0), \
DEFINE_REG(REG_EMC, EMC_DQS_BRLSHFT_1), \
DEFINE_REG(REG_EMC, EMC_CMD_BRLSHFT_2), \
DEFINE_REG(REG_EMC, EMC_CMD_BRLSHFT_3), \
DEFINE_REG(REG_EMC, EMC_PMACRO_PAD_CFG_CTRL), \
DEFINE_REG(REG_EMC, EMC_PMACRO_DATA_PAD_RX_CTRL), \
DEFINE_REG(REG_EMC, EMC_PMACRO_CMD_PAD_RX_CTRL), \
DEFINE_REG(REG_EMC, EMC_PMACRO_DATA_RX_TERM_MODE), \
DEFINE_REG(REG_EMC, EMC_PMACRO_CMD_RX_TERM_MODE), \
DEFINE_REG(REG_EMC, EMC_PMACRO_CMD_PAD_TX_CTRL), \
DEFINE_REG(REG_EMC, EMC_PMACRO_DATA_PAD_TX_CTRL), \
DEFINE_REG(REG_EMC, EMC_PMACRO_COMMON_PAD_TX_CTRL), \
DEFINE_REG(REG_EMC, EMC_PMACRO_VTTGEN_CTRL_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_VTTGEN_CTRL_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_VTTGEN_CTRL_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_BRICK_CTRL_RFU1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_CMD_BRICK_CTRL_FDPD), \
DEFINE_REG(REG_EMC, EMC_PMACRO_BRICK_CTRL_RFU2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_DATA_BRICK_CTRL_FDPD), \
DEFINE_REG(REG_EMC, EMC_PMACRO_BG_BIAS_CTRL_0), \
DEFINE_REG(REG_EMC, EMC_CFG_3), \
DEFINE_REG(REG_EMC, EMC_PMACRO_TX_PWRD_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_TX_PWRD_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_TX_PWRD_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_TX_PWRD_3), \
DEFINE_REG(REG_EMC, EMC_PMACRO_TX_PWRD_4), \
DEFINE_REG(REG_EMC, EMC_PMACRO_TX_PWRD_5), \
DEFINE_REG(REG_EMC, EMC_CONFIG_SAMPLE_DELAY), \
DEFINE_REG(REG_EMC, EMC_PMACRO_TX_SEL_CLK_SRC_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_TX_SEL_CLK_SRC_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_TX_SEL_CLK_SRC_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_TX_SEL_CLK_SRC_3), \
DEFINE_REG(REG_EMC, EMC_PMACRO_TX_SEL_CLK_SRC_4), \
DEFINE_REG(REG_EMC, EMC_PMACRO_TX_SEL_CLK_SRC_5), \
DEFINE_REG(REG_EMC, EMC_PMACRO_DDLL_BYPASS), \
DEFINE_REG(REG_EMC, EMC_PMACRO_DDLL_PWRD_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_DDLL_PWRD_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_DDLL_PWRD_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_CMD_CTRL_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_CMD_CTRL_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_CMD_CTRL_2), \
DEFINE_REG(REG_EMC, EMC_TR_TIMING_0), \
DEFINE_REG(REG_EMC, EMC_TR_DVFS), \
DEFINE_REG(REG_EMC, EMC_TR_CTRL_1), \
DEFINE_REG(REG_EMC, EMC_TR_RDV), \
DEFINE_REG(REG_EMC, EMC_TR_QPOP), \
DEFINE_REG(REG_EMC, EMC_TR_RDV_MASK), \
DEFINE_REG(REG_EMC, EMC_MRW14), \
DEFINE_REG(REG_EMC, EMC_TR_QSAFE), \
DEFINE_REG(REG_EMC, EMC_TR_QRST), \
DEFINE_REG(REG_EMC, EMC_TRAINING_CTRL), \
DEFINE_REG(REG_EMC, EMC_TRAINING_SETTLE), \
DEFINE_REG(REG_EMC, EMC_TRAINING_VREF_SETTLE), \
DEFINE_REG(REG_EMC, EMC_TRAINING_CA_FINE_CTRL), \
DEFINE_REG(REG_EMC, EMC_TRAINING_CA_CTRL_MISC), \
DEFINE_REG(REG_EMC, EMC_TRAINING_CA_CTRL_MISC1), \
DEFINE_REG(REG_EMC, EMC_TRAINING_CA_VREF_CTRL), \
DEFINE_REG(REG_EMC, EMC_TRAINING_QUSE_CORS_CTRL), \
DEFINE_REG(REG_EMC, EMC_TRAINING_QUSE_FINE_CTRL), \
DEFINE_REG(REG_EMC, EMC_TRAINING_QUSE_CTRL_MISC), \
DEFINE_REG(REG_EMC, EMC_TRAINING_QUSE_VREF_CTRL), \
DEFINE_REG(REG_EMC, EMC_TRAINING_READ_FINE_CTRL), \
DEFINE_REG(REG_EMC, EMC_TRAINING_READ_CTRL_MISC), \
DEFINE_REG(REG_EMC, EMC_TRAINING_READ_VREF_CTRL), \
DEFINE_REG(REG_EMC, EMC_TRAINING_WRITE_FINE_CTRL), \
DEFINE_REG(REG_EMC, EMC_TRAINING_WRITE_CTRL_MISC), \
DEFINE_REG(REG_EMC, EMC_TRAINING_WRITE_VREF_CTRL), \
DEFINE_REG(REG_EMC, EMC_TRAINING_MPC), \
DEFINE_REG(REG_EMC, EMC_MRW15), \
}
#define TRIM_REGS_PER_CH_LIST \
{ \
DEFINE_REG(REG_EMC0, EMC_CMD_BRLSHFT_0), \
DEFINE_REG(REG_EMC1, EMC_CMD_BRLSHFT_1), \
DEFINE_REG(REG_EMC0, EMC_DATA_BRLSHFT_0), \
DEFINE_REG(REG_EMC1, EMC_DATA_BRLSHFT_0), \
DEFINE_REG(REG_EMC0, EMC_DATA_BRLSHFT_1), \
DEFINE_REG(REG_EMC1, EMC_DATA_BRLSHFT_1), \
DEFINE_REG(REG_EMC0, EMC_QUSE_BRLSHFT_0), \
DEFINE_REG(REG_EMC1, EMC_QUSE_BRLSHFT_1), \
DEFINE_REG(REG_EMC0, EMC_QUSE_BRLSHFT_2), \
DEFINE_REG(REG_EMC1, EMC_QUSE_BRLSHFT_3), \
}
#define TRIM_REGS_LIST \
{ \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_VREF_DQS_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_VREF_DQS_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_VREF_DQ_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_VREF_DQ_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_QUSE_DDLL_RANK0_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_QUSE_DDLL_RANK0_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_QUSE_DDLL_RANK0_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_QUSE_DDLL_RANK0_3), \
DEFINE_REG(REG_EMC, EMC_PMACRO_QUSE_DDLL_RANK1_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_QUSE_DDLL_RANK1_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_QUSE_DDLL_RANK1_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_QUSE_DDLL_RANK1_3), \
}
#define VREF_REGS_PER_CH_LIST \
{ \
DEFINE_REG(REG_EMC0, EMC_TRAINING_OPT_DQS_IB_VREF_RANK0), \
DEFINE_REG(REG_EMC1, EMC_TRAINING_OPT_DQS_IB_VREF_RANK0), \
DEFINE_REG(REG_EMC0, EMC_TRAINING_OPT_DQS_IB_VREF_RANK1), \
DEFINE_REG(REG_EMC1, EMC_TRAINING_OPT_DQS_IB_VREF_RANK1), \
}
#define TRAINING_MOD_REGS_PER_CH_LIST \
{ \
DEFINE_REG(REG_EMC0, EMC_TRAINING_RW_OFFSET_IB_BYTE0), \
DEFINE_REG(REG_EMC1, EMC_TRAINING_RW_OFFSET_IB_BYTE0), \
DEFINE_REG(REG_EMC0, EMC_TRAINING_RW_OFFSET_IB_BYTE1), \
DEFINE_REG(REG_EMC1, EMC_TRAINING_RW_OFFSET_IB_BYTE1), \
DEFINE_REG(REG_EMC0, EMC_TRAINING_RW_OFFSET_IB_BYTE2), \
DEFINE_REG(REG_EMC1, EMC_TRAINING_RW_OFFSET_IB_BYTE2), \
DEFINE_REG(REG_EMC0, EMC_TRAINING_RW_OFFSET_IB_BYTE3), \
DEFINE_REG(REG_EMC1, EMC_TRAINING_RW_OFFSET_IB_BYTE3), \
DEFINE_REG(REG_EMC0, EMC_TRAINING_RW_OFFSET_IB_MISC), \
DEFINE_REG(REG_EMC1, EMC_TRAINING_RW_OFFSET_IB_MISC), \
DEFINE_REG(REG_EMC0, EMC_TRAINING_RW_OFFSET_OB_BYTE0), \
DEFINE_REG(REG_EMC1, EMC_TRAINING_RW_OFFSET_OB_BYTE0), \
DEFINE_REG(REG_EMC0, EMC_TRAINING_RW_OFFSET_OB_BYTE1), \
DEFINE_REG(REG_EMC1, EMC_TRAINING_RW_OFFSET_OB_BYTE1), \
DEFINE_REG(REG_EMC0, EMC_TRAINING_RW_OFFSET_OB_BYTE2), \
DEFINE_REG(REG_EMC1, EMC_TRAINING_RW_OFFSET_OB_BYTE2), \
DEFINE_REG(REG_EMC0, EMC_TRAINING_RW_OFFSET_OB_BYTE3), \
DEFINE_REG(REG_EMC1, EMC_TRAINING_RW_OFFSET_OB_BYTE3), \
DEFINE_REG(REG_EMC0, EMC_TRAINING_RW_OFFSET_OB_MISC), \
DEFINE_REG(REG_EMC1, EMC_TRAINING_RW_OFFSET_OB_MISC), \
}
#define BURST_MC_REGS_LIST \
{ \
DEFINE_REG(REG_MC, MC_EMEM_ARB_CFG), \
DEFINE_REG(REG_MC, MC_EMEM_ARB_OUTSTANDING_REQ), \
DEFINE_REG(REG_MC, MC_EMEM_ARB_REFPB_HP_CTRL), \
DEFINE_REG(REG_MC, MC_EMEM_ARB_REFPB_BANK_CTRL), \
DEFINE_REG(REG_MC, MC_EMEM_ARB_TIMING_RCD), \
DEFINE_REG(REG_MC, MC_EMEM_ARB_TIMING_RP), \
DEFINE_REG(REG_MC, MC_EMEM_ARB_TIMING_RC), \
DEFINE_REG(REG_MC, MC_EMEM_ARB_TIMING_RAS), \
DEFINE_REG(REG_MC, MC_EMEM_ARB_TIMING_FAW), \
DEFINE_REG(REG_MC, MC_EMEM_ARB_TIMING_RRD), \
DEFINE_REG(REG_MC, MC_EMEM_ARB_TIMING_RAP2PRE), \
DEFINE_REG(REG_MC, MC_EMEM_ARB_TIMING_WAP2PRE), \
DEFINE_REG(REG_MC, MC_EMEM_ARB_TIMING_R2R), \
DEFINE_REG(REG_MC, MC_EMEM_ARB_TIMING_W2W), \
DEFINE_REG(REG_MC, MC_EMEM_ARB_TIMING_R2W), \
DEFINE_REG(REG_MC, MC_EMEM_ARB_TIMING_CCDMW), \
DEFINE_REG(REG_MC, MC_EMEM_ARB_TIMING_W2R), \
DEFINE_REG(REG_MC, MC_EMEM_ARB_TIMING_RFCPB), \
DEFINE_REG(REG_MC, MC_EMEM_ARB_DA_TURNS), \
DEFINE_REG(REG_MC, MC_EMEM_ARB_DA_COVERS), \
DEFINE_REG(REG_MC, MC_EMEM_ARB_MISC0), \
DEFINE_REG(REG_MC, MC_EMEM_ARB_MISC1), \
DEFINE_REG(REG_MC, MC_EMEM_ARB_MISC2), \
DEFINE_REG(REG_MC, MC_EMEM_ARB_RING1_THROTTLE), \
DEFINE_REG(REG_MC, MC_EMEM_ARB_DHYST_CTRL), \
DEFINE_REG(REG_MC, MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0), \
DEFINE_REG(REG_MC, MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1), \
DEFINE_REG(REG_MC, MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2), \
DEFINE_REG(REG_MC, MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3), \
DEFINE_REG(REG_MC, MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4), \
DEFINE_REG(REG_MC, MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5), \
DEFINE_REG(REG_MC, MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6), \
DEFINE_REG(REG_MC, MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7), \
}
#define BURST_UP_DOWN_REGS_LIST \
{ \
DEFINE_REG(REG_MC, MC_MLL_MPCORER_PTSA_RATE), \
DEFINE_REG(REG_MC, MC_FTOP_PTSA_RATE), \
DEFINE_REG(REG_MC, MC_PTSA_GRANT_DECREMENT), \
DEFINE_REG(REG_MC, MC_LATENCY_ALLOWANCE_XUSB_0), \
DEFINE_REG(REG_MC, MC_LATENCY_ALLOWANCE_XUSB_1), \
DEFINE_REG(REG_MC, MC_LATENCY_ALLOWANCE_TSEC_0), \
DEFINE_REG(REG_MC, MC_LATENCY_ALLOWANCE_SDMMCA_0), \
DEFINE_REG(REG_MC, MC_LATENCY_ALLOWANCE_SDMMCAA_0), \
DEFINE_REG(REG_MC, MC_LATENCY_ALLOWANCE_SDMMC_0), \
DEFINE_REG(REG_MC, MC_LATENCY_ALLOWANCE_SDMMCAB_0), \
DEFINE_REG(REG_MC, MC_LATENCY_ALLOWANCE_PPCS_0), \
DEFINE_REG(REG_MC, MC_LATENCY_ALLOWANCE_PPCS_1), \
DEFINE_REG(REG_MC, MC_LATENCY_ALLOWANCE_MPCORE_0), \
DEFINE_REG(REG_MC, MC_LATENCY_ALLOWANCE_HC_0), \
DEFINE_REG(REG_MC, MC_LATENCY_ALLOWANCE_HC_1), \
DEFINE_REG(REG_MC, MC_LATENCY_ALLOWANCE_AVPC_0), \
DEFINE_REG(REG_MC, MC_LATENCY_ALLOWANCE_GPU_0), \
DEFINE_REG(REG_MC, MC_LATENCY_ALLOWANCE_GPU2_0), \
DEFINE_REG(REG_MC, MC_LATENCY_ALLOWANCE_NVENC_0), \
DEFINE_REG(REG_MC, MC_LATENCY_ALLOWANCE_NVDEC_0), \
DEFINE_REG(REG_MC, MC_LATENCY_ALLOWANCE_VIC_0), \
DEFINE_REG(REG_MC, MC_LATENCY_ALLOWANCE_VI2_0), \
DEFINE_REG(REG_MC, MC_LATENCY_ALLOWANCE_ISP2_0), \
DEFINE_REG(REG_MC, MC_LATENCY_ALLOWANCE_ISP2_1), \
}
#define DEFINE_REG(type, reg) reg##_INDEX
enum BURST_REGS_LIST;
enum TRIM_REGS_LIST;
enum BURST_MC_REGS_LIST;
enum BURST_UP_DOWN_REGS_LIST;
#undef DEFINE_REG
#define DEFINE_REG(type, reg) type##_##reg##_INDEX
enum BURST_REGS_PER_CH_LIST;
enum TRIM_REGS_PER_CH_LIST;
enum VREF_REGS_PER_CH_LIST;
enum TRAINING_MOD_REGS_PER_CH_LIST;
#undef DEFINE_REG
typedef struct {
uint32_t rev;
char dvfs_ver[60];
uint32_t rate;
uint32_t min_volt;
uint32_t gpu_min_volt;
char clock_src[32];
uint32_t clk_src_emc;
uint32_t needs_training;
uint32_t training_pattern;
uint32_t trained;
uint32_t periodic_training;
uint32_t trained_dram_clktree_c0d0u0;
uint32_t trained_dram_clktree_c0d0u1;
uint32_t trained_dram_clktree_c0d1u0;
uint32_t trained_dram_clktree_c0d1u1;
uint32_t trained_dram_clktree_c1d0u0;
uint32_t trained_dram_clktree_c1d0u1;
uint32_t trained_dram_clktree_c1d1u0;
uint32_t trained_dram_clktree_c1d1u1;
uint32_t current_dram_clktree_c0d0u0;
uint32_t current_dram_clktree_c0d0u1;
uint32_t current_dram_clktree_c0d1u0;
uint32_t current_dram_clktree_c0d1u1;
uint32_t current_dram_clktree_c1d0u0;
uint32_t current_dram_clktree_c1d0u1;
uint32_t current_dram_clktree_c1d1u0;
uint32_t current_dram_clktree_c1d1u1;
uint32_t run_clocks;
uint32_t tree_margin;
uint32_t num_burst;
uint32_t num_burst_per_ch;
uint32_t num_trim;
uint32_t num_trim_per_ch;
uint32_t num_mc_regs;
uint32_t num_up_down;
uint32_t vref_num;
uint32_t training_mod_num;
uint32_t dram_timing_num;
uint32_t ptfv_list[12];
uint32_t burst_regs[221];
uint32_t burst_reg_per_ch[8];
uint32_t shadow_regs_ca_train[221];
uint32_t shadow_regs_quse_train[221];
uint32_t shadow_regs_rdwr_train[221];
uint32_t trim_regs[138];
uint32_t trim_perch_regs[10];
uint32_t vref_perch_regs[4];
uint32_t dram_timings[5];
uint32_t training_mod_regs[20];
uint32_t save_restore_mod_regs[12];
uint32_t burst_mc_regs[33];
uint32_t la_scale_regs[24];
uint32_t min_mrs_wait;
uint32_t emc_mrw;
uint32_t emc_mrw2;
uint32_t emc_mrw3;
uint32_t emc_mrw4;
uint32_t emc_mrw9;
uint32_t emc_mrs;
uint32_t emc_emrs;
uint32_t emc_emrs2;
uint32_t emc_auto_cal_config;
uint32_t emc_auto_cal_config2;
uint32_t emc_auto_cal_config3;
uint32_t emc_auto_cal_config4;
uint32_t emc_auto_cal_config5;
uint32_t emc_auto_cal_config6;
uint32_t emc_auto_cal_config7;
uint32_t emc_auto_cal_config8;
uint32_t emc_cfg_2;
uint32_t emc_sel_dpd_ctrl;
uint32_t emc_fdpd_ctrl_cmd_no_ramp;
uint32_t dll_clk_src;
uint32_t clk_out_enb_x_0_clk_enb_emc_dll;
uint32_t latency;
} tegra_emc_timing_t;
typedef struct {
uint32_t osc_freq;
uint32_t out_freq;
uint32_t feedback_div;
uint32_t input_div;
uint32_t post_div;
} pll_cfg_t;
typedef enum {
OP_SWITCH = 0,
OP_TRAIN = 1,
OP_TRAIN_SWITCH = 2
} TrainMode;
typedef enum {
TEGRA_EMC_SRC_PLLM,
TEGRA_EMC_SRC_PLLC,
TEGRA_EMC_SRC_PLLP,
TEGRA_EMC_SRC_CLKM,
TEGRA_EMC_SRC_PLLM_UD,
TEGRA_EMC_SRC_PLLMB_UD,
TEGRA_EMC_SRC_PLLMB,
TEGRA_EMC_SRC_PLLP_UD,
TEGRA_EMC_SRC_COUNT,
} EmcSource;
enum {
DRAM_TYPE_DDR3 = 0,
DRAM_TYPE_LPDDR4 = 1,
DRAM_TYPE_LPDDR2 = 2,
DRAM_TYPE_DDR2 = 3,
};
enum {
DLL_CHANGE_NONE = 0,
DLL_CHANGE_ON,
DLL_CHANGE_OFF,
};
enum {
DLL_OFF,
DLL_ON
};
enum {
AUTO_PD = 0,
MAN_SR = 2
};
enum {
ASSEMBLY = 0,
ACTIVE
};
enum {
T_RP = 0,
T_FC_LPDDR4,
T_RFC,
T_PDEX,
RL
};
enum {
ONE_RANK = 1,
TWO_RANK = 2
};
enum {
SINGLE_CHANNEL = 0,
DUAL_CHANNEL
};
enum {
DRAM_DEV_SEL_ALL = 0,
DRAM_DEV_SEL_0 = (2 << 30),
DRAM_DEV_SEL_1 = (1 << 30),
};
enum {
EMC_CFG5_QUSE_MODE_NORMAL = 0,
EMC_CFG5_QUSE_MODE_ALWAYS_ON,
EMC_CFG5_QUSE_MODE_INTERNAL_LPBK,
EMC_CFG5_QUSE_MODE_PULSE_INTERN,
EMC_CFG5_QUSE_MODE_PULSE_EXTERN,
EMC_CFG5_QUSE_MODE_DIRECT_QUSE,
};
enum {
DVFS_SEQUENCE = 1,
WRITE_TRAINING_SEQUENCE = 2,
PERIODIC_TRAINING_SEQUENCE = 3,
DVFS_PT1 = 10,
DVFS_UPDATE = 11,
TRAINING_PT1 = 12,
TRAINING_UPDATE = 13,
PERIODIC_TRAINING_UPDATE = 14
};
enum {
TEGRA_DRAM_OVER_TEMP_NONE = 0,
TEGRA_DRAM_OVER_TEMP_REFRESH_X2,
TEGRA_DRAM_OVER_TEMP_REFRESH_X4,
TEGRA_DRAM_OVER_TEMP_THROTTLE,
TEGRA_DRAM_OVER_TEMP_MAX,
};
/* Train all possible DRAM sequences. */
void train_dram();
#endif

File diff suppressed because it is too large Load diff