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mtc: implement memory training for mariko (#1593)

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* mtc: implement memory training for mariko

* mtc: fix apply_periodic_compensation_trimmer, train_wr_vref results

* mtc: fix clktree calculations
This commit is contained in:
SciresM 2021-08-17 17:27:12 -07:00 committed by GitHub
parent f5704d25f8
commit aee89db748
No known key found for this signature in database
GPG key ID: 4AEE18F83AFDEB23
9 changed files with 15719 additions and 280 deletions
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9
fusee/fusee-mtc/src/car.h
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@ -490,6 +490,15 @@ typedef struct {
uint32_t sdmmc4_pllc4_out1_shaper_ctrl; /* _SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0, 0x73c */ uint32_t sdmmc4_pllc4_out1_shaper_ctrl; /* _SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0, 0x73c */
uint32_t sdmmc4_pllc4_out2_shaper_ctrl; /* _SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0, 0x740 */ uint32_t sdmmc4_pllc4_out2_shaper_ctrl; /* _SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0, 0x740 */
uint32_t sdmmc4_div_clk_shaper_ctrl; /* _SDMMC4_DIV_CLK_SHAPER_CTRL_0, 0x744 */ uint32_t sdmmc4_div_clk_shaper_ctrl; /* _SDMMC4_DIV_CLK_SHAPER_CTRL_0, 0x744 */
uint32_t _0x748[(0x774-0x748) / sizeof(uint32_t)]; // TODO
uint32_t pllm_ss_cfg; /* _PLLM_SS_CFG_0, 0x744 */
uint32_t pllm_ss_ctrl1; /* _PLLM_SS_CTRL1_0, 0x778 */
uint32_t pllm_ss_ctrl2; /* _PLLM_SS_CTRL2_0, 0x77C */
uint32_t pllmb_ss_cfg; /* _PLLMB_SS_CFG_0, 0x780 */
uint32_t pllmb_ss_ctrl1; /* _PLLMB_SS_CTRL1_0, 0x784 */
uint32_t pllmb_ss_ctrl2; /* _PLLMB_SS_CTRL2_0, 0x788 */
} tegra_car_t; } tegra_car_t;
static inline volatile tegra_car_t *car_get_regs(void) { static inline volatile tegra_car_t *car_get_regs(void) {

9
fusee/fusee-mtc/src/emc.h
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@ -393,6 +393,7 @@
#define EMC_CFG_DIG_DLL_PERIOD 0x2c0 #define EMC_CFG_DIG_DLL_PERIOD 0x2c0
#define EMC_DIG_DLL_STATUS 0x2c4 #define EMC_DIG_DLL_STATUS 0x2c4
#define EMC_DIG_DLL_STATUS_DLL_LOCK (1 << 15) #define EMC_DIG_DLL_STATUS_DLL_LOCK (1 << 15)
#define EMC_DIG_DLL_STATUS_DLL_LOCK_B01 (1 << 2)
#define EMC_DIG_DLL_STATUS_DLL_PRIV_UPDATED (1 << 17) #define EMC_DIG_DLL_STATUS_DLL_PRIV_UPDATED (1 << 17)
#define EMC_DIG_DLL_STATUS_DLL_OUT_SHIFT 0 #define EMC_DIG_DLL_STATUS_DLL_OUT_SHIFT 0
#define EMC_DIG_DLL_STATUS_DLL_OUT_MASK \ #define EMC_DIG_DLL_STATUS_DLL_OUT_MASK \
@ -1065,6 +1066,10 @@
#define EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQSN_TX_E_DCC (1 << 16) #define EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQSN_TX_E_DCC (1 << 16)
#define EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_CMD_TX_E_DCC (1 << 24) #define EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_CMD_TX_E_DCC (1 << 24)
#define EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQS_E_IVREF_B01 (1 << 10)
#define EMC_PMACRO_COMMON_PAD_TX_CTRL 0xc68 #define EMC_PMACRO_COMMON_PAD_TX_CTRL 0xc68
#define EMC_PMACRO_BRICK_MAPPING_0 0xc80 #define EMC_PMACRO_BRICK_MAPPING_0 0xc80
#define EMC_PMACRO_BRICK_MAPPING_1 0xc84 #define EMC_PMACRO_BRICK_MAPPING_1 0xc84
@ -1126,4 +1131,8 @@
#define EMC_PMACRO_DSR_VTTGEN_CTRL_0 0xc6c #define EMC_PMACRO_DSR_VTTGEN_CTRL_0 0xc6c
// B01
#define EMC_PMACRO_DLL_CFG_0 0x5E4
#define EMC_PMACRO_DLL_CFG_1 0x5E8
#endif #endif

3
fusee/fusee-mtc/src/mtc.c
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@ -17,6 +17,7 @@
*/ */
#include "mtc.h" #include "mtc.h"
#include "mtc_b01.h"
#include "mtc_tables.h" #include "mtc_tables.h"
#include "car.h" #include "car.h"
#include "fuse.h" #include "fuse.h"
@ -3742,7 +3743,7 @@ static void train_dram_erista(void) {
void train_dram(void) { void train_dram(void) {
if (is_soc_mariko()) { if (is_soc_mariko()) {
/* TODO */ train_dram_mariko();
} else { } else {
train_dram_erista(); train_dram_erista();
} }

2
fusee/fusee-mtc/src/mtc.h
View file

@ -35,7 +35,7 @@
#define TEGRA21_MAX_TABLE_ID_LEN 50 #define TEGRA21_MAX_TABLE_ID_LEN 50
#define TEGRA_EMC_ISO_USE_FREQ_MAX_NUM 12 #define TEGRA_EMC_ISO_USE_FREQ_MAX_NUM 12
#define PLL_C_DIRECT_FLOOR 333500000 #define PLL_C_DIRECT_FLOOR 333500000
#define EMC_STATUS_UPDATE_TIMEOUT 1000 #define EMC_STATUS_UPDATE_TIMEOUT 2000
#define TEGRA_EMC_DEFAULT_CLK_LATENCY_US 2000 #define TEGRA_EMC_DEFAULT_CLK_LATENCY_US 2000
#define TEGRA_EMC_MODE_REG_17 0x00110000 #define TEGRA_EMC_MODE_REG_17 0x00110000

4180
fusee/fusee-mtc/src/mtc_b01.c Normal file
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File diff suppressed because it is too large Load diff

689
fusee/fusee-mtc/src/mtc_b01.h Normal file
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@ -0,0 +1,689 @@
/*
* Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2018 CTCaer <ctcaer@gmail.com>
* Copyright (c) 2018-2020 Atmosphère-NX
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef FUSEE_MTC_B01_H_
#define FUSEE_MTC_B01_H_
#include "mtc.h"
typedef struct {
uint32_t ptfv_dqsosc_movavg_c0d0u0;
uint32_t ptfv_dqsosc_movavg_c0d0u1;
uint32_t ptfv_dqsosc_movavg_c0d1u0;
uint32_t ptfv_dqsosc_movavg_c0d1u1;
uint32_t ptfv_dqsosc_movavg_c1d0u0;
uint32_t ptfv_dqsosc_movavg_c1d0u1;
uint32_t ptfv_dqsosc_movavg_c1d1u0;
uint32_t ptfv_dqsosc_movavg_c1d1u1;
uint32_t ptfv_write_samples;
uint32_t ptfv_dvfs_samples;
uint32_t ptfv_movavg_weight;
uint32_t ptfv_config_ctrl;
} t210_emc_ptfv_list_table;
typedef struct {
uint32_t emc_rc;
uint32_t emc_rfc;
uint32_t emc_rfcpb;
uint32_t emc_refctrl2;
uint32_t emc_rfc_slr;
uint32_t emc_ras;
uint32_t emc_rp;
uint32_t emc_r2w;
uint32_t emc_w2r;
uint32_t emc_r2p;
uint32_t emc_w2p;
uint32_t emc_r2r;
uint32_t emc_tppd;
uint32_t emc_trtm;
uint32_t emc_twtm;
uint32_t emc_tratm;
uint32_t emc_twatm;
uint32_t emc_tr2ref;
uint32_t emc_ccdmw;
uint32_t emc_rd_rcd;
uint32_t emc_wr_rcd;
uint32_t emc_rrd;
uint32_t emc_rext;
uint32_t emc_wext;
uint32_t emc_wdv_chk;
uint32_t emc_wdv;
uint32_t emc_wsv;
uint32_t emc_wev;
uint32_t emc_wdv_mask;
uint32_t emc_ws_duration;
uint32_t emc_we_duration;
uint32_t emc_quse;
uint32_t emc_quse_width;
uint32_t emc_ibdly;
uint32_t emc_obdly;
uint32_t emc_einput;
uint32_t emc_mrw6;
uint32_t emc_einput_duration;
uint32_t emc_puterm_extra;
uint32_t emc_puterm_width;
uint32_t emc_qrst;
uint32_t emc_qsafe;
uint32_t emc_rdv;
uint32_t emc_rdv_mask;
uint32_t emc_rdv_early;
uint32_t emc_rdv_early_mask;
uint32_t emc_refresh;
uint32_t emc_burst_refresh_num;
uint32_t emc_pre_refresh_req_cnt;
uint32_t emc_pdex2wr;
uint32_t emc_pdex2rd;
uint32_t emc_pchg2pden;
uint32_t emc_act2pden;
uint32_t emc_ar2pden;
uint32_t emc_rw2pden;
uint32_t emc_cke2pden;
uint32_t emc_pdex2cke;
uint32_t emc_pdex2mrr;
uint32_t emc_txsr;
uint32_t emc_txsrdll;
uint32_t emc_tcke;
uint32_t emc_tckesr;
uint32_t emc_tpd;
uint32_t emc_tfaw;
uint32_t emc_trpab;
uint32_t emc_tclkstable;
uint32_t emc_tclkstop;
uint32_t emc_mrw7;
uint32_t emc_trefbw;
uint32_t emc_odt_write;
uint32_t emc_fbio_cfg5;
uint32_t emc_fbio_cfg7;
uint32_t emc_cfg_dig_dll;
uint32_t emc_cfg_dig_dll_period;
uint32_t emc_pmacro_ib_rxrt;
uint32_t emc_cfg_pipe_1;
uint32_t emc_cfg_pipe_2;
uint32_t emc_pmacro_quse_ddll_rank0_4;
uint32_t emc_pmacro_quse_ddll_rank0_5;
uint32_t emc_pmacro_quse_ddll_rank1_4;
uint32_t emc_pmacro_quse_ddll_rank1_5;
uint32_t emc_mrw8;
uint32_t emc_pmacro_ob_ddll_long_dq_rank1_4;
uint32_t emc_pmacro_ob_ddll_long_dq_rank1_5;
uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_0;
uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_1;
uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_2;
uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_3;
uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_4;
uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_5;
uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_0;
uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_1;
uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_2;
uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_3;
uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_4;
uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_5;
uint32_t emc_pmacro_ddll_long_cmd_0;
uint32_t emc_pmacro_ddll_long_cmd_1;
uint32_t emc_pmacro_ddll_long_cmd_2;
uint32_t emc_pmacro_ddll_long_cmd_3;
uint32_t emc_pmacro_ddll_long_cmd_4;
uint32_t emc_pmacro_ddll_short_cmd_0;
uint32_t emc_pmacro_ddll_short_cmd_1;
uint32_t emc_pmacro_ddll_short_cmd_2;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte0_3;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte1_3;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte2_3;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte3_3;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte4_3;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte5_3;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte6_3;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte7_3;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd0_3;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd1_3;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd2_3;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd3_3;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte0_3;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte1_3;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte2_3;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte3_3;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte4_3;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte5_3;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte6_3;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte7_3;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd0_0;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd0_1;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd0_2;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd0_3;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd1_0;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd1_1;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd1_2;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd1_3;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd2_0;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd2_1;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd2_2;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd2_3;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd3_0;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd3_1;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd3_2;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd3_3;
uint32_t emc_txdsrvttgen;
uint32_t emc_fdpd_ctrl_dq;
uint32_t emc_fdpd_ctrl_cmd;
uint32_t emc_fbio_spare;
uint32_t emc_zcal_interval;
uint32_t emc_zcal_wait_cnt;
uint32_t emc_mrs_wait_cnt;
uint32_t emc_mrs_wait_cnt2;
uint32_t emc_auto_cal_channel;
uint32_t emc_pmacro_dll_cfg_0;
uint32_t emc_pmacro_dll_cfg_1;
uint32_t emc_pmacro_dll_cfg_2;
uint32_t emc_pmacro_autocal_cfg_common;
uint32_t emc_pmacro_zctrl;
uint32_t emc_cfg;
uint32_t emc_cfg_pipe;
uint32_t emc_dyn_self_ref_control;
uint32_t emc_qpop;
uint32_t emc_dqs_brlshft_0;
uint32_t emc_dqs_brlshft_1;
uint32_t emc_cmd_brlshft_2;
uint32_t emc_cmd_brlshft_3;
uint32_t emc_pmacro_pad_cfg_ctrl;
uint32_t emc_pmacro_data_pad_rx_ctrl;
uint32_t emc_pmacro_cmd_pad_rx_ctrl;
uint32_t emc_pmacro_data_rx_term_mode;
uint32_t emc_pmacro_cmd_rx_term_mode;
uint32_t emc_pmacro_cmd_pad_tx_ctrl;
uint32_t emc_pmacro_data_pad_tx_ctrl;
uint32_t emc_pmacro_vttgen_ctrl_0;
uint32_t emc_pmacro_vttgen_ctrl_1;
uint32_t emc_pmacro_vttgen_ctrl_2;
uint32_t emc_pmacro_brick_ctrl_rfu1;
uint32_t emc_pmacro_cmd_brick_ctrl_fdpd;
uint32_t emc_pmacro_brick_ctrl_rfu2;
uint32_t emc_pmacro_data_brick_ctrl_fdpd;
uint32_t emc_pmacro_bg_bias_ctrl_0;
uint32_t emc_cfg_3;
uint32_t emc_pmacro_tx_pwrd_0;
uint32_t emc_pmacro_tx_pwrd_1;
uint32_t emc_pmacro_tx_pwrd_2;
uint32_t emc_pmacro_tx_pwrd_3;
uint32_t emc_pmacro_tx_pwrd_4;
uint32_t emc_pmacro_tx_pwrd_5;
uint32_t emc_config_sample_delay;
uint32_t emc_pmacro_tx_sel_clk_src_0;
uint32_t emc_pmacro_tx_sel_clk_src_1;
uint32_t emc_pmacro_tx_sel_clk_src_2;
uint32_t emc_pmacro_tx_sel_clk_src_3;
uint32_t emc_pmacro_tx_sel_clk_src_4;
uint32_t emc_pmacro_tx_sel_clk_src_5;
uint32_t emc_pmacro_ddll_bypass;
uint32_t emc_pmacro_ddll_pwrd_0;
uint32_t emc_pmacro_ddll_pwrd_1;
uint32_t emc_pmacro_ddll_pwrd_2;
uint32_t emc_pmacro_cmd_ctrl_0;
uint32_t emc_pmacro_cmd_ctrl_1;
uint32_t emc_pmacro_cmd_ctrl_2;
uint32_t emc_pmacro_data_pi_ctrl;
uint32_t emc_pmacro_cmd_pi_ctrl;
uint32_t emc_tr_timing_0;
uint32_t emc_tr_dvfs;
uint32_t emc_tr_ctrl_1;
uint32_t emc_tr_rdv;
uint32_t emc_tr_qpop;
uint32_t emc_tr_rdv_mask;
uint32_t emc_mrw14;
uint32_t emc_tr_qsafe;
uint32_t emc_tr_qrst;
uint32_t emc_training_ctrl;
uint32_t emc_training_settle;
uint32_t emc_training_vref_settle;
uint32_t emc_training_ca_fine_ctrl;
uint32_t emc_training_ca_ctrl_misc;
uint32_t emc_training_ca_ctrl_misc1;
uint32_t emc_training_ca_vref_ctrl;
uint32_t emc_training_quse_cors_ctrl;
uint32_t emc_training_quse_fine_ctrl;
uint32_t emc_training_quse_ctrl_misc;
uint32_t emc_training_quse_vref_ctrl;
uint32_t emc_training_read_fine_ctrl;
uint32_t emc_training_read_ctrl_misc;
uint32_t emc_training_read_vref_ctrl;
uint32_t emc_training_write_fine_ctrl;
uint32_t emc_training_write_ctrl_misc;
uint32_t emc_training_write_vref_ctrl;
uint32_t emc_training_mpc;
uint32_t emc_mrw15;
} t210b01_emc_burst_regs;
typedef struct {
uint32_t emc0_mrw10;
uint32_t emc1_mrw10;
uint32_t emc0_mrw11;
uint32_t emc1_mrw11;
uint32_t emc0_mrw12;
uint32_t emc1_mrw12;
uint32_t emc0_mrw13;
uint32_t emc1_mrw13;
} t210_emc_burst_reg_per_ch;
typedef struct {
uint32_t emc_pmacro_ib_ddll_long_dqs_rank0_0;
uint32_t emc_pmacro_ib_ddll_long_dqs_rank0_1;
uint32_t emc_pmacro_ib_ddll_long_dqs_rank0_2;
uint32_t emc_pmacro_ib_ddll_long_dqs_rank0_3;
uint32_t emc_pmacro_ib_ddll_long_dqs_rank1_0;
uint32_t emc_pmacro_ib_ddll_long_dqs_rank1_1;
uint32_t emc_pmacro_ib_ddll_long_dqs_rank1_2;
uint32_t emc_pmacro_ib_ddll_long_dqs_rank1_3;
uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte0_0;
uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte0_1;
uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte0_2;
uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte1_0;
uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte1_1;
uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte1_2;
uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte2_0;
uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte2_1;
uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte2_2;
uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte3_0;
uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte3_1;
uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte3_2;
uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte4_0;
uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte4_1;
uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte4_2;
uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte5_0;
uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte5_1;
uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte5_2;
uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte6_0;
uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte6_1;
uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte6_2;
uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte7_0;
uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte7_1;
uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte7_2;
uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte0_0;
uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte0_1;
uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte0_2;
uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte1_0;
uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte1_1;
uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte1_2;
uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte2_0;
uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte2_1;
uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte2_2;
uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte3_0;
uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte3_1;
uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte3_2;
uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte4_0;
uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte4_1;
uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte4_2;
uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte5_0;
uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte5_1;
uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte5_2;
uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte6_0;
uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte6_1;
uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte6_2;
uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte7_0;
uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte7_1;
uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte7_2;
uint32_t emc_pmacro_ib_vref_dqs_0;
uint32_t emc_pmacro_ib_vref_dqs_1;
uint32_t emc_pmacro_ib_vref_dq_0;
uint32_t emc_pmacro_ib_vref_dq_1;
uint32_t emc_pmacro_ob_ddll_long_dq_rank0_0;
uint32_t emc_pmacro_ob_ddll_long_dq_rank0_1;
uint32_t emc_pmacro_ob_ddll_long_dq_rank0_2;
uint32_t emc_pmacro_ob_ddll_long_dq_rank0_3;
uint32_t emc_pmacro_ob_ddll_long_dq_rank0_4;
uint32_t emc_pmacro_ob_ddll_long_dq_rank0_5;
uint32_t emc_pmacro_ob_ddll_long_dq_rank1_0;
uint32_t emc_pmacro_ob_ddll_long_dq_rank1_1;
uint32_t emc_pmacro_ob_ddll_long_dq_rank1_2;
uint32_t emc_pmacro_ob_ddll_long_dq_rank1_3;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte0_0;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte0_1;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte0_2;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte1_0;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte1_1;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte1_2;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte2_0;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte2_1;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte2_2;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte3_0;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte3_1;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte3_2;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte4_0;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte4_1;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte4_2;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte5_0;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte5_1;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte5_2;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte6_0;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte6_1;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte6_2;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte7_0;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte7_1;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte7_2;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd0_0;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd0_1;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd0_2;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd1_0;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd1_1;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd1_2;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd2_0;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd2_1;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd2_2;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd3_0;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd3_1;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd3_2;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte0_0;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte0_1;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte0_2;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte1_0;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte1_1;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte1_2;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte2_0;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte2_1;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte2_2;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte3_0;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte3_1;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte3_2;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte4_0;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte4_1;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte4_2;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte5_0;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte5_1;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte5_2;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte6_0;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte6_1;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte6_2;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte7_0;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte7_1;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte7_2;
uint32_t emc_pmacro_quse_ddll_rank0_0;
uint32_t emc_pmacro_quse_ddll_rank0_1;
uint32_t emc_pmacro_quse_ddll_rank0_2;
uint32_t emc_pmacro_quse_ddll_rank0_3;
uint32_t emc_pmacro_quse_ddll_rank1_0;
uint32_t emc_pmacro_quse_ddll_rank1_1;
uint32_t emc_pmacro_quse_ddll_rank1_2;
uint32_t emc_pmacro_quse_ddll_rank1_3;
} t210_emc_trim_regs;
typedef struct {
uint32_t emc_cmd_brlshft_0;
uint32_t emc_cmd_brlshft_1;
uint32_t emc0_data_brlshft_0;
uint32_t emc1_data_brlshft_0;
uint32_t emc0_data_brlshft_1;
uint32_t emc1_data_brlshft_1;
uint32_t emc_quse_brlshft_0;
uint32_t emc_quse_brlshft_1;
uint32_t emc_quse_brlshft_2;
uint32_t emc_quse_brlshft_3;
} t210_emc_trim_perch_regs;
typedef struct {
uint32_t emc0_training_opt_dqs_ib_vref_rank0;
uint32_t emc1_training_opt_dqs_ib_vref_rank0;
uint32_t emc0_training_opt_dqs_ib_vref_rank1;
uint32_t emc1_training_opt_dqs_ib_vref_rank1;
} t210_emc_vref_perch_regs;
typedef struct {
uint32_t t_rp;
uint32_t t_fc_lpddr4;
uint32_t t_rfc;
uint32_t t_pdex;
uint32_t rl;
} t210_emc_dram_timings;
typedef struct {
uint32_t emc0_training_rw_offset_ib_byte0;
uint32_t emc1_training_rw_offset_ib_byte0;
uint32_t emc0_training_rw_offset_ib_byte1;
uint32_t emc1_training_rw_offset_ib_byte1;
uint32_t emc0_training_rw_offset_ib_byte2;
uint32_t emc1_training_rw_offset_ib_byte2;
uint32_t emc0_training_rw_offset_ib_byte3;
uint32_t emc1_training_rw_offset_ib_byte3;
uint32_t emc0_training_rw_offset_ib_misc;
uint32_t emc1_training_rw_offset_ib_misc;
uint32_t emc0_training_rw_offset_ob_byte0;
uint32_t emc1_training_rw_offset_ob_byte0;
uint32_t emc0_training_rw_offset_ob_byte1;
uint32_t emc1_training_rw_offset_ob_byte1;
uint32_t emc0_training_rw_offset_ob_byte2;
uint32_t emc1_training_rw_offset_ob_byte2;
uint32_t emc0_training_rw_offset_ob_byte3;
uint32_t emc1_training_rw_offset_ob_byte3;
uint32_t emc0_training_rw_offset_ob_misc;
uint32_t emc1_training_rw_offset_ob_misc;
} t210_emc_training_mod_regs;
typedef struct {
uint32_t mc_emem_arb_cfg;
uint32_t mc_emem_arb_outstanding_req;
uint32_t mc_emem_arb_refpb_hp_ctrl;
uint32_t mc_emem_arb_refpb_bank_ctrl;
uint32_t mc_emem_arb_timing_rcd;
uint32_t mc_emem_arb_timing_rp;
uint32_t mc_emem_arb_timing_rc;
uint32_t mc_emem_arb_timing_ras;
uint32_t mc_emem_arb_timing_faw;
uint32_t mc_emem_arb_timing_rrd;
uint32_t mc_emem_arb_timing_rap2pre;
uint32_t mc_emem_arb_timing_wap2pre;
uint32_t mc_emem_arb_timing_r2r;
uint32_t mc_emem_arb_timing_w2w;
uint32_t mc_emem_arb_timing_r2w;
uint32_t mc_emem_arb_timing_ccdmw;
uint32_t mc_emem_arb_timing_w2r;
uint32_t mc_emem_arb_timing_rfcpb;
uint32_t mc_emem_arb_da_turns;
uint32_t mc_emem_arb_da_covers;
uint32_t mc_emem_arb_misc0;
uint32_t mc_emem_arb_misc1;
uint32_t mc_emem_arb_misc2;
uint32_t mc_emem_arb_ring1_throttle;
uint32_t mc_emem_arb_dhyst_ctrl;
uint32_t mc_emem_arb_dhyst_timeout_util_0;
uint32_t mc_emem_arb_dhyst_timeout_util_1;
uint32_t mc_emem_arb_dhyst_timeout_util_2;
uint32_t mc_emem_arb_dhyst_timeout_util_3;
uint32_t mc_emem_arb_dhyst_timeout_util_4;
uint32_t mc_emem_arb_dhyst_timeout_util_5;
uint32_t mc_emem_arb_dhyst_timeout_util_6;
uint32_t mc_emem_arb_dhyst_timeout_util_7;
} t210_emc_burst_mc_regs;
typedef struct {
uint32_t mc_mll_mpcorer_ptsa_rate;
uint32_t mc_ftop_ptsa_rate;
uint32_t mc_ptsa_grant_decrement;
uint32_t mc_latency_allowance_xusb_0;
uint32_t mc_latency_allowance_xusb_1;
uint32_t mc_latency_allowance_tsec_0;
uint32_t mc_latency_allowance_sdmmca_0;
uint32_t mc_latency_allowance_sdmmcaa_0;
uint32_t mc_latency_allowance_sdmmc_0;
uint32_t mc_latency_allowance_sdmmcab_0;
uint32_t mc_latency_allowance_ppcs_0;
uint32_t mc_latency_allowance_ppcs_1;
uint32_t mc_latency_allowance_mpcore_0;
uint32_t mc_latency_allowance_hc_0;
uint32_t mc_latency_allowance_hc_1;
uint32_t mc_latency_allowance_avpc_0;
uint32_t mc_latency_allowance_gpu_0;
uint32_t mc_latency_allowance_gpu2_0;
uint32_t mc_latency_allowance_nvenc_0;
uint32_t mc_latency_allowance_nvdec_0;
uint32_t mc_latency_allowance_vic_0;
uint32_t mc_latency_allowance_vi2_0;
uint32_t mc_latency_allowance_isp2_0;
uint32_t mc_latency_allowance_isp2_1;
} t210_emc_la_scale_regs;
typedef struct {
uint32_t rev;
char dvfs_ver[60];
uint32_t rate_khz;
uint32_t min_volt;
uint32_t gpu_min_volt;
char clock_src[32];
uint32_t clk_src_emc;
uint32_t pll_en_ssc;
uint32_t needs_training;
uint32_t training_pattern;
uint32_t trained;
uint32_t periodic_training;
uint32_t trained_dram_clktree_c0d0u0;
uint32_t trained_dram_clktree_c0d0u1;
uint32_t trained_dram_clktree_c0d1u0;
uint32_t trained_dram_clktree_c0d1u1;
uint32_t trained_dram_clktree_c1d0u0;
uint32_t trained_dram_clktree_c1d0u1;
uint32_t trained_dram_clktree_c1d1u0;
uint32_t trained_dram_clktree_c1d1u1;
uint32_t current_dram_clktree_c0d0u0;
uint32_t current_dram_clktree_c0d0u1;
uint32_t current_dram_clktree_c0d1u0;
uint32_t current_dram_clktree_c0d1u1;
uint32_t current_dram_clktree_c1d0u0;
uint32_t current_dram_clktree_c1d0u1;
uint32_t current_dram_clktree_c1d1u0;
uint32_t current_dram_clktree_c1d1u1;
uint32_t emc_fbio_cfg7;
uint32_t run_clocks;
uint32_t tree_margin;
uint32_t num_burst;
uint32_t num_burst_per_ch;
uint32_t num_trim;
uint32_t num_trim_per_ch;
uint32_t num_mc_regs;
uint32_t num_up_down;
uint32_t vref_num;
uint32_t training_mod_num;
uint32_t dram_timing_num;
t210_emc_ptfv_list_table ptfv_list;
union {
t210b01_emc_burst_regs burst_regs;
uint32_t burst_regs_arr[sizeof(t210b01_emc_burst_regs) / sizeof(uint32_t)];
};
union {
t210_emc_burst_reg_per_ch burst_reg_per_ch;
uint32_t burst_reg_per_ch_arr[sizeof(t210_emc_burst_reg_per_ch) / sizeof(uint32_t)];
};
union {
t210b01_emc_burst_regs shadow_regs_ca_train;
uint32_t shadow_regs_ca_train_arr[sizeof(t210b01_emc_burst_regs) / sizeof(uint32_t)];
};
union {
t210b01_emc_burst_regs shadow_regs_rdwr_train;
uint32_t shadow_regs_rdwr_train_arr[sizeof(t210b01_emc_burst_regs) / sizeof(uint32_t)];
};
union {
t210_emc_trim_regs trim_regs;
uint32_t trim_regs_arr[sizeof(t210_emc_trim_regs) / sizeof(uint32_t)];
};
union {
t210_emc_trim_perch_regs trim_perch_regs;
uint32_t trim_perch_regs_arr[sizeof(t210_emc_trim_perch_regs) / sizeof(uint32_t)];
};
union {
t210_emc_vref_perch_regs vref_perch_regs;
uint32_t vref_perch_regs_arr[sizeof(t210_emc_vref_perch_regs) / sizeof(uint32_t)];
};
t210_emc_dram_timings dram_timings;
uint32_t zq_op_cc_long_zcal;
uint32_t zq_op_cc_short_zcal;
uint32_t zcal_wait_time_ps_cc_long_zcal;
uint32_t zcal_wait_time_ps_cc_short_zcal;
uint32_t tZQCAL_lpddr4;
uint32_t zqcal_before_cc_cutoff;
uint32_t opt_cc_short_zcal;
uint32_t opt_short_zcal;
uint32_t opt_do_sw_qrst;
uint32_t save_restore_clkstop_pd;
uint32_t opt_E90;
uint32_t cya_allow_ref_cc;
uint32_t ref_b4_sref_en;
uint32_t cya_issue_pc_ref;
union {
t210_emc_training_mod_regs training_mod_regs;
uint32_t training_mod_regs_arr[sizeof(t210_emc_training_mod_regs) / sizeof(uint32_t)];
};
uint32_t save_restore_mod_regs[12];
union {
t210_emc_burst_mc_regs burst_mc_regs;
uint32_t burst_mc_regs_arr[sizeof(t210_emc_burst_mc_regs) / sizeof(uint32_t)];
};
union {
t210_emc_la_scale_regs la_scale_regs;
uint32_t la_scale_regs_arr[sizeof(t210_emc_la_scale_regs) / sizeof(uint32_t)];
};
uint32_t unk_0;
uint32_t vtt_vdda_ctrl_0;
uint32_t src_clock_div;
uint32_t vtt_vdda_dual_channel;
uint32_t vtt_vdda_ctrl_1;
uint32_t vtt_vdda_ctrl_2;
uint32_t vtt_vdda_ctrl_3;
uint32_t vtt_vdda_ctrl_4;
uint32_t misc_cfg_0;
uint32_t misc_cfg_1;
uint32_t misc_cfg_2;
uint32_t unk_1;
uint32_t unk_2;
uint32_t pipe_clk_delay;
uint32_t clkchange_delay;
uint32_t pllm_ss_cfg;
uint32_t pllm_ss_ctrl1;
uint32_t pllm_ss_ctrl2;
uint32_t pllmb_ss_cfg;
uint32_t pllmb_ss_ctrl1;
uint32_t pllmb_ss_ctrl2;
uint32_t pllmb_divm;
uint32_t pllmb_divn;
uint32_t pllmb_divp;
uint32_t min_mrs_wait;
uint32_t ramp_wait;
uint32_t emc_mrw;
uint32_t emc_mrw2;
uint32_t emc_mrw3;
uint32_t emc_mrw4;
uint32_t emc_mrw9;
uint32_t emc_mrs;
uint32_t emc_emrs;
uint32_t emc_emrs2;
uint32_t emc_auto_cal_config;
uint32_t emc_auto_cal_config2;
uint32_t emc_auto_cal_config3;
uint32_t emc_auto_cal_config4;
uint32_t emc_auto_cal_config5;
uint32_t emc_auto_cal_config6;
uint32_t emc_auto_cal_config7;
uint32_t emc_auto_cal_config8;
uint32_t emc_cfg_2;
uint32_t emc_sel_dpd_ctrl;
uint32_t emc_fdpd_ctrl_cmd_no_ramp;
uint32_t emc_tr_ctrl_0;
uint32_t dll_clk_src;
uint32_t clk_out_enb_x_0_clk_enb_emc_dll;
uint32_t latency;
uint32_t pllm_misc1_0_pllm_clamp_ph90;
} tegra_b01_emc_timing_t;
_Static_assert(sizeof(tegra_b01_emc_timing_t) == 0x10CC);
void train_dram_mariko(void);
#endif

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fusee/fusee-mtc/src/mtc_tables_b01.h Normal file
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