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https://github.com/Atmosphere-NX/Atmosphere
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Implement more SE context save functionality
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93634d08e3
commit
a8a2f8c3f6
3 changed files with 69 additions and 7 deletions
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@ -60,7 +60,7 @@ void save_se_and_power_down_cpu(void) {
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uint8_t *se_state_dst = (uint8_t *)(WARMBOOT_GET_RAM_SEGMENT_ADDRESS(WARMBOOT_RAM_SEGMENT_ID_SE_STATE));
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se_check_error_status_reg();
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se_set_in_context_save_mode(true);
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se_save_context(KEYSLOT_SWITCH_SRKKEY, KEYSLOT_SWITCH_RNGKEY, se_state_dst);
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se_save_context(KEYSLOT_SWITCH_SRKGENKEY, KEYSLOT_SWITCH_RNGKEY, se_state_dst);
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flush_dcache_range(se_state_dst, se_state_dst + 0x840);
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APBDEV_PMC_SCRATCH43_0 = (uint32_t)(WARMBOOT_GET_RAM_SEGMENT_PA(WARMBOOT_RAM_SEGMENT_ID_SE_STATE));
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se_set_in_context_save_mode(false);
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@ -534,7 +534,15 @@ void se_compute_aes_256_cmac(unsigned int keyslot, void *cmac, size_t cmac_size,
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}
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void se_aes_256_cbc_encrypt(unsigned int keyslot, void *dst, size_t dst_size, const void *src, size_t src_size, const void *iv) {
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/* TODO */
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if (keyslot >= KEYSLOT_AES_MAX || src_size < 0x10) {
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generic_panic();
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}
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SECURITY_ENGINE->CONFIG_REG = (ALG_AES_ENC | DST_MEMORY) | (0x202 << 16);
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SECURITY_ENGINE->CRYPTO_REG = (keyslot << 24) | 0x144;
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set_aes_keyslot_iv(keyslot, iv, 0x10);
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SECURITY_ENGINE->BLOCK_COUNT_REG = (src_size >> 4) - 1;
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trigger_se_blocking_op(1, dst, dst_size, src, src_size);
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}
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/* SHA256 Implementation. */
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@ -603,13 +611,67 @@ void se_generate_random(unsigned int keyslot, void *dst, size_t size) {
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/* SE context save API. */
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void se_set_in_context_save_mode(bool is_context_save_mode) {
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/* TODO */
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uint32_t val = SECURITY_ENGINE->_0x0;
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if (is_context_save_mode) {
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val |= 0x10000;
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} else {
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val &= 0xFFFEFFFF;
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}
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SECURITY_ENGINE->_0x0 = val;
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/* Perform a useless read from flags reg. */
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(void)(SECURITY_ENGINE->FLAGS_REG);
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}
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void se_generate_random_key(unsigned int dst_keyslot, unsigned int rng_keyslot) {
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/* TODO */
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if (dst_keyslot >= KEYSLOT_AES_MAX || rng_keyslot >= KEYSLOT_AES_MAX) {
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generic_panic();
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}
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void se_save_context(unsigned int srk_keyslot, unsigned int rng_keyslot, void *dst) {
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/* TODO */
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/* Setup Config. */
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SECURITY_ENGINE->CONFIG_REG = (ALG_RNG | DST_KEYTAB);
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SECURITY_ENGINE->CRYPTO_REG = (rng_keyslot << 24) | 0x108;
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SECURITY_ENGINE->RNG_CONFIG_REG = 4;
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SECURITY_ENGINE->BLOCK_COUNT_REG = 0;
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/* Generate low part of key. */
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SECURITY_ENGINE->CRYPTO_KEYTABLE_DST_REG = (dst_keyslot << 8);
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trigger_se_blocking_op(1, NULL, 0, NULL, 0);
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/* Generate high part of key. */
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SECURITY_ENGINE->CRYPTO_KEYTABLE_DST_REG = (dst_keyslot << 8) | 1;
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trigger_se_blocking_op(1, NULL, 0, NULL, 0);
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}
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void se_generate_srk(unsigned int srkgen_keyslot) {
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SECURITY_ENGINE->CONFIG_REG = (ALG_RNG | DST_SRK);
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SECURITY_ENGINE->CRYPTO_REG = (srkgen_keyslot << 24) | 0x108;
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SECURITY_ENGINE->RNG_CONFIG_REG = 6;
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SECURITY_ENGINE->BLOCK_COUNT_REG = 0;
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trigger_se_blocking_op(1, NULL, 0, NULL, 0);
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}
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void se_encrypt_with_srk(void *dst, size_t dst_size, const void *src, size_t src_size) {
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uint8_t output[0x80];
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uint8_t *aligned_out = (uint8_t *)(((uintptr_t)output + 0x7F) & ~0x3F);
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if (dst_size > 0x10) {
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generic_panic();
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}
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if (src_size) {
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flush_dcache_range((uint8_t *)src, (uint8_t *)src + src_size);
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}
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if (dst_size) {
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flush_dcache_range(aligned_out, aligned_out + 0x10);
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trigger_se_blocking_op(3, aligned_out, dst_size, src, src_size);
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flush_dcache_range(aligned_out, aligned_out + 0x10);
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memcpy(dst, aligned_out, dst_size);
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} else {
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trigger_se_blocking_op(3, aligned_out, 0, src, src_size);
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}
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}
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void se_save_context(unsigned int srkgen_keyslot, unsigned int rng_keyslot, void *dst) {
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/* Generate the SRK (context save encryption key). */
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se_generate_random_key(srkgen_keyslot, rng_keyslot);
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se_generate_srk(srkgen_keyslot);
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/* TODO: Encrypt SE context with SRK. */
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}
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@ -10,7 +10,7 @@
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/* Exosphere driver for the Tegra X1 security engine. */
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#define KEYSLOT_SWITCH_LP0TZRAMKEY 0x2
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#define KEYSLOT_SWITCH_SRKKEY 0x8
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#define KEYSLOT_SWITCH_SRKGENKEY 0x8
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#define KEYSLOT_SWITCH_PACKAGE2KEY 0x8
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#define KEYSLOT_SWITCH_TEMPKEY 0x9
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#define KEYSLOT_SWITCH_SESSIONKEY 0xA
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