mirror of
https://github.com/Atmosphere-NX/Atmosphere
synced 2024-12-23 12:51:13 +00:00
thermosphere: pl011 uart refactor
This commit is contained in:
parent
57548e67fb
commit
a552c254e0
10 changed files with 224 additions and 135 deletions
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@ -145,7 +145,8 @@ ifeq ($(PLATFORM), qemu)
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export QEMU := qemu-system-aarch64
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QEMUFLAGS := -nographic -machine virt,virtualization=on,accel=tcg,gic-version=2 -cpu cortex-a57 -smp 4 -m 1024\
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-kernel thermosphere.elf -d unimp,guest_errors -semihosting-config enable,target=native -serial mon:stdio
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-kernel thermosphere.elf -d unimp,guest_errors -semihosting-config enable,target=native\
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-chardev stdio,id=uart -serial chardev:uart -monitor none
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qemu: all
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@$(QEMU) $(QEMUFLAGS)
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@ -37,7 +37,7 @@ int debugLog(const char *fmt, ...)
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if (DLOG_USE_SEMIHOSTING_WRITE0 && semihosting_connection_supported()) {
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semihosting_write_string(buf);
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} else {
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uartWriteData(buf, (size_t)res);
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uartWriteData(DEFAULT_UART, buf, (size_t)res);
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}
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return res;
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@ -98,7 +98,7 @@ static void initGic(void)
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currentCoreCtx->gicInterfaceMask = gicd->itargetsr[0];
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}
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static void configureInterrupt(u16 id, u8 prio, bool isLevelSensitive)
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void configureInterrupt(u16 id, u8 prio, bool isLevelSensitive)
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{
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volatile ArmGicV2Distributor *gicd = g_irqManager.gic.gicd;
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gicd->icenabler[id / 32] = BIT(id % 32);
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@ -129,6 +129,9 @@ void initIrq(void)
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configureInterrupt(GIC_IRQID_MAINTENANCE, IRQ_PRIORITY_HOST, true);
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for(u32 i=32; i < 256+32; i++) {
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configureInterrupt(i, IRQ_PRIORITY_HOST, true);
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}
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recursiveSpinlockUnlockRestoreIrq(&g_irqManager.lock, flags);
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}
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@ -159,7 +162,7 @@ void handleIrqException(ExceptionStackFrame *frame, bool isLowerEl, bool isA32)
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u32 irqId = iar & 0x3FF;
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u32 srcCore = (iar >> 10) & 7;
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//DEBUG("EL2 [core %d]: Received irq %x\n", (int)currentCoreCtx->coreId, irqId);
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DEBUG("EL2 [core %d]: Received irq %x\n", (int)currentCoreCtx->coreId, irqId);
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if (irqId == GIC_IRQID_SPURIOUS) {
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// Spurious interrupt received
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@ -21,6 +21,7 @@
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#include "exceptions.h"
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#include "utils.h"
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#include "platform/interrupt_config.h"
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#include "platform/uart.h"
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#define IRQ_PRIORITY_HOST 0
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#define IRQ_PRIORITY_GUEST 1
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@ -49,6 +50,7 @@ extern IrqManager g_irqManager;
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void initIrq(void);
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void handleIrqException(ExceptionStackFrame *frame, bool isLowerEl, bool isA32);
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void configureInterrupt(u16 id, u8 prio, bool isLevelSensitive);
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static inline void generateSgiForAllOthers(ThermosphereSgi id)
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{
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@ -78,6 +80,7 @@ static inline bool irqIsGuest(u16 id)
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}
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bool ret = id != GIC_IRQID_MAINTENANCE && id != GIC_IRQID_NS_PHYS_HYP_TIMER;
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ret = ret && id != uartGetIrqId(DEFAULT_UART); // FIXME
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#if GIC_IRQID_NS_VIRT_HYP_TIMER != GIC_IRQID_SPURIOUS
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ret = ret && id != GIC_IRQID_NS_VIRT_HYP_TIMER;
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#endif
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@ -45,7 +45,8 @@ void thermosphereMain(ExceptionStackFrame *frame)
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initIrq();
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if (currentCoreCtx->isBootCore) {
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uartInit(115200);
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uartInit(DEFAULT_UART, 115200, 0);
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uartSetInterruptStatus(DEFAULT_UART, false, false);
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DEBUG("EL2: core %u reached main first!\n", currentCoreCtx->coreId);
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}
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@ -35,6 +35,8 @@
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#define GIC_IRQID_SEC_PHYS_HYP_TIMER GIC_IRQID_SPURIOUS // SBSA: 20. Unimplemented
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#define GIC_IRQID_SEC_VIRT_HYP_TIMER GIC_IRQID_SPURIOUS // SBSA: 19. Unimplemented
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#define GIC_IRQID_UART 33
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static inline void initGicV2Pointers(ArmGicV2 *gic)
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{
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gic->gicd = (volatile ArmGicV2Distributor *)0x08000000ull;
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@ -15,9 +15,9 @@
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*/
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#include "uart.h"
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#include "../../utils.h"
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#include "../../irq.h"
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// Adapted from ARM TF asm code
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// Adapted from TF asm code
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// AMBA PL101 driver
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/*
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@ -28,52 +28,116 @@
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//115200
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void uartInit(u32 baudRate)
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static inline volatile PL011UartRegisters *uartGetRegisters(UartDevice dev)
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{
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// First, disable UART
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g_uartRegs->CR &= ~PL011_UARTCR_UARTEN;
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switch (dev) {
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case UART_A:
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return (volatile PL011UartRegisters *)0x09000000;
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default:
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return NULL;
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}
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}
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void uartInit(UartDevice dev, u32 baudRate, u32 flags)
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{
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/* The TRM (DDI0183) reads:
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Program the control registers as follows:
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1. Disable the UART.
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2. Wait for the end of transmission or reception of the current character.
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3. Flush the transmit FIFO by disabling bit 4 (FEN) in the line control register
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(UARTCLR_H).
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4. Reprogram the control register.
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5. Enable the UART.
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*/
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(void)flags;
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volatile PL011UartRegisters *uart = uartGetRegisters(dev);
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// First, disable the UART. Flush the receive FIFO, wait for tx to complete, and disable both FIFOs.
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uart->cr &= ~PL011_UARTCR_UARTEN;
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while (!(uart->fr & PL011_UARTFR_RXFE)) {
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uart->dr;
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}
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while (uart->fr & PL011_UARTFR_BUSY);
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// This flushes the transmit FIFO:
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uart->lcr_h &= ~PL011_UARTLCR_H_FEN;
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// Set baudrate, Divisor = (Uart clock * 4) / baudrate; stored in IBRD|FBRD
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u32 divisor = (4 * UART0_CLK_IN_HZ) / baudRate;
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g_uartRegs->IBRD = divisor >> 6;
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g_uartRegs->FBRD = divisor & 0x3F;
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g_uartRegs->LCR_H = PL011_LINE_CONTROL;
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u32 divisor = (4 * UART_CLK_IN_HZ) / baudRate;
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uart->ibrd = divisor >> 6;
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uart->fbrd = divisor & 0x3F;
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// Select FIFO fill levels for interrupts
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uart->ifls = PL011_IFLS_RX4_8 | PL011_IFLS_TX4_8;
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// FIFO Enabled / No Parity / 8 Data bit / One Stop Bit
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uart->lcr_h = PL011_UARTLCR_H_FEN | PL011_UARTLCR_H_WLEN_8;
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// Select the interrupts we want to have
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// RX timeout and TX/RX fill interrupts
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uart->imsc = PL011_RTI | PL011_RXI | PL011_RXI;
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// Clear any pending errors
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g_uartRegs->ECR = 0;
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uart->ecr = 0;
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// Clear all interrupts
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uart->icr = PL011_ALL_INTERRUPTS;
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// Register the interrupt ID
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//configureInterrupt(uartGetIrqId(dev), IRQ_PRIORITY_HOST, true);
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// Enable tx, rx, and uart overall
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g_uartRegs->CR = PL011_UARTCR_RXE | PL011_UARTCR_TXE | PL011_UARTCR_UARTEN;
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uart->cr = PL011_UARTCR_RXE | PL011_UARTCR_TXE | PL011_UARTCR_UARTEN;
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uart->imsc = PL011_RTI | PL011_RXI | PL011_RXI;
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}
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void uartWriteData(const void *buffer, size_t size)
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void uartWriteData(UartDevice dev, const void *buffer, size_t size)
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{
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volatile PL011UartRegisters *uart = uartGetRegisters(dev);
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const u8 *buf8 = (const u8 *)buffer;
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for (size_t i = 0; i < size; i++) {
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while (g_uartRegs->FR & PL011_UARTFR_TXFF); // while TX FIFO full
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g_uartRegs->DR = buf8[i];
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while (uart->fr & PL011_UARTFR_TXFF); // while TX FIFO full
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uart->dr = buf8[i];
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}
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}
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void uartReadData(void *buffer, size_t size)
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void uartReadData(UartDevice dev, void *buffer, size_t size)
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{
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volatile PL011UartRegisters *uart = uartGetRegisters(dev);
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u8 *buf8 = (u8 *)buffer;
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size_t i;
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for (i = 0; i < size; i++) {
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while (g_uartRegs->FR & PL011_UARTFR_RXFE);
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buf8[i] = g_uartRegs->DR;
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while (uart->fr & PL011_UARTFR_RXFE);
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buf8[i] = uart->dr;
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}
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}
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size_t uartReadDataMax(void *buffer, size_t maxSize)
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size_t uartReadDataMax(UartDevice dev, void *buffer, size_t maxSize)
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{
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volatile PL011UartRegisters *uart = uartGetRegisters(dev);
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u8 *buf8 = (u8 *)buffer;
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size_t i;
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for (i = 0; i < maxSize && !(g_uartRegs->FR & PL011_UARTFR_RXFE); i++) {
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buf8[i] = g_uartRegs->DR;
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for (i = 0; i < maxSize && !(uart->fr & PL011_UARTFR_RXFE); i++) {
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buf8[i] = uart->dr;
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}
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return 1 + i;
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}
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void uartSetInterruptStatus(UartDevice dev, bool read, bool enable)
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{
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volatile PL011UartRegisters *uart = uartGetRegisters(dev);
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u32 mask = read ? PL011_RTI | PL011_RXI : PL011_RTI;
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if (enable) {
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uart->imsc |= mask;
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} else {
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uart->icr = mask;
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uart->imsc &= ~mask;
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}
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}
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@ -16,120 +16,130 @@
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#pragma once
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#include "../../types.h"
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#include "../../utils.h"
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#include "interrupt_config.h"
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// AMBA PL011 driver
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// Originally from
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/*
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* Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#if 0
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/* PL011 Registers */
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#define UARTDR 0x000
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#define UARTRSR 0x004
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#define UARTECR 0x004
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#define UARTFR 0x018
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#define UARTIMSC 0x038
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#define UARTRIS 0x03C
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#define UARTICR 0x044
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typedef enum UartDevice {
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UART_A = 0,
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/* PL011 registers (out of the SBSA specification) */
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#if !PL011_GENERIC_UART
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#define UARTILPR 0x020
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#define UARTIBRD 0x024
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#define UARTFBRD 0x028
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#define UARTLCR_H 0x02C
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#define UARTCR 0x030
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#define UARTIFLS 0x034
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#define UARTMIS 0x040
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#define UARTDMACR 0x048
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#endif /* !PL011_GENERIC_UART */
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UART_MAX,
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} UartDevice;
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#endif
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typedef struct PL011UartRegisters {
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u32 DR;
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u32 dr;
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union {
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u32 SR;
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u32 ECR;
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u32 sr;
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u32 ecr;
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};
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u32 _0x08, _0x0C, _0x10, _0x14;
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u32 FR;
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u32 fr;
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u32 _0x1C;
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u32 ILPR;
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u32 IBRD;
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u32 FBRD;
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u32 LCR_H;
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u32 CR;
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u32 IFLS;
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u32 IMSC;
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u32 TRIS;
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u32 TMIS;
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u32 TICR;
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u32 TDMACR;
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u32 ilpr;
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u32 ibrd;
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u32 fbrd;
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u32 lcr_h;
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u32 cr;
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u32 ifls;
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u32 imsc;
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u32 ris;
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u32 mis;
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u32 icr;
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u32 dmacr;
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} PL011UartRegisters;
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/* Data status bits */
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// Data status bits
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#define UART_DATA_ERROR_MASK 0x0F00
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/* Status reg bits */
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// Status reg bits
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#define UART_STATUS_ERROR_MASK 0x0F
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/* Flag reg bits */
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#define PL011_UARTFR_RI (1 << 8) /* Ring indicator */
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#define PL011_UARTFR_TXFE (1 << 7) /* Transmit FIFO empty */
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#define PL011_UARTFR_RXFF (1 << 6) /* Receive FIFO full */
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#define PL011_UARTFR_TXFF (1 << 5) /* Transmit FIFO full */
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#define PL011_UARTFR_RXFE (1 << 4) /* Receive FIFO empty */
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#define PL011_UARTFR_BUSY (1 << 3) /* UART busy */
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#define PL011_UARTFR_DCD (1 << 2) /* Data carrier detect */
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#define PL011_UARTFR_DSR (1 << 1) /* Data set ready */
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#define PL011_UARTFR_CTS (1 << 0) /* Clear to send */
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// Errors
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#define PL011_OE BIT(3) // Overrun error
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#define PL011_BE BIT(2) // Break error
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#define PL011_PE BIT(1) // Parity error
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#define PL011_FE BIT(0) // Framing error
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#define PL011_UARTFR_TXFF_BIT 5 /* Transmit FIFO full bit in UARTFR register */
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#define PL011_UARTFR_RXFE_BIT 4 /* Receive FIFO empty bit in UARTFR register */
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#define PL011_UARTFR_BUSY_BIT 3 /* UART busy bit in UARTFR register */
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// Interrupts
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#define PL011_OEI BIT(10) // Overrun error interrupt
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#define PL011_BEI BIT(9) // Break error interrupt
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#define PL011_PEI BIT(8) // Parity error interrupt
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#define PL011_FEI BIT(7) // Framing error interrupt
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#define PL011_RTI BIT(6) // Receive timeout interrupt
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#define PL011_TXI BIT(5) // Transmit interrupt
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#define PL011_RXI BIT(4) // Receive interrupt
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#define PL011_DSRMI BIT(3) // DSR modem interrupt
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#define PL011_DCDMI BIT(2) // DCD modem interrupt
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#define PL011_CTSMI BIT(1) // CTS modem interrupt
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#define PL011_RIMI BIT(0) // RI modem interrupt
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#define PL011_ALL_INTERRUPTS MASK(11)
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/* Control reg bits */
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#if !PL011_GENERIC_UART
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#define PL011_UARTCR_CTSEN (1 << 15) /* CTS hardware flow control enable */
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#define PL011_UARTCR_RTSEN (1 << 14) /* RTS hardware flow control enable */
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#define PL011_UARTCR_RTS (1 << 11) /* Request to send */
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#define PL011_UARTCR_DTR (1 << 10) /* Data transmit ready. */
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#define PL011_UARTCR_RXE (1 << 9) /* Receive enable */
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#define PL011_UARTCR_TXE (1 << 8) /* Transmit enable */
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#define PL011_UARTCR_LBE (1 << 7) /* Loopback enable */
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#define PL011_UARTCR_UARTEN (1 << 0) /* UART Enable */
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// Flag reg bits
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#define PL011_UARTFR_RI BIT(8) // Ring indicator
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#define PL011_UARTFR_TXFE BIT(7) // Transmit FIFO empty
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#define PL011_UARTFR_RXFF BIT(6) // Receive FIFO full
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#define PL011_UARTFR_TXFF BIT(5) // Transmit FIFO full
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#define PL011_UARTFR_RXFE BIT(4) // Receive FIFO empty
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#define PL011_UARTFR_BUSY BIT(3) // UART busy
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#define PL011_UARTFR_DCD BIT(2) // Data carrier detect
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#define PL011_UARTFR_DSR BIT(1) // Data set ready
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#define PL011_UARTFR_CTS BIT(0) // Clear to send
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#if !defined(PL011_LINE_CONTROL)
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/* FIFO Enabled / No Parity / 8 Data bit / One Stop Bit */
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#define PL011_LINE_CONTROL (PL011_UARTLCR_H_FEN | PL011_UARTLCR_H_WLEN_8)
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#endif
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// Control reg bits
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#define PL011_UARTCR_CTSEN BIT(15) // CTS hardware flow control enable
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#define PL011_UARTCR_RTSEN BIT(14) // RTS hardware flow control enable
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#define PL011_UARTCR_RTS BIT(11) // Request to send
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#define PL011_UARTCR_DTR BIT(10) // Data transmit ready.
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#define PL011_UARTCR_RXE BIT(9) // Receive enable
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#define PL011_UARTCR_TXE BIT(8) // Transmit enable
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#define PL011_UARTCR_LBE BIT(7) // Loopback enable
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#define PL011_UARTCR_UARTEN BIT(0) // UART Enable
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/* Line Control Register Bits */
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#define PL011_UARTLCR_H_SPS (1 << 7) /* Stick parity select */
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// Line Control Register Bits
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#define PL011_UARTLCR_H_SPS BIT(7) // Stick parity select
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#define PL011_UARTLCR_H_WLEN_8 (3 << 5)
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#define PL011_UARTLCR_H_WLEN_7 (2 << 5)
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#define PL011_UARTLCR_H_WLEN_6 (1 << 5)
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#define PL011_UARTLCR_H_WLEN_6 BIT(5)
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#define PL011_UARTLCR_H_WLEN_5 (0 << 5)
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#define PL011_UARTLCR_H_FEN (1 << 4) /* FIFOs Enable */
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#define PL011_UARTLCR_H_STP2 (1 << 3) /* Two stop bits select */
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#define PL011_UARTLCR_H_EPS (1 << 2) /* Even parity select */
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#define PL011_UARTLCR_H_PEN (1 << 1) /* Parity Enable */
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#define PL011_UARTLCR_H_BRK (1 << 0) /* Send break */
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#define PL011_UARTLCR_H_FEN BIT(4) // FIFOs Enable
|
||||
#define PL011_UARTLCR_H_STP2 BIT(3) // Two stop bits select
|
||||
#define PL011_UARTLCR_H_EPS BIT(2) // Even parity select
|
||||
#define PL011_UARTLCR_H_PEN BIT(1) // Parity Enable
|
||||
#define PL011_UARTLCR_H_BRK BIT(0) // Send break
|
||||
|
||||
#endif /* !PL011_GENERIC_UART */
|
||||
// FIFO level select register
|
||||
#define PL011_IFLS_RX1_8 (0 << 3)
|
||||
#define PL011_IFLS_RX2_8 (1 << 3)
|
||||
#define PL011_IFLS_RX4_8 (2 << 3)
|
||||
#define PL011_IFLS_RX6_8 (3 << 3)
|
||||
#define PL011_IFLS_RX7_8 (4 << 3)
|
||||
#define PL011_IFLS_TX1_8 (0 << 0)
|
||||
#define PL011_IFLS_TX2_8 (1 << 0)
|
||||
#define PL011_IFLS_TX4_8 (2 << 0)
|
||||
#define PL011_IFLS_TX6_8 (3 << 0)
|
||||
#define PL011_IFLS_TX7_8 (4 << 0)
|
||||
|
||||
#define UART0_BASE 0x09000000
|
||||
#define UART1_BASE 0x09040000
|
||||
#define UART0_CLK_IN_HZ 1
|
||||
#define UART1_CLK_IN_HZ 1
|
||||
#define UART_CLK_IN_HZ 1
|
||||
|
||||
static volatile PL011UartRegisters *const g_uartRegs = (volatile PL011UartRegisters *)UART0_BASE;
|
||||
void uartInit(UartDevice dev, u32 baudRate, u32 flags);
|
||||
void uartWriteData(UartDevice dev, const void *buffer, size_t size);
|
||||
void uartReadData(UartDevice dev, void *buffer, size_t size);
|
||||
size_t uartReadDataMax(UartDevice dev, void *buffer, size_t maxSize);
|
||||
void uartSetInterruptStatus(UartDevice dev, bool read, bool enable);
|
||||
|
||||
void uartInit(u32 baudRate);
|
||||
void uartWriteData(const void *buffer, size_t size);
|
||||
void uartReadData(void *buffer, size_t size);
|
||||
size_t uartReadDataMax(void *buffer, size_t maxSize);
|
||||
static inline u16 uartGetIrqId(UartDevice dev)
|
||||
{
|
||||
switch (dev) {
|
||||
case UART_A:
|
||||
return GIC_IRQID_UART;
|
||||
default:
|
||||
return GIC_IRQID_SPURIOUS;
|
||||
}
|
||||
}
|
|
@ -16,8 +16,10 @@
|
|||
|
||||
#pragma once
|
||||
|
||||
#ifdef PLATFORM_TEGRA
|
||||
#include "tegra/uart.h"
|
||||
#if PLATFORM_TEGRA
|
||||
// TODO
|
||||
|
||||
/*#include "tegra/uart.h"
|
||||
|
||||
#define DEFAULT_UART UART_C
|
||||
#define DEFAULT_UARTINV_STATUS true
|
||||
|
@ -42,9 +44,12 @@ static inline size_t uartReadDataMax(void *buffer, size_t maxSize)
|
|||
{
|
||||
return uart_recv_max(DEFAULT_UART, buffer, maxSize);
|
||||
}
|
||||
*/
|
||||
|
||||
#elif defined(PLATFORM_QEMU)
|
||||
|
||||
#define DEFAULT_UART UART_A
|
||||
|
||||
#include "qemu/uart.h"
|
||||
|
||||
#else
|
||||
|
|
Loading…
Reference in a new issue