mirror of
https://github.com/Atmosphere-NX/Atmosphere
synced 2024-12-22 12:21:18 +00:00
Boot: Fleshing out more low level stuff
Add register read/write for 2.0.0+ (with svcReadWriteRegister) Add hardware type recognition Implement PMC clock out configuration Implement PINMUX park updating
This commit is contained in:
hexkyz
GitHub
parent
7df879d346
commit
a39ad22841
1 changed files with 286 additions and 18 deletions
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@ -11,6 +11,7 @@
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#define PINMUX_BASE (APB_MISC_BASE + 0x3000)
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#define PMC_BASE 0x7000E400
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#define MAX_GPIOS 0x3D
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#define MAX_PINMUX 0xA2
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extern "C" {
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extern u32 __start__;
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@ -41,7 +42,7 @@ void __libnx_initheap(void) {
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void __appInit(void) {
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Result rc;
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/* Initialize services we need (TODO: SPL, NCM) */
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/* Initialize services we need (TODO: NCM) */
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rc = smInitialize();
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if (R_FAILED(rc))
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fatalSimple(MAKERESULT(Module_Libnx, LibnxError_InitFail_SM));
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@ -50,10 +51,14 @@ void __appInit(void) {
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if (R_FAILED(rc))
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fatalSimple(MAKERESULT(Module_Libnx, LibnxError_InitFail_FS));
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rc = pmshellInitialize();
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rc = splInitialize();
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if (R_FAILED(rc))
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fatalSimple(0xCAFE << 4 | 1);
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rc = pmshellInitialize();
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if (R_FAILED(rc))
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fatalSimple(0xCAFE << 4 | 2);
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fsdevInit();
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}
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@ -61,11 +66,13 @@ void __appExit(void) {
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/* Cleanup services. */
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fsdevExit();
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pmshellExit();
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splExit();
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fsExit();
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smExit();
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}
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static const std::tuple<u32, bool, bool> g_gpio_map[] = {
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/* Icosa, Copper, Hoag and Mariko */
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{0xFFFFFFFF, false, false}, /* Invalid */
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{0x000000CC, true, false}, /* Port Z, Pin 4 */
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{0x00000024, true, false}, /* Port E, Pin 4 */
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@ -127,22 +134,31 @@ static const std::tuple<u32, bool, bool> g_gpio_map[] = {
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{0x00000058, true, false}, /* Port L, Pin 0 */
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{0x0000003E, false, false}, /* Port H, Pin 6 */
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{0x00000026, false, false}, /* Port E, Pin 6 */
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/* Copper only */
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{0xFFFFFFFF, false, false}, /* Invalid */
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{0x00000033, false, false}, /* Port G, Pin 3 */
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{0x0000001C, false, false}, /* Port D, Pin 4 */
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{0x000000D9, false, false}, /* Port BB, Pin 1 */
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{0x000000D9, true, false}, /* Port BB, Pin 1 */
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{0x0000000C, false, false}, /* Port B, Pin 4 */
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{0x0000000D, false, false}, /* Port B, Pin 5 */
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{0x00000021, false, false}, /* Port E, Pin 1 */
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{0x00000021, true, false}, /* Port E, Pin 1 */
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{0x00000027, false, false}, /* Port E, Pin 7 */
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{0x00000092, false, false}, /* Port S, Pin 2 */
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{0x00000095, false, false}, /* Port S, Pin 5 */
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{0x00000098, false, false}, /* Port T, Pin 0 */
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{0x00000010, false, false}, /* Port C, Pin 0 */
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{0x00000011, false, false}, /* Port C, Pin 1 */
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{0x00000012, false, false}, /* Port C, Pin 2 */
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{0x00000042, false, false}, /* Port I, Pin 2 */
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{0x00000095, true, false}, /* Port S, Pin 5 */
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{0x00000098, true, false}, /* Port T, Pin 0 */
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{0x00000010, true, false}, /* Port C, Pin 0 */
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{0x00000011, true, false}, /* Port C, Pin 1 */
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{0x00000012, true, false}, /* Port C, Pin 2 */
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{0x00000042, true, false}, /* Port I, Pin 2 */
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{0x000000E6, false, false}, /* Port CC, Pin 6 */
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/* 2.0.0+ Copper only */
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{0x000000AC, true, false}, /* Port V, Pin 4 */
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{0x000000E1, false, false}, /* Port CC, Pin 1 */
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/* 5.0.0+ Copper only (unused) */
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{0x00000056, false, false}, /* Port K, Pin 6 */
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};
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static int gpio_configure(u64 gpio_base_vaddr, unsigned int gpio_pad_name) {
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@ -174,7 +190,7 @@ static int gpio_set_direction(u64 gpio_base_vaddr, unsigned int gpio_pad_name) {
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/* Convert the GPIO pad descriptor into its register offset */
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u32 gpio_reg_offset = (((gpio_pad_desc << 0x03) & 0xFFFFFF00) | ((gpio_pad_desc >> 0x01) & 0x0C));
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/* Set the direction bit and lock values (bug?) */
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/* Set the direction bit and lock values */
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u32 gpio_oe_val = ((0x01 << ((gpio_pad_desc & 0x07) | 0x08)) | (is_out << (gpio_pad_desc & 0x07)));
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/* Write to the appropriate GPIO_OE_x register (upper offset) */
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@ -186,7 +202,7 @@ static int gpio_set_direction(u64 gpio_base_vaddr, unsigned int gpio_pad_name) {
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return gpio_oe_val;
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}
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static int gpio_set_output(u64 gpio_base_vaddr, unsigned int gpio_pad_name) {
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static int gpio_set_value(u64 gpio_base_vaddr, unsigned int gpio_pad_name) {
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/* Fetch this GPIO's pad descriptor */
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u32 gpio_pad_desc = std::get<0>(g_gpio_map[gpio_pad_name]);
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@ -196,7 +212,7 @@ static int gpio_set_output(u64 gpio_base_vaddr, unsigned int gpio_pad_name) {
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/* Convert the GPIO pad descriptor into its register offset */
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u32 gpio_reg_offset = (((gpio_pad_desc << 0x03) & 0xFFFFFF00) | ((gpio_pad_desc >> 0x01) & 0x0C));
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/* Set the output bit and lock values (bug?) */
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/* Set the output bit and lock values */
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u32 gpio_out_val = ((0x01 << ((gpio_pad_desc & 0x07) | 0x08)) | (is_high << (gpio_pad_desc & 0x07)));
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/* Write to the appropriate GPIO_OUT_x register (upper offset) */
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@ -208,6 +224,198 @@ static int gpio_set_output(u64 gpio_base_vaddr, unsigned int gpio_pad_name) {
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return gpio_out_val;
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}
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static const std::tuple<u32, u32, u8> g_pinmux_map[] = {
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{0x00003000, 0x72FF, 0x01}, /* Sdmmc1Clk */
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{0x00003004, 0x72FF, 0x02}, /* Sdmmc1Cmd */
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{0x00003008, 0x72FF, 0x02}, /* Sdmmc1Dat3 */
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{0x0000300C, 0x72FF, 0x02}, /* Sdmmc1Dat2 */
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{0x00003010, 0x72FF, 0x02}, /* Sdmmc1Dat1 */
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{0x00003014, 0x72FF, 0x01}, /* Sdmmc1Dat0 */
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{0x0000301C, 0x72FF, 0x01}, /* Sdmmc3Clk */
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{0x00003020, 0x72FF, 0x01}, /* Sdmmc3Cmd */
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{0x00003024, 0x72FF, 0x01}, /* Sdmmc3Dat0 */
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{0x00003028, 0x72FF, 0x01}, /* Sdmmc3Dat1 */
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{0x0000302C, 0x72FF, 0x01}, /* Sdmmc3Dat2 */
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{0x00003030, 0x72FF, 0x01}, /* Sdmmc3Dat3 */
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{0x00003038, 0x1DFF, 0x01}, /* PexL0RstN */
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{0x0000303C, 0x1DFF, 0x01}, /* PexL0ClkreqN */
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{0x00003040, 0x1DFF, 0x01}, /* PexWakeN */
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{0x00003044, 0x1DFF, 0x01}, /* PexL1RstN */
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{0x00003048, 0x1DFF, 0x01}, /* PexL1ClkreqN */
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{0x0000304C, 0x19FF, 0x01}, /* SataLedActive */
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{0x00003050, 0x1F2FF, 0x01}, /* Spi1Mosi */
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{0x00003054, 0x1F2FF, 0x01}, /* Spi1Miso */
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{0x00003058, 0x1F2FF, 0x01}, /* Spi1Sck */
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{0x0000305C, 0x1F2FF, 0x01}, /* Spi1Cs0 */
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{0x00003060, 0x1F2FF, 0x01}, /* Spi1Cs1 */
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{0x00003064, 0x72FF, 0x02}, /* Spi2Mosi */
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{0x00003068, 0x72FF, 0x02}, /* Spi2Miso */
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{0x0000306C, 0x72FF, 0x02}, /* Spi2Sck */
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{0x00003070, 0x72FF, 0x02}, /* Spi2Cs0 */
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{0x00003074, 0x72FF, 0x01}, /* Spi2Cs1 */
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{0x00003078, 0x1F2FF, 0x01}, /* Spi4Mosi */
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{0x0000307C, 0x1F2FF, 0x01}, /* Spi4Miso */
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{0x00003080, 0x1F2FF, 0x01}, /* Spi4Sck */
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{0x00003084, 0x1F2FF, 0x01}, /* Spi4Cs0 */
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{0x00003088, 0x72FF, 0x01}, /* QspiSck */
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{0x0000308C, 0x72FF, 0x01}, /* QspiCsN */
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{0x00003090, 0x72FF, 0x01}, /* QspiIo0 */
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{0x00003094, 0x72FF, 0x01}, /* QspiIo1 */
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{0x00003098, 0x72FF, 0x01}, /* QspiIo2 */
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{0x0000309C, 0x72FF, 0x01}, /* QspiIo3 */
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{0x000030A4, 0x19FF, 0x02}, /* Dmic1Clk */
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{0x000030A8, 0x19FF, 0x02}, /* Dmic1Dat */
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{0x000030AC, 0x19FF, 0x02}, /* Dmic2Clk */
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{0x000030B0, 0x19FF, 0x02}, /* Dmic2Dat */
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{0x000030B4, 0x19FF, 0x02}, /* Dmic3Clk */
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{0x000030B8, 0x19FF, 0x02}, /* Dmic3Dat */
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{0x000030BC, 0x1DFF, 0x01}, /* Gen1I2cScl */
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{0x000030C0, 0x1DFF, 0x01}, /* Gen1I2cSda */
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{0x000030C4, 0x1DFF, 0x01}, /* Gen2I2cScl */
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{0x000030C8, 0x1DFF, 0x01}, /* Gen2I2cSda */
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{0x000030CC, 0x1DFF, 0x01}, /* Gen3I2cScl */
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{0x000030D0, 0x1DFF, 0x01}, /* Gen3I2cSda */
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{0x000030D4, 0x1DFF, 0x02}, /* CamI2cScl */
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{0x000030D8, 0x1DFF, 0x02}, /* CamI2cSda */
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{0x000030DC, 0x1DFF, 0x01}, /* PwrI2cScl */
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{0x000030E0, 0x1DFF, 0x01}, /* PwrI2cSda */
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{0x000030E4, 0x19FF, 0x01}, /* Uart1Tx */
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{0x000030E8, 0x19FF, 0x01}, /* Uart1Rx */
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{0x000030EC, 0x19FF, 0x01}, /* Uart1Rts */
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{0x000030F0, 0x19FF, 0x01}, /* Uart1Cts */
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{0x000030F4, 0x19FF, 0x00}, /* Uart2Tx */
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{0x000030F8, 0x19FF, 0x00}, /* Uart2Rx */
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{0x000030FC, 0x19FF, 0x02}, /* Uart2Rts */
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{0x00003100, 0x19FF, 0x02}, /* Uart2Cts */
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{0x00003104, 0x19FF, 0x02}, /* Uart3Tx */
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{0x00003108, 0x19FF, 0x02}, /* Uart3Rx */
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{0x0000310C, 0x19FF, 0x02}, /* Uart3Rts */
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{0x00003110, 0x19FF, 0x02}, /* Uart3Cts */
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{0x00003114, 0x19FF, 0x02}, /* Uart4Tx */
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{0x00003118, 0x19FF, 0x02}, /* Uart4Rx */
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{0x0000311C, 0x19FF, 0x02}, /* Uart4Rts */
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{0x00003120, 0x19FF, 0x02}, /* Uart4Cts */
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{0x00003124, 0x72FF, 0x01}, /* Dap1Fs */
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{0x00003128, 0x72FF, 0x01}, /* Dap1Din */
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{0x0000312C, 0x72FF, 0x01}, /* Dap1Dout */
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{0x00003130, 0x72FF, 0x01}, /* Dap1Sclk */
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{0x00003134, 0x72FF, 0x01}, /* Dap2Fs */
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{0x00003138, 0x72FF, 0x01}, /* Dap2Din */
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{0x0000313C, 0x72FF, 0x01}, /* Dap2Dout */
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{0x00003140, 0x72FF, 0x01}, /* Dap2Sclk */
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{0x00003144, 0x72FF, 0x01}, /* Dap4Fs */
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{0x00003148, 0x72FF, 0x01}, /* Dap4Din */
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{0x0000314C, 0x72FF, 0x01}, /* Dap4Dout */
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{0x00003150, 0x72FF, 0x01}, /* Dap4Sclk */
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{0x00003154, 0x72FF, 0x01}, /* Cam1Mclk */
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{0x00003158, 0x72FF, 0x01}, /* Cam2Mclk */
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{0x0000315C, 0x72FF, 0x01}, /* JtagRtck */
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{0x00003160, 0x118C, 0xFF}, /* Clk32kIn */
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{0x00003164, 0x72FF, 0x02}, /* Clk32kOut */
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{0x00003168, 0x1DFF, 0x01}, /* BattBcl */
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{0x0000316C, 0x11CC, 0xFF}, /* ClkReq */
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{0x00003170, 0x11CC, 0xFF}, /* CpuPwrReq */
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{0x00003174, 0x11CC, 0xFF}, /* PwrIntN */
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{0x00003178, 0x11CC, 0xFF}, /* Shutdown */
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{0x0000317C, 0x11CC, 0xFF}, /* CorePwrReq */
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{0x00003180, 0x19FF, 0x01}, /* AudMclk */
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{0x00003184, 0x19FF, 0x00}, /* DvfsPwm */
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{0x00003188, 0x19FF, 0x00}, /* DvfsClk */
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{0x0000318C, 0x19FF, 0x00}, /* GpioX1Aud */
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{0x00003190, 0x19FF, 0x00}, /* GpioX3Aud */
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{0x00003194, 0x1DFF, 0x00}, /* GpioPcc7 */
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{0x00003198, 0x1DFF, 0x01}, /* HdmiCec */
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{0x0000319C, 0x1DFF, 0x01}, /* HdmiIntDpHpd */
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{0x000031A0, 0x19FF, 0x01}, /* SpdifOut */
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{0x000031A4, 0x19FF, 0x01}, /* SpdifIn */
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{0x000031A8, 0x1DFF, 0x01}, /* UsbVbusEn0 */
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{0x000031AC, 0x1DFF, 0x01}, /* UsbVbusEn1 */
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{0x000031B0, 0x19FF, 0x01}, /* DpHpd0 */
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{0x000031B4, 0x19FF, 0x00}, /* WifiEn */
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{0x000031B8, 0x19FF, 0x00}, /* WifiRst */
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{0x000031BC, 0x19FF, 0x00}, /* WifiWakeAp */
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{0x000031C0, 0x19FF, 0x00}, /* ApWakeBt */
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{0x000031C4, 0x19FF, 0x00}, /* BtRst */
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{0x000031C8, 0x19FF, 0x00}, /* BtWakeAp */
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{0x000031CC, 0x19FF, 0x00}, /* ApWakeNfc */
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{0x000031D0, 0x19FF, 0x00}, /* NfcEn */
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{0x000031D4, 0x19FF, 0x00}, /* NfcInt */
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{0x000031D8, 0x19FF, 0x00}, /* GpsEn */
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{0x000031DC, 0x19FF, 0x00}, /* GpsRst */
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{0x000031E0, 0x19FF, 0x01}, /* CamRst */
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{0x000031E4, 0x19FF, 0x02}, /* CamAfEn */
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{0x000031E8, 0x19FF, 0x02}, /* CamFlashEn */
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{0x000031EC, 0x19FF, 0x01}, /* Cam1Pwdn */
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{0x000031F0, 0x19FF, 0x01}, /* Cam2Pwdn */
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{0x000031F4, 0x19FF, 0x01}, /* Cam1Strobe */
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{0x000031F8, 0x19FF, 0x01}, /* LcdTe */
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{0x000031FC, 0x19FF, 0x03}, /* LcdBlPwm */
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{0x00003200, 0x19FF, 0x00}, /* LcdBlEn */
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{0x00003204, 0x19FF, 0x00}, /* LcdRst */
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{0x00003208, 0x19FF, 0x01}, /* LcdGpio1 */
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{0x0000320C, 0x19FF, 0x02}, /* LcdGpio2 */
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{0x00003210, 0x19FF, 0x00}, /* ApReady */
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{0x00003214, 0x19FF, 0x00}, /* TouchRst */
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{0x00003218, 0x19FF, 0x01}, /* TouchClk */
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{0x0000321C, 0x19FF, 0x00}, /* ModemWakeAp */
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{0x00003220, 0x19FF, 0x00}, /* TouchInt */
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{0x00003224, 0x19FF, 0x00}, /* MotionInt */
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{0x00003228, 0x19FF, 0x00}, /* AlsProxInt */
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{0x0000322C, 0x19FF, 0x00}, /* TempAlert */
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{0x00003230, 0x19FF, 0x00}, /* ButtonPowerOn */
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{0x00003234, 0x19FF, 0x00}, /* ButtonVolUp */
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{0x00003238, 0x19FF, 0x00}, /* ButtonVolDown */
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{0x0000323C, 0x19FF, 0x00}, /* ButtonSlideSw */
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{0x00003240, 0x19FF, 0x00}, /* ButtonHome */
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{0x00003244, 0x19FF, 0x01}, /* GpioPa6 */
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{0x00003248, 0x19FF, 0x00}, /* GpioPe6 */
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{0x0000324C, 0x19FF, 0x00}, /* GpioPe7 */
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{0x00003250, 0x19FF, 0x00}, /* GpioPh6 */
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{0x00003254, 0x72FF, 0x02}, /* GpioPk0 */
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{0x00003258, 0x72FF, 0x02}, /* GpioPk1 */
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{0x0000325C, 0x72FF, 0x02}, /* GpioPk2 */
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{0x00003260, 0x72FF, 0x02}, /* GpioPk3 */
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{0x00003264, 0x72FF, 0x01}, /* GpioPk4 */
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{0x00003268, 0x72FF, 0x01}, /* GpioPk5 */
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{0x0000326C, 0x72FF, 0x01}, /* GpioPk6 */
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{0x00003270, 0x72FF, 0x01}, /* GpioPk7 */
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{0x00003274, 0x72FF, 0x00}, /* GpioPl0 */
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{0x00003278, 0x72FF, 0x01}, /* GpioPl1 */
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{0x0000327C, 0x72FF, 0x01}, /* GpioPz0 */
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{0x00003280, 0x72FF, 0x02}, /* GpioPz1 */
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{0x00003284, 0x72FF, 0x02}, /* GpioPz2 */
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{0x00003288, 0x72FF, 0x01}, /* GpioPz3 */
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{0x0000328C, 0x72FF, 0x01}, /* GpioPz4 */
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{0x00003290, 0x72FF, 0x01}, /* GpioPz5 */
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};
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static int pinmux_update_park(u64 pinmux_base_vaddr, unsigned int pinmux_idx) {
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/* Fetch this PINMUX's register offset */
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u32 pinmux_reg_offset = std::get<0>(g_pinmux_map[pinmux_idx]);
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/* Fetch this PINMUX's mask value */
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u32 pinmux_mask_val = std::get<1>(g_pinmux_map[pinmux_idx]);
|
||||
|
||||
/* Read from the PINMUX register */
|
||||
u32 pinmux_val = *((u32 *)pinmux_base_vaddr + pinmux_reg_offset);
|
||||
|
||||
/* This PINMUX supports park change */
|
||||
if (pinmux_mask_val & 0x20) {
|
||||
/* Clear park status if set */
|
||||
if (pinmux_val & 0x20) {
|
||||
pinmux_val &= ~(0x20);
|
||||
}
|
||||
}
|
||||
|
||||
/* Write to the appropriate PINMUX register */
|
||||
*((u32 *)pinmux_base_vaddr + pinmux_reg_offset) = pinmux_val;
|
||||
|
||||
/* Do a dummy read from the PINMUX register */
|
||||
pinmux_val = *((u32 *)pinmux_base_vaddr + pinmux_reg_offset);
|
||||
|
||||
return pinmux_val;
|
||||
}
|
||||
|
||||
int main(int argc, char **argv)
|
||||
{
|
||||
consoleDebugInit(debugDevice_SVC);
|
||||
|
|
@ -239,7 +447,19 @@ int main(int argc, char **argv)
|
|||
|
||||
/* Change GPIO voltage to 1.8v */
|
||||
if (kernelAbove200()) {
|
||||
/* TODO: svcReadWriteRegister */
|
||||
u32 rw_reg_val = 0;
|
||||
|
||||
/* Use svcReadWriteRegister to write APBDEV_PMC_PWR_DET_0 */
|
||||
rc = svcReadWriteRegister(&rw_reg_val, PMC_BASE + 0x48, 0xA42000, 0xA42000);
|
||||
if (R_FAILED(rc)) {
|
||||
return rc;
|
||||
}
|
||||
|
||||
/* Use svcReadWriteRegister to write APBDEV_PMC_PWR_DET_VAL_0 */
|
||||
rc = svcReadWriteRegister(&rw_reg_val, PMC_BASE + 0xE4, 0, 0xA42000);
|
||||
if (R_FAILED(rc)) {
|
||||
return rc;
|
||||
}
|
||||
} else {
|
||||
/* Map the PMC registers directly */
|
||||
rc = svcQueryIoMapping(&pmc_base_vaddr, PMC_BASE, 0x3000);
|
||||
|
|
@ -252,10 +472,10 @@ int main(int argc, char **argv)
|
|||
fatalSimple(MAKERESULT(Module_Libnx, LibnxError_IoError));
|
||||
|
||||
/* Write to APBDEV_PMC_PWR_DET_0 */
|
||||
*((u32 *)pmc_base_vaddr + 0x48) |= 0x00A42000;
|
||||
*((u32 *)pmc_base_vaddr + 0x48) |= 0xA42000;
|
||||
|
||||
/* Write to APBDEV_PMC_PWR_DET_VAL_0 */
|
||||
*((u32 *)pmc_base_vaddr + 0xE4) &= 0xFF5BDFFF;
|
||||
*((u32 *)pmc_base_vaddr + 0xE4) &= ~(0xA42000);
|
||||
}
|
||||
|
||||
/* Wait for changes to take effect */
|
||||
|
|
@ -265,10 +485,58 @@ int main(int argc, char **argv)
|
|||
for (unsigned int i = 1; i < MAX_GPIOS; i++) {
|
||||
gpio_configure(gpio_base_vaddr, i);
|
||||
gpio_set_direction(gpio_base_vaddr, i);
|
||||
gpio_set_output(gpio_base_vaddr, i);
|
||||
gpio_set_value(gpio_base_vaddr, i);
|
||||
}
|
||||
|
||||
/* TODO: Hardware setup, NAND repair, NotifyBootFinished */
|
||||
u64 hardware_type = 0;
|
||||
|
||||
/* Get the hardware type from SPL */
|
||||
rc = splGetConfig(SplConfigItem_HardwareType, &hardware_type);
|
||||
if (R_FAILED(rc)) {
|
||||
return rc;
|
||||
}
|
||||
|
||||
/* This is ignored in Copper hardware */
|
||||
if (hardware_type != 0x01) {
|
||||
/* TODO: Battery charge check */
|
||||
}
|
||||
|
||||
/* Update PINMUX park status */
|
||||
for (unsigned int i = 0; i < MAX_PINMUX; i++) {
|
||||
pinmux_update_park(pinmux_base_vaddr, i);
|
||||
}
|
||||
|
||||
/* TODO: Set initial PINMUX configuration */
|
||||
/* TODO: Set initial PINMUX drive pad configuration */
|
||||
/* TODO: Set initial wake pin configuration */
|
||||
|
||||
/* This is ignored in Copper hardware */
|
||||
if (hardware_type != 0x01) {
|
||||
/* Configure PMC clock out */
|
||||
if (kernelAbove200()) {
|
||||
u32 rw_reg_val = 0;
|
||||
|
||||
/* Use svcReadWriteRegister to write APBDEV_PMC_CLK_OUT_CNTRL_0 */
|
||||
rc = svcReadWriteRegister(&rw_reg_val, PMC_BASE + 0x1A8, 0xC4, 0xC4);
|
||||
if (R_FAILED(rc)) {
|
||||
return rc;
|
||||
}
|
||||
} else {
|
||||
/* Write to APBDEV_PMC_CLK_OUT_CNTRL_0 */
|
||||
*((u32 *)pmc_base_vaddr + 0x1A8) |= 0xC4;
|
||||
}
|
||||
}
|
||||
|
||||
/* Setup GPIO 0x4B for Copper hardware only */
|
||||
if (hardware_type == 0x01) {
|
||||
gpio_configure(gpio_base_vaddr, 0x4B);
|
||||
gpio_set_direction(gpio_base_vaddr, 0x4B);
|
||||
gpio_set_value(gpio_base_vaddr, 0x4B);
|
||||
}
|
||||
|
||||
/* TODO: NAND repair */
|
||||
|
||||
/* pmshellNotifyBootFinished(); */
|
||||
|
||||
rc = 0;
|
||||
return rc;
|
||||
|
|
|
|||
Loading…
Reference in a new issue