mirror of
https://github.com/Atmosphere-NX/Atmosphere
synced 2024-11-09 22:56:35 +00:00
Fix bpmpfw/Makefile, other changes.
This commit is contained in:
TuxSH
parent
90f792b1cc
commit
91d1b047c4
5 changed files with 63 additions and 67 deletions
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@ -12,24 +12,23 @@ dir_source := src
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dir_build := build
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dir_out := out
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ASFLAGS :=
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ARCH := -march=armv4t -mtune=arm7tdmi -mthumb -mthumb-interwork
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ASFLAGS := -g $(ARCH)
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CFLAGS = \
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-Iinclude \
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-Iinclude/compat \
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-march=armv8-a \
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-mlittle-endian \
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-fno-stack-protector \
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-fno-common \
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-fno-builtin \
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-fno-inline \
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-ffreestanding \
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-std=gnu99 \
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$(ARCH) \
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-g \
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-O2 \
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-ffunction-sections \
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-fdata-sections \
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-fomit-frame-pointer \
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-fno-inline \
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-std=gnu11 \
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-Werror \
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-Wall \
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-Wno-error=unused-variable
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LDFLAGS := -nostartfiles -Wl,--nmagic
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-Wall
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LDFLAGS = -g $(ARCH) -nostartfiles -nostdlib -Wl,--nmagic,--gc-sections
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objects = $(patsubst $(dir_source)/%.s, $(dir_build)/%.o, \
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$(patsubst $(dir_source)/%.c, $(dir_build)/%.o, \
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@ -59,4 +58,4 @@ $(dir_build)/%.o: $(dir_source)/%.c
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$(dir_build)/%.o: $(dir_source)/%.s
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@mkdir -p "$(@D)"
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$(COMPILE.s) $(OUTPUT_OPTION) $<
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$(COMPILE.c) -x assembler-with-cpp $(OUTPUT_OPTION) $<
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@ -5,7 +5,7 @@
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#include "pmc.h"
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#include "timer.h"
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void emc_trigger_timing_update(void) {
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static void emc_trigger_timing_update(void) {
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EMC_TIMING_CONTROL_0 = 1;
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while (EMC_EMC_STATUS_0 & 0x800000) {
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/* Wait until TIMING_UPDATE_STALLED is unset. */
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@ -18,16 +18,16 @@ void emc_put_dram_in_self_refresh_mode(void) {
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if (!(EMC_FBIO_CFG7_0 & 4)) {
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reboot();
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}
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/* Clear config. */
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EMC_CFG_0 = 0;
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emc_trigger_timing_update();
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timer_wait(5);
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/* Set calibration intervals. */
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EMC_ZCAL_INTERVAL_0 = 0;
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EMC_AUTO_CAL_CONFIG_0 = 0x600; /* AUTO_CAL_MEASURE_STALL | AUTO_CAL_UPDATE_STALL */
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/* If EMC0 mirror is set, clear digital DLL. */
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if (EMC0_CFG_DIG_DLL_0 & 1) {
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EMC_CFG_DIG_DLL_0 &= 0xFFFFFFFE;
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@ -37,22 +37,22 @@ void emc_put_dram_in_self_refresh_mode(void) {
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} else {
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emc_trigger_timing_update();
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}
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/* Stall all transactions to DRAM. */
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EMC_REQ_CTRL_0 = 3; /* STALL_ALL_WRITES | STALL_ALL_READS. */
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while (!(EMC0_EMC_STATUS_0 & 4)) { /* Wait for NO_OUTSTANDING_TRANSACTIONS for EMC0. */ }
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while (!(EMC1_EMC_STATUS_0 & 4)) { /* Wait for NO_OUTSTANDING_TRANSACTIONS for EMC1. */ }
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/* Enable Self-Refresh Mode. */
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EMC_SELF_REF_0 |= 1;
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/* Wait until we see the right devices in self refresh mode. */
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uint32_t num_populated_devices = 1;
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if (EMC_ADR_CFG_0) {
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num_populated_devices = 3;
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}
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while (((EMC0_EMC_STATUS_0 >> 8) & 3) != num_populated_devices) { /* Wait for EMC0 DRAM_IN_SELF_REFRESH to be correct. */ }
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while (((EMC1_EMC_STATUS_0 >> 8) & 3) != num_populated_devices) { /* Wait for EMC1 DRAM_IN_SELF_REFRESH to be correct. */ }
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}
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}
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@ -5,7 +5,7 @@
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void i2c_load_config(void) {
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/* Set MSTR_CONFIG_LOAD, TIMEOUT_CONFIG_LOAD, undocumented bit. */
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I2C_I2C_CONFIG_LOAD_0 = 0x25;
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/* Wait a bit for master config to be loaded. */
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for (unsigned int i = 0; i < 20; i++) {
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timer_wait(1);
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@ -20,10 +20,10 @@ void i2c_init(void) {
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/* Setup divisor, and clear the bus. */
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I2C_I2C_CLK_DIVISOR_REGISTER_0 = 0x50001;
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I2C_I2C_BUS_CLEAR_CONFIG_0 = 0x90003;
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/* Load hardware configuration. */
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i2c_load_config();
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/* Wait a while until BUS_CLEAR_DONE is set. */
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for (unsigned int i = 0; i < 10; i++) {
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timer_wait(20000);
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@ -31,10 +31,10 @@ void i2c_init(void) {
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break;
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}
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}
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/* Read the BUS_CLEAR_STATUS. Result doesn't matter. */
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uint32_t unused_clear_status = I2C_I2C_BUS_CLEAR_STATUS_0;
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I2C_I2C_BUS_CLEAR_STATUS_0;
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/* Read and set the Interrupt Status. */
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uint32_t int_status = I2C_INTERRUPT_STATUS_REGISTER_0;
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I2C_INTERRUPT_STATUS_REGISTER_0 = int_status;
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@ -45,26 +45,26 @@ int i2c_write(unsigned int device, uint32_t val, unsigned int num_bytes) {
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if (num_bytes > 4) {
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return 0;
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}
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/* Set device for 7-bit mode. */
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I2C_I2C_CMD_ADDR0_0 = device << 1;
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/* Load in data to write. */
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I2C_I2C_CMD_DATA1_0 = val;
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/* Set config with LENGTH = num_bytes, NEW_MASTER_FSM, DEBOUNCE_CNT = 4T. */
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I2C_I2C_CNFG_0 = ((num_bytes << 1) - 2) | 0x2800;
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i2c_load_config();
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/* Config |= SEND; */
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I2C_I2C_CNFG_0 |= 0x200;
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while (I2C_I2C_STATUS_0 & 0x100) {
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/* Wait until not busy. */
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}
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/* Return CMD1_STAT == SL1_XFER_SUCCESSFUL. */
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return (I2C_I2C_STATUS_0 & 7) == 0;
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}
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@ -80,4 +80,4 @@ int i2c_send_byte_command(unsigned int device, unsigned char reg, unsigned char
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int i2c_send_reset_cmd(void) {
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/* Write 00 to Device 27 Reg 00. */
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return i2c_send_byte_command(27, 0, 0);
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}
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}
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@ -1,4 +1,5 @@
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#include <stdint.h>
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#include <stdbool.h>
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#include "lp0.h"
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#include "i2c.h"
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@ -18,13 +19,13 @@
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void reboot(void) {
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/* Write MAIN_RST */
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APBDEV_PMC_CNTRL_0 = 0x10;
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while (1) {
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while (true) {
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/* Wait for reboot. */
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}
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}
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void set_pmc_dpd_io_pads(void) {
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static void set_pmc_dpd_io_pads(void) {
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/* Read val from EMC_PMC scratch, configure accordingly. */
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uint32_t emc_pmc_val = EMC_PMC_SCRATCH3_0;
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APBDEV_PMC_DDR_CNTRL_0 = emc_pmc_val & 0x7FFFF;
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@ -43,22 +44,22 @@ void set_pmc_dpd_io_pads(void) {
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void lp0_entry_main(void) {
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/* Disable the BPMP Cache. */
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CACHE_CTRL |= 0xC00;
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/* Wait until the CPU Rail is turned off. */
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while (APBDEV_PMC_PWRGATE_STATUS_0 & 1) { /* Wait for TrustZone to finish. */ }
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/* Clamp the CPU Rail. */
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APBDEV_PMC_SET_SW_CLAMP_0 |= 0x1;
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while (!(APBDEV_PMC_CLAMP_STATUS_0 & 1)) { /* Wait for CPU Rail to be clamped. */ }
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/* Waste some time. */
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spinlock_wait(10);
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/* Reset device 27 over I2C, then wait a while. */
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i2c_init();
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i2c_send_reset_cmd();
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timer_wait(700);
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/* Clear Interrupt Enable for BPMP in all ICTLRs. */
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PRI_ICTLR_COP_IER_CLR_0 = 0xFFFFFFFF;
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SEC_ICTLR_COP_IER_CLR_0 = 0xFFFFFFFF;
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@ -66,7 +67,7 @@ void lp0_entry_main(void) {
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QUAD_ICTLR_COP_IER_CLR_0 = 0xFFFFFFFF;
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PENTA_ICTLR_COP_IER_CLR_0 = 0xFFFFFFFF;
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HEXA_ICTLR_COP_IER_CLR_0 = 0xFFFFFFFF;
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/* Write EMC's DRAM op into PMC scratch. */
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if ((EMC_FBIO_CFG5_0 & 3) != 1) {
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/* If DRAM_TYPE != LPDDR4, something's gone wrong. Reboot. */
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@ -77,29 +78,29 @@ void lp0_entry_main(void) {
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uint32_t mrw3_op = ((EMC_MRW3_0 & 0xC0) << 8) | (EMC_MRW3_0 & 0xC0);
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APBDEV_PMC_SCRATCH12_0 = (APBDEV_PMC_SCRATCH12_0 & 0xFFFF3F3F) | mrw3_op;
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APBDEV_PMC_SCRATCH13_0 = (APBDEV_PMC_SCRATCH13_0 & 0xFFFF3F3F) | mrw3_op;
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/* Ready DRAM for deep sleep. */
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emc_put_dram_in_self_refresh_mode();
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/* Setup LPDDR MRW based on device config. */
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EMC_MRW_0 = 0x88110000;
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if (EMC_ADR_CFG_0 & 1) {
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EMC_MRW_0 = 0x48110000;
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}
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/* Put IO pads in Deep Power Down. */
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set_pmc_dpd_io_pads();
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/* Enable pad sampling during deep sleep. */
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APBDEV_PMC_DPD_SAMPLE_0 |= 1;
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/* Waste some more time. */
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spinlock_wait(0x128);
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/* Enter deep sleep. */
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APBDEV_PMC_DPD_ENABLE_0 |= 1;
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while (1) { /* Wait until we're asleep. */ }
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while (true) { /* Wait until we're asleep. */ }
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}
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@ -10,19 +10,15 @@ _start:
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.type crt0, %function
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crt0:
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@ setup to call lp0_entry_main
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msr cpsr_f, #0xC0
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msr cpsr_cf, #0xD3
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msr cpsr_cxsf, #0xD3
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ldr sp, =__stack_top__
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ldr lr, =reboot
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bl lp0_entry_main
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infloop:
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b infloop
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b lp0_entry_main
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.global spinlock_wait
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.type spinlock_wait, %function
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spinlock_wait:
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sub r0, r0, #1
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cmp r0, #0
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subs r0, r0, #1
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bgt spinlock_wait
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bx lr
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bx lr
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