warmboot: add ram config

exosphere/lp0fw/src/emc.c

@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2018 Atmosphère-NX
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "utils.h"
+#include "lp0.h"
+#include "emc.h"
+#include "pmc.h"
+#include "timer.h"
+
+void emc_configure_pmacro_training(void) {
+    /* Set DISABLE_CFG_BYTEN for all N. */
+    EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0xFF0000;
+    
+    /* Set CHN_TRAINING_E_WRPTR for channel 0 + channel 1. */
+    EMC_PMACRO_TRAINING_CTRL_0_0 = 8;
+    EMC_PMACRO_TRAINING_CTRL_1_0 = 8;
+    
+    /* Clear DISABLE_CFG_BYTEN for all N. */
+    EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x0;
+}

exosphere/lp0fw/src/emc.h

@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2018 Atmosphère-NX
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+ 
+#ifndef EXOSPHERE_WARMBOOT_BIN_EMC_H
+#define EXOSPHERE_WARMBOOT_BIN_EMC_H
+
+#include "utils.h"
+
+#define EMC_BASE (0x7001B000)
+
+#define EMC0_BASE (0x7001E000)
+#define EMC1_BASE (0x7001F000)
+
+
+#define MAKE_EMC_REG(ofs) (MAKE_REG32(EMC_BASE + ofs))
+
+#define MAKE_EMC0_REG(ofs) (MAKE_REG32(EMC0_BASE + ofs))
+#define MAKE_EMC1_REG(ofs) (MAKE_REG32(EMC1_BASE + ofs))
+
+#define EMC_CFG_0                    MAKE_EMC_REG(0x00C)
+
+#define EMC_ADR_CFG_0                MAKE_EMC_REG(0x10)
+
+#define EMC_TIMING_CONTROL_0         MAKE_EMC_REG(0x028)
+
+#define EMC_SELF_REF_0               MAKE_EMC_REG(0x0E0)
+
+#define EMC_MRW_0                    MAKE_EMC_REG(0x0E8)
+
+#define EMC_FBIO_CFG5_0              MAKE_EMC_REG(0x104)
+
+#define EMC_MRW3_0                   MAKE_EMC_REG(0x138)
+
+#define EMC_AUTO_CAL_CONFIG_0        MAKE_EMC_REG(0x2A4)
+
+#define EMC_REQ_CTRL_0               MAKE_EMC_REG(0x2B0)
+
+#define EMC_EMC_STATUS_0             MAKE_EMC_REG(0x2B4)
+#define EMC0_EMC_STATUS_0            MAKE_EMC0_REG(0x2B4)
+#define EMC1_EMC_STATUS_0            MAKE_EMC1_REG(0x2B4)
+
+#define EMC_CFG_DIG_DLL_0            MAKE_EMC_REG(0x2BC)
+#define EMC0_CFG_DIG_DLL_0           MAKE_EMC0_REG(0x2BC)
+#define EMC1_CFG_DIG_DLL_0           MAKE_EMC1_REG(0x2BC)
+
+#define EMC_ZCAL_INTERVAL_0          MAKE_EMC_REG(0x2E0)
+
+#define EMC_PMC_SCRATCH3_0           MAKE_EMC_REG(0x448)
+
+#define EMC_FBIO_CFG7_0              MAKE_EMC_REG(0x584)
+
+#define EMC_PMACRO_CFG_PM_GLOBAL_0_0 MAKE_EMC_REG(0xC30)
+#define EMC_PMACRO_TRAINING_CTRL_0_0 MAKE_EMC_REG(0xCF8)
+#define EMC_PMACRO_TRAINING_CTRL_1_0 MAKE_EMC_REG(0xCFC)
+
+void emc_configure_pmacro_training(void);
+
+#endif

exosphere/lp0fw/src/lp0.c

@@ -20,6 +20,8 @@
 #include "pmc.h"
 #include "misc.h"
 #include "fuse.h"
+#include "car.h"
+#include "emc.h"
 #include "timer.h"
 
 void reboot(void) {
@@ -43,7 +45,7 @@ void lp0_entry_main(warmboot_metadata_t *meta) {
     }
     
     /* Configure debugging depending on FUSE_PRODUCTION_MODE */
-    configure_device_dbg_settings();
+    misc_configure_device_dbg_settings();
     
     /* Check for downgrade. */
     /* NOTE: We implemented this as "return false" */
@@ -64,6 +66,12 @@ void lp0_entry_main(warmboot_metadata_t *meta) {
     /* Setup fuses, disable bypass. */
     fuse_configure_fuse_bypass();
     
+    /* Configure oscillators/timing in CAR. */
+    car_configure_oscillators();
+    
+    /* Restore RAM configuration. */
+    misc_restore_ram_svop();
+    emc_configure_pmacro_training();
     
     /* TODO: stuff */
 

exosphere/lp0fw/src/misc.c

@@ -22,7 +22,7 @@
 #include "sysreg.h"
 #include "pmc.h"
 
-void configure_device_dbg_settings(void) {
+void misc_configure_device_dbg_settings(void) {
     /* Enable RTCK daisychaining by setting TBE bit. */
     APB_MISC_PP_CONFIG_CTL_0 = 0x80;
     
@@ -45,3 +45,8 @@ void configure_device_dbg_settings(void) {
     /* Set E_INPUT in PINMUX_AUX_GPIO_PA6_0 */
     PINMUX_AUX_GPIO_PA6_0 |= 0x40;
 }
+
+void misc_restore_ram_svop(void) {
+    /* This sets CFG2TMC_RAM_SVOP_PDP to 0x2. */
+    APB_MISC_GP_ASDBGREG_0 |= 0x02000000;
+}

exosphere/lp0fw/src/misc.h

@@ -27,9 +27,12 @@
 
 #define APB_MISC_PP_CONFIG_CTL_0 MAKE_MISC_REG(0x024)
 
+#define APB_MISC_GP_ASDBGREG_0 MAKE_MISC_REG(0x810)
 
 #define PINMUX_AUX_GPIO_PA6_0 MAKE_MISC_REG(0x3244)
 
-void configure_device_dbg_settings(void);
+void misc_configure_device_dbg_settings(void);
+
+void misc_restore_ram_svop(void);
 
 #endif