mirror of
https://github.com/Atmosphere-NX/Atmosphere
synced 2024-12-31 17:31:15 +00:00
dmnt-cheat: Add opcode to store register to memory
This commit is contained in:
Michael Scire
parent
88a6ef4cd7
commit
8c86074da2
2 changed files with 127 additions and 27 deletions
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@ -95,15 +95,15 @@ void DmntCheatVm::LogOpcode(const CheatVmOpcode *opcode) {
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this->LogToDebugFile("From Reg: %d\n", opcode->ldr_memory.load_from_reg);
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this->LogToDebugFile("Rel Addr: %lx\n", opcode->ldr_memory.rel_address);
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break;
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case CheatVmOpcodeType_StoreToRegisterAddress:
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this->LogToDebugFile("Opcode: Store Static to Register Address\n");
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this->LogToDebugFile("Bit Width: %x\n", opcode->str_regaddr.bit_width);
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this->LogToDebugFile("Reg Idx: %x\n", opcode->str_regaddr.reg_index);
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if (opcode->str_regaddr.add_offset_reg) {
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this->LogToDebugFile("O Reg Idx: %x\n", opcode->str_regaddr.offset_reg_index);
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case CheatVmOpcodeType_StoreStaticToAddress:
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this->LogToDebugFile("Opcode: Store Static to Address\n");
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this->LogToDebugFile("Bit Width: %x\n", opcode->str_static.bit_width);
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this->LogToDebugFile("Reg Idx: %x\n", opcode->str_static.reg_index);
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if (opcode->str_static.add_offset_reg) {
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this->LogToDebugFile("O Reg Idx: %x\n", opcode->str_static.offset_reg_index);
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}
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this->LogToDebugFile("Incr Reg: %d\n", opcode->str_regaddr.increment_reg);
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this->LogToDebugFile("Value: %lx\n", opcode->str_regaddr.value);
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this->LogToDebugFile("Incr Reg: %d\n", opcode->str_static.increment_reg);
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this->LogToDebugFile("Value: %lx\n", opcode->str_static.value);
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break;
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case CheatVmOpcodeType_PerformArithmeticStatic:
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this->LogToDebugFile("Opcode: Perform Static Arithmetic\n");
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@ -127,6 +127,23 @@ void DmntCheatVm::LogOpcode(const CheatVmOpcode *opcode) {
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this->LogToDebugFile("Src2 Idx: %x\n", opcode->perform_math_reg.src_reg_2_index);
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}
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break;
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case CheatVmOpcodeType_StoreRegisterToAddress:
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this->LogToDebugFile("Opcode: Store Register to Address\n");
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this->LogToDebugFile("Bit Width: %x\n", opcode->str_register.bit_width);
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this->LogToDebugFile("S Reg Idx: %x\n", opcode->str_register.str_reg_index);
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this->LogToDebugFile("A Reg Idx: %x\n", opcode->str_register.addr_reg_index);
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this->LogToDebugFile("Incr Reg: %d\n", opcode->str_register.increment_reg);
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switch (opcode->str_register.ofs_type) {
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case StoreRegisterOffsetType_None:
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break;
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case StoreRegisterOffsetType_Reg:
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this->LogToDebugFile("O Reg Idx: %x\n", opcode->str_register.ofs_reg_index);
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break;
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case StoreRegisterOffsetType_Imm:
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this->LogToDebugFile("Rel Addr: %lx\n", opcode->str_register.rel_address);
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break;
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}
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break;
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default:
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this->LogToDebugFile("Unknown opcode: %x\n", opcode->opcode);
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break;
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@ -252,16 +269,16 @@ bool DmntCheatVm::DecodeNextOpcode(CheatVmOpcode *out) {
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opcode.ldr_memory.rel_address = ((u64)(first_dword & 0xFF) << 32ul) | ((u64)second_dword);
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}
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break;
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case CheatVmOpcodeType_StoreToRegisterAddress:
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case CheatVmOpcodeType_StoreStaticToAddress:
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{
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/* 6T0RIor0 VVVVVVVV VVVVVVVV */
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/* Read additional words. */
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opcode.str_regaddr.bit_width = (first_dword >> 24) & 0xF;
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opcode.str_regaddr.reg_index = ((first_dword >> 16) & 0xF);
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opcode.str_regaddr.increment_reg = ((first_dword >> 12) & 0xF) != 0;
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opcode.str_regaddr.add_offset_reg = ((first_dword >> 8) & 0xF) != 0;
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opcode.str_regaddr.offset_reg_index = ((first_dword >> 4) & 0xF);
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opcode.str_regaddr.value = (((u64)GetNextDword()) << 32ul) | ((u64)GetNextDword());
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opcode.str_static.bit_width = (first_dword >> 24) & 0xF;
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opcode.str_static.reg_index = ((first_dword >> 16) & 0xF);
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opcode.str_static.increment_reg = ((first_dword >> 12) & 0xF) != 0;
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opcode.str_static.add_offset_reg = ((first_dword >> 8) & 0xF) != 0;
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opcode.str_static.offset_reg_index = ((first_dword >> 4) & 0xF);
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opcode.str_static.value = (((u64)GetNextDword()) << 32ul) | ((u64)GetNextDword());
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}
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break;
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case CheatVmOpcodeType_PerformArithmeticStatic:
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@ -297,6 +314,37 @@ bool DmntCheatVm::DecodeNextOpcode(CheatVmOpcode *out) {
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}
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}
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break;
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case CheatVmOpcodeType_StoreRegisterToAddress:
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{
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/* ATSRIOra (aaaaaaaa) */
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/* A = opcode 10 */
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/* T = bit width */
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/* S = src register index */
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/* R = address register index */
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/* I = 1 if increment address register, 0 if not increment address register */
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/* O = offset type, 0 = None, 1 = Register, 2 = Immediate */
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/* r = offset register (for offset type 1) */
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/* a = relative address (for offset type 2) */
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opcode.str_register.bit_width = (first_dword >> 24) & 0xF;
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opcode.str_register.str_reg_index = ((first_dword >> 20) & 0xF);
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opcode.str_register.addr_reg_index = ((first_dword >> 16) & 0xF);
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opcode.str_register.increment_reg = ((first_dword >> 12) & 0xF) != 0;
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opcode.str_register.ofs_type = (StoreRegisterOffsetType)(((first_dword >> 8) & 0xF));
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opcode.str_register.ofs_reg_index = ((first_dword >> 4) & 0xF);
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switch (opcode.str_register.ofs_type) {
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case StoreRegisterOffsetType_None:
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case StoreRegisterOffsetType_Reg:
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/* Nothing more to do */
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break;
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case StoreRegisterOffsetType_Imm:
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opcode.str_register.rel_address = (((u64)(first_dword & 0xF) << 32ul) | ((u64)GetNextDword()));
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break;
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default:
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opcode.str_register.ofs_type = StoreRegisterOffsetType_None;
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break;
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}
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}
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break;
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case CheatVmOpcodeType_ExtendedWidth:
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default:
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/* Unrecognized instruction cannot be decoded. */
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@ -502,26 +550,26 @@ void DmntCheatVm::Execute(const CheatProcessMetadata *metadata) {
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}
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}
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break;
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case CheatVmOpcodeType_StoreToRegisterAddress:
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case CheatVmOpcodeType_StoreStaticToAddress:
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{
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/* Calculate address. */
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u64 dst_address = this->registers[cur_opcode.str_regaddr.reg_index];
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u64 dst_value = cur_opcode.str_regaddr.value;
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if (cur_opcode.str_regaddr.add_offset_reg) {
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dst_address += this->registers[cur_opcode.str_regaddr.offset_reg_index];
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u64 dst_address = this->registers[cur_opcode.str_static.reg_index];
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u64 dst_value = cur_opcode.str_static.value;
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if (cur_opcode.str_static.add_offset_reg) {
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dst_address += this->registers[cur_opcode.str_static.offset_reg_index];
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}
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/* Write value to memory. Gateway only writes on valid bitwidth. */
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switch (cur_opcode.str_regaddr.bit_width) {
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switch (cur_opcode.str_static.bit_width) {
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case 1:
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case 2:
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case 4:
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case 8:
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DmntCheatManager::WriteCheatProcessMemoryForVm(dst_address, &dst_value, cur_opcode.str_regaddr.bit_width);
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DmntCheatManager::WriteCheatProcessMemoryForVm(dst_address, &dst_value, cur_opcode.str_static.bit_width);
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break;
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}
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/* Increment register if relevant. */
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if (cur_opcode.str_regaddr.increment_reg) {
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this->registers[cur_opcode.str_regaddr.reg_index] += cur_opcode.str_regaddr.bit_width;
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if (cur_opcode.str_static.increment_reg) {
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this->registers[cur_opcode.str_static.reg_index] += cur_opcode.str_static.bit_width;
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}
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}
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break;
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@ -635,6 +683,39 @@ void DmntCheatVm::Execute(const CheatProcessMetadata *metadata) {
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this->registers[cur_opcode.perform_math_reg.dst_reg_index] = res_val;
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}
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break;
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case CheatVmOpcodeType_StoreRegisterToAddress:
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{
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/* Calculate address. */
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u64 dst_value = this->registers[cur_opcode.str_register.str_reg_index];
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u64 dst_address = this->registers[cur_opcode.str_register.addr_reg_index];
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switch (cur_opcode.str_register.ofs_type) {
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case StoreRegisterOffsetType_None:
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/* Nothing more to do */
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break;
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case StoreRegisterOffsetType_Reg:
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dst_address += this->registers[cur_opcode.str_register.ofs_reg_index];
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break;
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case StoreRegisterOffsetType_Imm:
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dst_address += cur_opcode.str_register.rel_address;
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break;
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}
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/* Write value to memory. Write only on valid bitwidth. */
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switch (cur_opcode.str_register.bit_width) {
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case 1:
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case 2:
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case 4:
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case 8:
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DmntCheatManager::WriteCheatProcessMemoryForVm(dst_address, &dst_value, cur_opcode.str_register.bit_width);
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break;
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}
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/* Increment register if relevant. */
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if (cur_opcode.str_register.increment_reg) {
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this->registers[cur_opcode.str_register.addr_reg_index] += cur_opcode.str_register.bit_width;
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}
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}
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break;
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default:
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/* By default, we do a no-op. */
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break;
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@ -28,12 +28,13 @@ enum CheatVmOpcodeType : u32 {
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CheatVmOpcodeType_ControlLoop = 3,
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CheatVmOpcodeType_LoadRegisterStatic = 4,
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CheatVmOpcodeType_LoadRegisterMemory = 5,
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CheatVmOpcodeType_StoreToRegisterAddress = 6,
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CheatVmOpcodeType_StoreStaticToAddress = 6,
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CheatVmOpcodeType_PerformArithmeticStatic = 7,
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CheatVmOpcodeType_BeginKeypressConditionalBlock = 8,
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/* These are not implemented by Gateway's VM. */
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CheatVmOpcodeType_PerformArithmeticRegister = 9,
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CheatVmOpcodeType_StoreRegisterToAddress = 10,
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/* This is a meta entry, and not a real opcode. */
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/* This is to facilitate multi-nybble instruction decoding in the future. */
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@ -70,6 +71,12 @@ enum RegisterArithmeticType : u32 {
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RegisterArithmeticType_None = 9,
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};
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enum StoreRegisterOffsetType : u32 {
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StoreRegisterOffsetType_None = 0,
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StoreRegisterOffsetType_Reg = 1,
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StoreRegisterOffsetType_Imm = 2,
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};
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union VmInt {
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u8 bit8;
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u16 bit16;
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@ -114,7 +121,7 @@ struct LoadRegisterMemoryOpcode {
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u64 rel_address;
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};
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struct StoreToRegisterAddressOpcode {
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struct StoreStaticToAddressOpcode {
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u32 bit_width;
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u32 reg_index;
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bool increment_reg;
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@ -144,6 +151,17 @@ struct PerformArithmeticRegisterOpcode {
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VmInt value;
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};
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struct StoreRegisterToAddressOpcode {
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u32 bit_width;
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u32 str_reg_index;
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u32 addr_reg_index;
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bool increment_reg;
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StoreRegisterOffsetType ofs_type;
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u32 ofs_reg_index;
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u64 rel_address;
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};
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struct CheatVmOpcode {
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CheatVmOpcodeType opcode;
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union {
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@ -153,10 +171,11 @@ struct CheatVmOpcode {
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ControlLoopOpcode ctrl_loop;
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LoadRegisterStaticOpcode ldr_static;
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LoadRegisterMemoryOpcode ldr_memory;
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StoreToRegisterAddressOpcode str_regaddr;
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StoreStaticToAddressOpcode str_static;
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PerformArithmeticStaticOpcode perform_math_static;
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BeginKeypressConditionalOpcode begin_keypress_cond;
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PerformArithmeticRegisterOpcode perform_math_reg;
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StoreRegisterToAddressOpcode str_register;
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};
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};
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